From f20f95cf0e7f7788a43d0ca91e384c613380169d Mon Sep 17 00:00:00 2001 From: jihye kim Date: Thu, 12 Sep 2013 14:58:59 +0900 Subject: [PATCH] apply modification of piix4.c to maru_pm.c Change-Id: Ib611c6afb30802818389ec59c3bdba109634fffd Signed-off-by: jihye kim --- tizen/src/hw/maru_pm.c | 64 ++++++++++++++++++++++++------------------ tizen/src/hw/maru_pm.h | 2 +- 2 files changed, 37 insertions(+), 29 deletions(-) diff --git a/tizen/src/hw/maru_pm.c b/tizen/src/hw/maru_pm.c index 4f9bc35c19..65065227cf 100644 --- a/tizen/src/hw/maru_pm.c +++ b/tizen/src/hw/maru_pm.c @@ -1,6 +1,6 @@ /* * Maru power management emulator - * Based on qemu/hw/acpi_piix4.c + * Based on qemu/hw/acpi/piix4.c * * Copyright (C) 2011 - 2012 Samsung Electronics Co., Ltd. All rights reserved. * @@ -82,7 +82,7 @@ typedef struct CPUStatus { typedef struct PIIX4PMState { - PCIDevice dev; + PCIDevice parent_obj; MemoryRegion io; MemoryRegion io_gpe; @@ -116,6 +116,11 @@ typedef struct PIIX4PMState { static int is_suspended; +#define TYPE_PIIX4_PM "MARU_PM" + +#define PIIX4_PM(obj) \ + OBJECT_CHECK(PIIX4PMState, (obj), TYPE_PIIX4_PM) + static void piix4_acpi_system_hot_add_init(MemoryRegion *parent, PCIBus *bus, PIIX4PMState *s); #define ACPI_ENABLE 0xf1 @@ -201,11 +206,12 @@ static const MemoryRegionOps maru_pm_cnt_ops = { static void apm_ctrl_changed(uint32_t val, void *arg) { PIIX4PMState *s = arg; + PCIDevice *d = PCI_DEVICE(s); /* ACPI specs 3.0, 4.7.2.5 */ acpi_pm1_cnt_update(&s->ar, val == ACPI_ENABLE, val == ACPI_DISABLE); - if (s->dev.config[0x5b] & (1 << 1)) { + if (d->config[0x5b] & (1 << 1)) { if (s->smi_irq) { qemu_irq_raise(s->smi_irq); } @@ -214,24 +220,27 @@ static void apm_ctrl_changed(uint32_t val, void *arg) static void pm_io_space_update(PIIX4PMState *s) { + PCIDevice *d = PCI_DEVICE(s); uint32_t pm_io_base; - pm_io_base = le32_to_cpu(*(uint32_t *)(s->dev.config + 0x40)); + pm_io_base = le32_to_cpu(*(uint32_t *)(d->config + 0x40)); pm_io_base &= 0xffc0; memory_region_transaction_begin(); - memory_region_set_enabled(&s->io, s->dev.config[0x80] & 1); + memory_region_set_enabled(&s->io, d->config[0x80] & 1); memory_region_set_address(&s->io, pm_io_base); memory_region_transaction_commit(); } static void smbus_io_space_update(PIIX4PMState *s) { - s->smb_io_base = le32_to_cpu(*(uint32_t *)(s->dev.config + 0x90)); + PCIDevice *d = PCI_DEVICE(s); + + s->smb_io_base = le32_to_cpu(*(uint32_t *)(d->config + 0x90)); s->smb_io_base &= 0xffc0; memory_region_transaction_begin(); - memory_region_set_enabled(&s->smb.io, s->dev.config[0xd2] & 1); + memory_region_set_enabled(&s->smb.io, d->config[0xd2] & 1); memory_region_set_address(&s->smb.io, s->smb_io_base); memory_region_transaction_commit(); } @@ -310,7 +319,7 @@ static int acpi_load_old(QEMUFile *f, void *opaque, int version_id) int ret, i; uint16_t temp; - ret = pci_device_load(&s->dev, f); + ret = pci_device_load(PCI_DEVICE(s), f); if (ret < 0) { return ret; } @@ -354,7 +363,7 @@ static const VMStateDescription vmstate_acpi = { .load_state_old = acpi_load_old, .post_load = vmstate_acpi_post_load, .fields = (VMStateField []) { - VMSTATE_PCI_DEVICE(dev, PIIX4PMState), + VMSTATE_PCI_DEVICE(parent_obj, PIIX4PMState), VMSTATE_UINT16(ar.pm1.evt.sts, PIIX4PMState), VMSTATE_UINT16(ar.pm1.evt.en, PIIX4PMState), VMSTATE_UINT16(ar.pm1.cnt.cnt, PIIX4PMState), @@ -371,7 +380,7 @@ static const VMStateDescription vmstate_acpi = { static void acpi_piix_eject_slot(PIIX4PMState *s, unsigned slots) { BusChild *kid, *next; - BusState *bus = qdev_get_parent_bus(&s->dev.qdev); + BusState *bus = qdev_get_parent_bus(DEVICE(s)); int slot = ffs(slots) - 1; bool slot_free = true; @@ -397,8 +406,7 @@ static void acpi_piix_eject_slot(PIIX4PMState *s, unsigned slots) static void piix4_update_hotplug(PIIX4PMState *s) { - PCIDevice *dev = &s->dev; - BusState *bus = qdev_get_parent_bus(&dev->qdev); + BusState *bus = qdev_get_parent_bus(DEVICE(s)); BusChild *kid, *next; /* Execute any pending removes during reset */ @@ -426,7 +434,8 @@ static void piix4_update_hotplug(PIIX4PMState *s) static void piix4_reset(void *opaque) { PIIX4PMState *s = opaque; - uint8_t *pci_conf = s->dev.config; + PCIDevice *d = PCI_DEVICE(s); + uint8_t *pci_conf = d->config; pci_conf[0x58] = 0; pci_conf[0x59] = 0; @@ -468,10 +477,10 @@ static void piix4_pm_machine_ready(Notifier *n, void *opaque) static int piix4_pm_initfn(PCIDevice *dev) { - PIIX4PMState *s = DO_UPCAST(PIIX4PMState, dev, dev); + PIIX4PMState *s = PIIX4_PM(dev); uint8_t *pci_conf; - pci_conf = s->dev.config; + pci_conf = dev->config; pci_conf[0x06] = 0x80; pci_conf[0x07] = 0x02; pci_conf[0x09] = 0x00; @@ -493,7 +502,7 @@ static int piix4_pm_initfn(PCIDevice *dev) pci_conf[0x90] = s->smb_io_base | 1; pci_conf[0x91] = s->smb_io_base >> 8; pci_conf[0xd2] = 0x09; - pm_smbus_init(&s->dev.qdev, &s->smb); + pm_smbus_init(DEVICE(dev), &s->smb); memory_region_set_enabled(&s->smb.io, pci_conf[0xd2] & 1); memory_region_add_subregion(pci_address_space_io(dev), s->smb_io_base, &s->smb.io); @@ -525,20 +534,20 @@ static int piix4_pm_initfn(PCIDevice *dev) i2c_bus *maru_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base, qemu_irq sci_irq, qemu_irq smi_irq, - int kvm_enabled, void *fw_cfg) + int kvm_enabled, FWCfgState *fw_cfg) { - PCIDevice *dev; + DeviceState *dev; PIIX4PMState *s; - dev = pci_create(bus, devfn, "MARU_PM"); - qdev_prop_set_uint32(&dev->qdev, "smb_io_base", smb_io_base); + dev = DEVICE(pci_create(bus, devfn, TYPE_PIIX4_PM)); + qdev_prop_set_uint32(dev, "smb_io_base", smb_io_base); - s = DO_UPCAST(PIIX4PMState, dev, dev); + s = PIIX4_PM(dev); s->irq = sci_irq; s->smi_irq = smi_irq; s->kvm_enabled = kvm_enabled; - qdev_init_nofail(&dev->qdev); + qdev_init_nofail(dev); if (fw_cfg) { uint8_t suspend[6] = {128, 0, 0, 129, 128, 128}; @@ -577,8 +586,8 @@ static void piix4_pm_class_init(ObjectClass *klass, void *data) dc->props = piix4_pm_properties; } -static TypeInfo piix4_pm_info = { - .name = "MARU_PM", +static const TypeInfo piix4_pm_info = { + .name = TYPE_PIIX4_PM, .parent = TYPE_PCI_DEVICE, .instance_size = sizeof(PIIX4PMState), .class_init = piix4_pm_class_init, @@ -596,7 +605,7 @@ static uint64_t gpe_readb(void *opaque, hwaddr addr, unsigned width) PIIX4PMState *s = opaque; uint32_t val = acpi_gpe_ioport_readb(&s->ar, addr); - PIIX4_DPRINTF("gpe read %x == %x\n", addr, val); + PIIX4_DPRINTF("gpe read %" HWADDR_PRIx " == %" PRIu32 "\n", addr, val); return val; } @@ -608,7 +617,7 @@ static void gpe_writeb(void *opaque, hwaddr addr, uint64_t val, acpi_gpe_ioport_writeb(&s->ar, addr, val); pm_update_sci(s); - PIIX4_DPRINTF("gpe write %x <== %d\n", addr, val); + PIIX4_DPRINTF("gpe write %" HWADDR_PRIx " <== %" PRIu64 "\n", addr, val); } static const MemoryRegionOps piix4_gpe_ops = { @@ -782,8 +791,7 @@ static int piix4_device_hotplug(DeviceState *qdev, PCIDevice *dev, PCIHotplugState state) { int slot = PCI_SLOT(dev->devfn); - PIIX4PMState *s = DO_UPCAST(PIIX4PMState, dev, - PCI_DEVICE(qdev)); + PIIX4PMState *s = PIIX4_PM(qdev); /* Don't send event when device is enabled during qemu machine creation: * it is present on boot, no hotplug event is necessary. We do send an diff --git a/tizen/src/hw/maru_pm.h b/tizen/src/hw/maru_pm.h index e309b01564..1ee85508c2 100644 --- a/tizen/src/hw/maru_pm.h +++ b/tizen/src/hw/maru_pm.h @@ -35,7 +35,7 @@ i2c_bus *maru_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base, qemu_irq sci_irq, qemu_irq smi_irq, - int kvm_enabled, void *fw_cfg); + int kvm_enabled, FWCfgState *fw_cfg); #ifdef TARGET_ARM static int is_suspended_state( void ) -- 2.34.1