From f1df2d8eaf188eec2971b12e57c821a0db5f3a36 Mon Sep 17 00:00:00 2001 From: Roman Lebedev Date: Sat, 2 Oct 2021 13:39:10 +0300 Subject: [PATCH] [X86][Costmodel] Load/store i8 Stride=3 VF=4 interleaving costs While we already model this tuple, the values are divergent from reality, so fix them. The only sched models that for cpu's that support avx2 but not avx512 are: haswell, broadwell, skylake, zen1-3 For load we have: https://godbolt.org/z/obWz3PrfK - for intels `Block RThroughput: =3.0`; for ryzens, `Block RThroughput: <=1.5` So pick cost of `3`. For store we have: https://godbolt.org/z/orjPshn3h - for intels `Block RThroughput: =4.0`; for ryzens, `Block RThroughput: <=2.0` So pick cost of `4`. I'm directly using the shuffling asm the llc produced, without any manual fixups that may be needed to ensure sequential execution. Reviewed By: RKSimon Differential Revision: https://reviews.llvm.org/D110958 --- llvm/lib/Target/X86/X86TargetTransformInfo.cpp | 4 ++-- llvm/test/Analysis/CostModel/X86/interleaved-load-i8-stride-3.ll | 2 +- llvm/test/Analysis/CostModel/X86/interleaved-store-i8-stride-3.ll | 2 +- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/llvm/lib/Target/X86/X86TargetTransformInfo.cpp b/llvm/lib/Target/X86/X86TargetTransformInfo.cpp index 4c3f4da..f2e4695 100644 --- a/llvm/lib/Target/X86/X86TargetTransformInfo.cpp +++ b/llvm/lib/Target/X86/X86TargetTransformInfo.cpp @@ -5087,7 +5087,7 @@ InstructionCost X86TTIImpl::getInterleavedMemoryOpCostAVX2( {2, MVT::v16i64, 16}, // (load 32i64 and) deinterleave into 2 x 16i64 {3, MVT::v2i8, 3}, // (load 6i8 and) deinterleave into 3 x 2i8 - {3, MVT::v4i8, 4}, // (load 12i8 and) deinterleave into 3 x 4i8 + {3, MVT::v4i8, 3}, // (load 12i8 and) deinterleave into 3 x 4i8 {3, MVT::v8i8, 9}, // (load 24i8 and) deinterleave into 3 x 8i8 {3, MVT::v16i8, 11}, // (load 48i8 and) deinterleave into 3 x 16i8 {3, MVT::v32i8, 13}, // (load 96i8 and) deinterleave into 3 x 32i8 @@ -5139,7 +5139,7 @@ InstructionCost X86TTIImpl::getInterleavedMemoryOpCostAVX2( {2, MVT::v16i64, 16}, // interleave 2 x 16i64 into 32i64 (and store) {3, MVT::v2i8, 4}, // interleave 3 x 2i8 into 6i8 (and store) - {3, MVT::v4i8, 8}, // interleave 3 x 4i8 into 12i8 (and store) + {3, MVT::v4i8, 4}, // interleave 3 x 4i8 into 12i8 (and store) {3, MVT::v8i8, 11}, // interleave 3 x 8i8 into 24i8 (and store) {3, MVT::v16i8, 11}, // interleave 3 x 16i8 into 48i8 (and store) {3, MVT::v32i8, 13}, // interleave 3 x 32i8 into 96i8 (and store) diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-load-i8-stride-3.ll b/llvm/test/Analysis/CostModel/X86/interleaved-load-i8-stride-3.ll index ed6daac..e8feb4f 100644 --- a/llvm/test/Analysis/CostModel/X86/interleaved-load-i8-stride-3.ll +++ b/llvm/test/Analysis/CostModel/X86/interleaved-load-i8-stride-3.ll @@ -27,7 +27,7 @@ target triple = "x86_64-unknown-linux-gnu" ; ; AVX2: LV: Found an estimated cost of 1 for VF 1 For instruction: %v0 = load i8, i8* %in0, align 1 ; AVX2: LV: Found an estimated cost of 6 for VF 2 For instruction: %v0 = load i8, i8* %in0, align 1 -; AVX2: LV: Found an estimated cost of 7 for VF 4 For instruction: %v0 = load i8, i8* %in0, align 1 +; AVX2: LV: Found an estimated cost of 6 for VF 4 For instruction: %v0 = load i8, i8* %in0, align 1 ; AVX2: LV: Found an estimated cost of 12 for VF 8 For instruction: %v0 = load i8, i8* %in0, align 1 ; AVX2: LV: Found an estimated cost of 13 for VF 16 For instruction: %v0 = load i8, i8* %in0, align 1 ; AVX2: LV: Found an estimated cost of 16 for VF 32 For instruction: %v0 = load i8, i8* %in0, align 1 diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-store-i8-stride-3.ll b/llvm/test/Analysis/CostModel/X86/interleaved-store-i8-stride-3.ll index c0da095..f939d05 100644 --- a/llvm/test/Analysis/CostModel/X86/interleaved-store-i8-stride-3.ll +++ b/llvm/test/Analysis/CostModel/X86/interleaved-store-i8-stride-3.ll @@ -27,7 +27,7 @@ target triple = "x86_64-unknown-linux-gnu" ; ; AVX2: LV: Found an estimated cost of 1 for VF 1 For instruction: store i8 %v2, i8* %out2, align 1 ; AVX2: LV: Found an estimated cost of 7 for VF 2 For instruction: store i8 %v2, i8* %out2, align 1 -; AVX2: LV: Found an estimated cost of 11 for VF 4 For instruction: store i8 %v2, i8* %out2, align 1 +; AVX2: LV: Found an estimated cost of 7 for VF 4 For instruction: store i8 %v2, i8* %out2, align 1 ; AVX2: LV: Found an estimated cost of 14 for VF 8 For instruction: store i8 %v2, i8* %out2, align 1 ; AVX2: LV: Found an estimated cost of 13 for VF 16 For instruction: store i8 %v2, i8* %out2, align 1 ; AVX2: LV: Found an estimated cost of 16 for VF 32 For instruction: store i8 %v2, i8* %out2, align 1 -- 2.7.4