From f1b20c52251af54413ca5b990db2b29d9418e256 Mon Sep 17 00:00:00 2001 From: Matthias Braun Date: Wed, 24 Aug 2016 22:17:45 +0000 Subject: [PATCH] MachineRegisterInfo/MIR: Initialize tracksSubRegLiveness early, do not print/parser it tracksSubRegLiveness only depends on the Subtarget and a cl::opt, there is not need to change it or save/parse it in a .mir file. Make the field const and move the initialization LiveIntervalAnalysis to the MachineRegisterInfo constructor. Also cleanup some code and fix some instances which better use MachineRegisterInfo::subRegLivenessEnabled() instead of TargetSubtargetInfo::enableSubRegLiveness(). llvm-svn: 279676 --- llvm/include/llvm/CodeGen/MIRYamlMapping.h | 2 -- llvm/include/llvm/CodeGen/MachineRegisterInfo.h | 6 +----- llvm/include/llvm/Target/TargetSubtargetInfo.h | 2 ++ llvm/lib/CodeGen/DetectDeadLanes.cpp | 4 ++-- llvm/lib/CodeGen/LiveIntervalAnalysis.cpp | 7 ------- llvm/lib/CodeGen/MIRParser/MIRParser.cpp | 1 - llvm/lib/CodeGen/MIRPrinter.cpp | 1 - llvm/lib/CodeGen/MachineRegisterInfo.cpp | 7 ++++++- llvm/lib/CodeGen/RenameIndependentSubregs.cpp | 4 ++-- llvm/test/CodeGen/AArch64/ldst-opt-dbg-limit.mir | 2 -- llvm/test/CodeGen/AArch64/movimm-wzr.mir | 1 - llvm/test/CodeGen/ARM/ARMLoadStoreDBG.mir | 1 - llvm/test/CodeGen/MIR/AArch64/inst-size-tlsdesc-callseq.mir | 1 - llvm/test/CodeGen/MIR/AMDGPU/expected-target-index-name.mir | 3 +-- llvm/test/CodeGen/MIR/AMDGPU/invalid-target-index-operand.mir | 3 +-- llvm/test/CodeGen/MIR/AMDGPU/target-index-operands.mir | 6 ++---- llvm/test/CodeGen/MIR/ARM/sched-it-debug-nodes.mir | 1 - llvm/test/CodeGen/MIR/Generic/register-info.mir | 3 --- llvm/test/CodeGen/MIR/Lanai/peephole-compare.mir | 9 --------- llvm/test/CodeGen/PowerPC/aantidep-def-ec.mir | 1 - llvm/test/CodeGen/PowerPC/addisdtprelha-nonr3.mir | 1 - llvm/test/CodeGen/PowerPC/no-rlwimi-trivial-commute.mir | 1 - llvm/test/CodeGen/PowerPC/opt-sub-inst-cr0-live.mir | 1 - llvm/test/CodeGen/X86/implicit-null-checks.mir | 4 ---- llvm/test/DebugInfo/MIR/X86/live-debug-values-3preds.mir | 1 - llvm/test/DebugInfo/MIR/X86/live-debug-values.mir | 1 - 26 files changed, 17 insertions(+), 57 deletions(-) diff --git a/llvm/include/llvm/CodeGen/MIRYamlMapping.h b/llvm/include/llvm/CodeGen/MIRYamlMapping.h index bf39247..6138af4 100644 --- a/llvm/include/llvm/CodeGen/MIRYamlMapping.h +++ b/llvm/include/llvm/CodeGen/MIRYamlMapping.h @@ -390,7 +390,6 @@ struct MachineFunction { bool Selected = false; // Register information bool TracksRegLiveness = false; - bool TracksSubRegLiveness = false; std::vector VirtualRegisters; std::vector LiveIns; Optional> CalleeSavedRegisters; @@ -415,7 +414,6 @@ template <> struct MappingTraits { YamlIO.mapOptional("regBankSelected", MF.RegBankSelected); YamlIO.mapOptional("selected", MF.Selected); YamlIO.mapOptional("tracksRegLiveness", MF.TracksRegLiveness); - YamlIO.mapOptional("tracksSubRegLiveness", MF.TracksSubRegLiveness); YamlIO.mapOptional("registers", MF.VirtualRegisters); YamlIO.mapOptional("liveins", MF.LiveIns); YamlIO.mapOptional("calleeSavedRegisters", MF.CalleeSavedRegisters); diff --git a/llvm/include/llvm/CodeGen/MachineRegisterInfo.h b/llvm/include/llvm/CodeGen/MachineRegisterInfo.h index 74a49c7..a42c551 100644 --- a/llvm/include/llvm/CodeGen/MachineRegisterInfo.h +++ b/llvm/include/llvm/CodeGen/MachineRegisterInfo.h @@ -51,7 +51,7 @@ private: Delegate *TheDelegate; /// True if subregister liveness is tracked. - bool TracksSubRegLiveness; + const bool TracksSubRegLiveness; /// VRegInfo - Information we keep for each virtual register. /// @@ -199,10 +199,6 @@ public: return TracksSubRegLiveness; } - void enableSubRegLiveness(bool Enable = true) { - TracksSubRegLiveness = Enable; - } - //===--------------------------------------------------------------------===// // Register Info //===--------------------------------------------------------------------===// diff --git a/llvm/include/llvm/Target/TargetSubtargetInfo.h b/llvm/include/llvm/Target/TargetSubtargetInfo.h index 98fd80a..3965971 100644 --- a/llvm/include/llvm/Target/TargetSubtargetInfo.h +++ b/llvm/include/llvm/Target/TargetSubtargetInfo.h @@ -218,6 +218,8 @@ public: } /// Enable tracking of subregister liveness in register allocator. + /// Please use MachineRegisterInfo::subRegLivenessEnabled() instead where + /// possible. virtual bool enableSubRegLiveness() const { return false; } }; diff --git a/llvm/lib/CodeGen/DetectDeadLanes.cpp b/llvm/lib/CodeGen/DetectDeadLanes.cpp index 1d9e79c..931624b 100644 --- a/llvm/lib/CodeGen/DetectDeadLanes.cpp +++ b/llvm/lib/CodeGen/DetectDeadLanes.cpp @@ -577,12 +577,12 @@ bool DetectDeadLanes::runOnMachineFunction(MachineFunction &MF) { // register coalescer cannot deal with hidden dead defs. However without // subregister liveness enabled, the expected benefits of this pass are small // so we safe the compile time. - if (!MF.getSubtarget().enableSubRegLiveness()) { + MRI = &MF.getRegInfo(); + if (!MRI->subRegLivenessEnabled()) { DEBUG(dbgs() << "Skipping Detect dead lanes pass\n"); return false; } - MRI = &MF.getRegInfo(); TRI = MRI->getTargetRegisterInfo(); unsigned NumVirtRegs = MRI->getNumVirtRegs(); diff --git a/llvm/lib/CodeGen/LiveIntervalAnalysis.cpp b/llvm/lib/CodeGen/LiveIntervalAnalysis.cpp index 574684b..ba34d76 100644 --- a/llvm/lib/CodeGen/LiveIntervalAnalysis.cpp +++ b/llvm/lib/CodeGen/LiveIntervalAnalysis.cpp @@ -58,10 +58,6 @@ static cl::opt EnablePrecomputePhysRegs( static bool EnablePrecomputePhysRegs = false; #endif // NDEBUG -static cl::opt EnableSubRegLiveness( - "enable-subreg-liveness", cl::Hidden, cl::init(true), - cl::desc("Enable subregister liveness tracking.")); - namespace llvm { cl::opt UseSegmentSetForPhysRegs( "use-segment-set-for-physregs", cl::Hidden, cl::init(true), @@ -119,9 +115,6 @@ bool LiveIntervals::runOnMachineFunction(MachineFunction &fn) { Indexes = &getAnalysis(); DomTree = &getAnalysis(); - if (EnableSubRegLiveness && MF->getSubtarget().enableSubRegLiveness()) - MRI->enableSubRegLiveness(true); - if (!LRCalc) LRCalc = new LiveRangeCalc(); diff --git a/llvm/lib/CodeGen/MIRParser/MIRParser.cpp b/llvm/lib/CodeGen/MIRParser/MIRParser.cpp index 4a7dba6..f61b3c9 100644 --- a/llvm/lib/CodeGen/MIRParser/MIRParser.cpp +++ b/llvm/lib/CodeGen/MIRParser/MIRParser.cpp @@ -401,7 +401,6 @@ bool MIRParserImpl::initializeRegisterInfo(PerFunctionMIParsingState &PFS, assert(RegInfo.tracksLiveness()); if (!YamlMF.TracksRegLiveness) RegInfo.invalidateLiveness(); - RegInfo.enableSubRegLiveness(YamlMF.TracksSubRegLiveness); SMDiagnostic Error; // Parse the virtual register information. diff --git a/llvm/lib/CodeGen/MIRPrinter.cpp b/llvm/lib/CodeGen/MIRPrinter.cpp index 78de88f..795f1ca 100644 --- a/llvm/lib/CodeGen/MIRPrinter.cpp +++ b/llvm/lib/CodeGen/MIRPrinter.cpp @@ -213,7 +213,6 @@ void MIRPrinter::convert(yaml::MachineFunction &MF, const MachineRegisterInfo &RegInfo, const TargetRegisterInfo *TRI) { MF.TracksRegLiveness = RegInfo.tracksLiveness(); - MF.TracksSubRegLiveness = RegInfo.subRegLivenessEnabled(); // Print the virtual register definitions. for (unsigned I = 0, E = RegInfo.getNumVirtRegs(); I < E; ++I) { diff --git a/llvm/lib/CodeGen/MachineRegisterInfo.cpp b/llvm/lib/CodeGen/MachineRegisterInfo.cpp index 886de80..6e6c9f7 100644 --- a/llvm/lib/CodeGen/MachineRegisterInfo.cpp +++ b/llvm/lib/CodeGen/MachineRegisterInfo.cpp @@ -21,11 +21,16 @@ using namespace llvm; +static cl::opt EnableSubRegLiveness("enable-subreg-liveness", cl::Hidden, + cl::init(true), cl::desc("Enable subregister liveness tracking.")); + // Pin the vtable to this file. void MachineRegisterInfo::Delegate::anchor() {} MachineRegisterInfo::MachineRegisterInfo(MachineFunction *MF) - : MF(MF), TheDelegate(nullptr), TracksSubRegLiveness(false) { + : MF(MF), TheDelegate(nullptr), + TracksSubRegLiveness(MF->getSubtarget().enableSubRegLiveness() && + EnableSubRegLiveness) { unsigned NumRegs = getTargetRegisterInfo()->getNumRegs(); VRegInfo.reserve(256); RegAllocHints.reserve(256); diff --git a/llvm/lib/CodeGen/RenameIndependentSubregs.cpp b/llvm/lib/CodeGen/RenameIndependentSubregs.cpp index 9c189f9..73323fc 100644 --- a/llvm/lib/CodeGen/RenameIndependentSubregs.cpp +++ b/llvm/lib/CodeGen/RenameIndependentSubregs.cpp @@ -363,14 +363,14 @@ void RenameIndependentSubregs::computeMainRangesFixFlags( bool RenameIndependentSubregs::runOnMachineFunction(MachineFunction &MF) { // Skip renaming if liveness of subregister is not tracked. - if (!MF.getSubtarget().enableSubRegLiveness()) + MRI = &MF.getRegInfo(); + if (!MRI->subRegLivenessEnabled()) return false; DEBUG(dbgs() << "Renaming independent subregister live ranges in " << MF.getName() << '\n'); LIS = &getAnalysis(); - MRI = &MF.getRegInfo(); TII = MF.getSubtarget().getInstrInfo(); // Iterate over all vregs. Note that we query getNumVirtRegs() the newly diff --git a/llvm/test/CodeGen/AArch64/ldst-opt-dbg-limit.mir b/llvm/test/CodeGen/AArch64/ldst-opt-dbg-limit.mir index ecec1a3..bb9bdb0 100644 --- a/llvm/test/CodeGen/AArch64/ldst-opt-dbg-limit.mir +++ b/llvm/test/CodeGen/AArch64/ldst-opt-dbg-limit.mir @@ -31,7 +31,6 @@ exposesReturnsTwice: false hasInlineAsm: false allVRegsAllocated: true tracksRegLiveness: false -tracksSubRegLiveness: false liveins: - { reg: '%x0' } - { reg: '%w1' } @@ -88,7 +87,6 @@ exposesReturnsTwice: false hasInlineAsm: false allVRegsAllocated: true tracksRegLiveness: false -tracksSubRegLiveness: false liveins: - { reg: '%x0' } - { reg: '%w1' } diff --git a/llvm/test/CodeGen/AArch64/movimm-wzr.mir b/llvm/test/CodeGen/AArch64/movimm-wzr.mir index 7fb9ba6..1264f26 100644 --- a/llvm/test/CodeGen/AArch64/movimm-wzr.mir +++ b/llvm/test/CodeGen/AArch64/movimm-wzr.mir @@ -18,7 +18,6 @@ exposesReturnsTwice: false hasInlineAsm: false allVRegsAllocated: true tracksRegLiveness: false -tracksSubRegLiveness: false frameInfo: isFrameAddressTaken: false isReturnAddressTaken: false diff --git a/llvm/test/CodeGen/ARM/ARMLoadStoreDBG.mir b/llvm/test/CodeGen/ARM/ARMLoadStoreDBG.mir index fa58c16..2682daa 100644 --- a/llvm/test/CodeGen/ARM/ARMLoadStoreDBG.mir +++ b/llvm/test/CodeGen/ARM/ARMLoadStoreDBG.mir @@ -82,7 +82,6 @@ exposesReturnsTwice: false hasInlineAsm: false allVRegsAllocated: true tracksRegLiveness: true -tracksSubRegLiveness: false liveins: - { reg: '%r0' } - { reg: '%r1' } diff --git a/llvm/test/CodeGen/MIR/AArch64/inst-size-tlsdesc-callseq.mir b/llvm/test/CodeGen/MIR/AArch64/inst-size-tlsdesc-callseq.mir index a074998..588ec5d 100644 --- a/llvm/test/CodeGen/MIR/AArch64/inst-size-tlsdesc-callseq.mir +++ b/llvm/test/CodeGen/MIR/AArch64/inst-size-tlsdesc-callseq.mir @@ -36,7 +36,6 @@ exposesReturnsTwice: false hasInlineAsm: false allVRegsAllocated: true tracksRegLiveness: false -tracksSubRegLiveness: false liveins: - { reg: '%w0' } frameInfo: diff --git a/llvm/test/CodeGen/MIR/AMDGPU/expected-target-index-name.mir b/llvm/test/CodeGen/MIR/AMDGPU/expected-target-index-name.mir index d4d2ae1..47f0e16 100644 --- a/llvm/test/CodeGen/MIR/AMDGPU/expected-target-index-name.mir +++ b/llvm/test/CodeGen/MIR/AMDGPU/expected-target-index-name.mir @@ -32,8 +32,7 @@ ... --- -name: float -tracksSubRegLiveness: true +name: float liveins: - { reg: '%sgpr0_sgpr1' } frameInfo: diff --git a/llvm/test/CodeGen/MIR/AMDGPU/invalid-target-index-operand.mir b/llvm/test/CodeGen/MIR/AMDGPU/invalid-target-index-operand.mir index 1b67edc..d735032 100644 --- a/llvm/test/CodeGen/MIR/AMDGPU/invalid-target-index-operand.mir +++ b/llvm/test/CodeGen/MIR/AMDGPU/invalid-target-index-operand.mir @@ -32,8 +32,7 @@ ... --- -name: float -tracksSubRegLiveness: true +name: float liveins: - { reg: '%sgpr0_sgpr1' } frameInfo: diff --git a/llvm/test/CodeGen/MIR/AMDGPU/target-index-operands.mir b/llvm/test/CodeGen/MIR/AMDGPU/target-index-operands.mir index b0b7ea4..e15da09 100644 --- a/llvm/test/CodeGen/MIR/AMDGPU/target-index-operands.mir +++ b/llvm/test/CodeGen/MIR/AMDGPU/target-index-operands.mir @@ -41,8 +41,7 @@ ... --- -name: float -tracksSubRegLiveness: true +name: float liveins: - { reg: '%sgpr0_sgpr1' } frameInfo: @@ -72,8 +71,7 @@ body: | S_ENDPGM ... --- -name: float2 -tracksSubRegLiveness: true +name: float2 liveins: - { reg: '%sgpr0_sgpr1' } frameInfo: diff --git a/llvm/test/CodeGen/MIR/ARM/sched-it-debug-nodes.mir b/llvm/test/CodeGen/MIR/ARM/sched-it-debug-nodes.mir index 21b64c1..ca330cb 100644 --- a/llvm/test/CodeGen/MIR/ARM/sched-it-debug-nodes.mir +++ b/llvm/test/CodeGen/MIR/ARM/sched-it-debug-nodes.mir @@ -93,7 +93,6 @@ exposesReturnsTwice: false hasInlineAsm: false allVRegsAllocated: true tracksRegLiveness: true -tracksSubRegLiveness: false liveins: - { reg: '%r0' } - { reg: '%r1' } diff --git a/llvm/test/CodeGen/MIR/Generic/register-info.mir b/llvm/test/CodeGen/MIR/Generic/register-info.mir index 97a6593..af3f44f 100644 --- a/llvm/test/CodeGen/MIR/Generic/register-info.mir +++ b/llvm/test/CodeGen/MIR/Generic/register-info.mir @@ -18,7 +18,6 @@ --- # CHECK: name: foo # CHECK: tracksRegLiveness: false -# CHECK-NEXT: tracksSubRegLiveness: false # CHECK: ... name: foo body: | @@ -27,11 +26,9 @@ body: | --- # CHECK: name: bar # CHECK: tracksRegLiveness: true -# CHECK-NEXT: tracksSubRegLiveness: true # CHECK: ... name: bar tracksRegLiveness: true -tracksSubRegLiveness: true body: | bb.0: ... diff --git a/llvm/test/CodeGen/MIR/Lanai/peephole-compare.mir b/llvm/test/CodeGen/MIR/Lanai/peephole-compare.mir index 1f2ebe5..ddf4212 100644 --- a/llvm/test/CodeGen/MIR/Lanai/peephole-compare.mir +++ b/llvm/test/CodeGen/MIR/Lanai/peephole-compare.mir @@ -178,7 +178,6 @@ exposesReturnsTwice: false hasInlineAsm: false allVRegsAllocated: false tracksRegLiveness: true -tracksSubRegLiveness: false registers: - { id: 0, class: gpr } - { id: 1, class: gpr } @@ -225,7 +224,6 @@ exposesReturnsTwice: false hasInlineAsm: false allVRegsAllocated: false tracksRegLiveness: true -tracksSubRegLiveness: false registers: - { id: 0, class: gpr } - { id: 1, class: gpr } @@ -270,7 +268,6 @@ exposesReturnsTwice: false hasInlineAsm: false allVRegsAllocated: false tracksRegLiveness: true -tracksSubRegLiveness: false registers: - { id: 0, class: gpr } - { id: 1, class: gpr } @@ -319,7 +316,6 @@ exposesReturnsTwice: false hasInlineAsm: false allVRegsAllocated: false tracksRegLiveness: true -tracksSubRegLiveness: false registers: - { id: 0, class: gpr } - { id: 1, class: gpr } @@ -368,7 +364,6 @@ exposesReturnsTwice: false hasInlineAsm: false allVRegsAllocated: false tracksRegLiveness: true -tracksSubRegLiveness: false registers: - { id: 0, class: gpr } - { id: 1, class: gpr } @@ -417,7 +412,6 @@ exposesReturnsTwice: false hasInlineAsm: false allVRegsAllocated: false tracksRegLiveness: true -tracksSubRegLiveness: false registers: - { id: 0, class: gpr } - { id: 1, class: gpr } @@ -466,7 +460,6 @@ exposesReturnsTwice: false hasInlineAsm: false allVRegsAllocated: false tracksRegLiveness: true -tracksSubRegLiveness: false registers: - { id: 0, class: gpr } - { id: 1, class: gpr } @@ -515,7 +508,6 @@ exposesReturnsTwice: false hasInlineAsm: false allVRegsAllocated: false tracksRegLiveness: true -tracksSubRegLiveness: false registers: - { id: 0, class: gpr } - { id: 1, class: gpr } @@ -628,7 +620,6 @@ exposesReturnsTwice: false hasInlineAsm: false allVRegsAllocated: false tracksRegLiveness: true -tracksSubRegLiveness: false registers: - { id: 0, class: gpr } - { id: 1, class: gpr } diff --git a/llvm/test/CodeGen/PowerPC/aantidep-def-ec.mir b/llvm/test/CodeGen/PowerPC/aantidep-def-ec.mir index 31b256c..9e750eb 100644 --- a/llvm/test/CodeGen/PowerPC/aantidep-def-ec.mir +++ b/llvm/test/CodeGen/PowerPC/aantidep-def-ec.mir @@ -47,7 +47,6 @@ exposesReturnsTwice: false hasInlineAsm: true allVRegsAllocated: true tracksRegLiveness: true -tracksSubRegLiveness: false liveins: - { reg: '%x3' } - { reg: '%x4' } diff --git a/llvm/test/CodeGen/PowerPC/addisdtprelha-nonr3.mir b/llvm/test/CodeGen/PowerPC/addisdtprelha-nonr3.mir index f157b47..0bf7b95 100644 --- a/llvm/test/CodeGen/PowerPC/addisdtprelha-nonr3.mir +++ b/llvm/test/CodeGen/PowerPC/addisdtprelha-nonr3.mir @@ -29,7 +29,6 @@ exposesReturnsTwice: false hasInlineAsm: false allVRegsAllocated: true tracksRegLiveness: true -tracksSubRegLiveness: false frameInfo: isFrameAddressTaken: false isReturnAddressTaken: false diff --git a/llvm/test/CodeGen/PowerPC/no-rlwimi-trivial-commute.mir b/llvm/test/CodeGen/PowerPC/no-rlwimi-trivial-commute.mir index 479adbb..dce1e04 100644 --- a/llvm/test/CodeGen/PowerPC/no-rlwimi-trivial-commute.mir +++ b/llvm/test/CodeGen/PowerPC/no-rlwimi-trivial-commute.mir @@ -41,7 +41,6 @@ alignment: 2 exposesReturnsTwice: false hasInlineAsm: false tracksRegLiveness: true -tracksSubRegLiveness: false registers: - { id: 0, class: g8rc_and_g8rc_nox0 } - { id: 1, class: g8rc_and_g8rc_nox0 } diff --git a/llvm/test/CodeGen/PowerPC/opt-sub-inst-cr0-live.mir b/llvm/test/CodeGen/PowerPC/opt-sub-inst-cr0-live.mir index 942b44c..619954e 100644 --- a/llvm/test/CodeGen/PowerPC/opt-sub-inst-cr0-live.mir +++ b/llvm/test/CodeGen/PowerPC/opt-sub-inst-cr0-live.mir @@ -35,7 +35,6 @@ exposesReturnsTwice: false hasInlineAsm: false allVRegsAllocated: false tracksRegLiveness: true -tracksSubRegLiveness: false registers: - { id: 0, class: g8rc } - { id: 1, class: g8rc } diff --git a/llvm/test/CodeGen/X86/implicit-null-checks.mir b/llvm/test/CodeGen/X86/implicit-null-checks.mir index 9d54bcd..b2b7aca 100644 --- a/llvm/test/CodeGen/X86/implicit-null-checks.mir +++ b/llvm/test/CodeGen/X86/implicit-null-checks.mir @@ -87,7 +87,6 @@ name: imp_null_check_with_bitwise_op_0 alignment: 4 allVRegsAllocated: true tracksRegLiveness: true -tracksSubRegLiveness: false liveins: - { reg: '%rdi' } - { reg: '%esi' } @@ -131,7 +130,6 @@ name: imp_null_check_with_bitwise_op_1 alignment: 4 allVRegsAllocated: true tracksRegLiveness: true -tracksSubRegLiveness: false liveins: - { reg: '%rdi' } - { reg: '%esi' } @@ -180,7 +178,6 @@ name: imp_null_check_with_bitwise_op_2 alignment: 4 allVRegsAllocated: true tracksRegLiveness: true -tracksSubRegLiveness: false liveins: - { reg: '%rdi' } - { reg: '%esi' } @@ -225,7 +222,6 @@ name: imp_null_check_with_bitwise_op_3 alignment: 4 allVRegsAllocated: true tracksRegLiveness: true -tracksSubRegLiveness: false liveins: - { reg: '%rdi' } - { reg: '%rsi' } diff --git a/llvm/test/DebugInfo/MIR/X86/live-debug-values-3preds.mir b/llvm/test/DebugInfo/MIR/X86/live-debug-values-3preds.mir index ff81975..aaf1284 100644 --- a/llvm/test/DebugInfo/MIR/X86/live-debug-values-3preds.mir +++ b/llvm/test/DebugInfo/MIR/X86/live-debug-values-3preds.mir @@ -160,7 +160,6 @@ exposesReturnsTwice: false hasInlineAsm: false allVRegsAllocated: true tracksRegLiveness: true -tracksSubRegLiveness: false liveins: - { reg: '%edi' } - { reg: '%esi' } diff --git a/llvm/test/DebugInfo/MIR/X86/live-debug-values.mir b/llvm/test/DebugInfo/MIR/X86/live-debug-values.mir index dce88eb..750187e 100644 --- a/llvm/test/DebugInfo/MIR/X86/live-debug-values.mir +++ b/llvm/test/DebugInfo/MIR/X86/live-debug-values.mir @@ -162,7 +162,6 @@ exposesReturnsTwice: false hasInlineAsm: false allVRegsAllocated: true tracksRegLiveness: true -tracksSubRegLiveness: false liveins: - { reg: '%edi' } - { reg: '%rsi' } -- 2.7.4