From f178754e92c48908b155863a040e776b4b79a2b3 Mon Sep 17 00:00:00 2001 From: Sergio Paracuellos Date: Fri, 20 Mar 2020 12:01:20 +0100 Subject: [PATCH] staging: mt7621-dts: set up only two pcie phys This soc has only two real pcie phys one of them having a different register to enable and disable it. Change this to have only two dt nodes for the phys and use 'phy-cells' properly to say if the phy has dual ports. Signed-off-by: Sergio Paracuellos Link: https://lore.kernel.org/r/20200320110123.9907-3-sergio.paracuellos@gmail.com Signed-off-by: Greg Kroah-Hartman --- drivers/staging/mt7621-dts/mt7621.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/staging/mt7621-dts/mt7621.dtsi b/drivers/staging/mt7621-dts/mt7621.dtsi index 4884741..10fb497 100644 --- a/drivers/staging/mt7621-dts/mt7621.dtsi +++ b/drivers/staging/mt7621-dts/mt7621.dtsi @@ -535,8 +535,8 @@ reset-names = "pcie0", "pcie1", "pcie2"; clocks = <&clkctrl 24 &clkctrl 25 &clkctrl 26>; clock-names = "pcie0", "pcie1", "pcie2"; - phys = <&pcie0_phy 0>, <&pcie0_phy 1>, <&pcie1_phy 0>; - phy-names = "pcie-phy0", "pcie-phy1", "pcie-phy2"; + phys = <&pcie0_phy 1>, <&pcie2_phy 0>; + phy-names = "pcie-phy0", "pcie-phy2"; reset-gpios = <&gpio 19 GPIO_ACTIVE_LOW>, <&gpio 8 GPIO_ACTIVE_LOW>, @@ -573,7 +573,7 @@ #phy-cells = <1>; }; - pcie1_phy: pcie-phy@1e14a000 { + pcie2_phy: pcie-phy@1e14a000 { compatible = "mediatek,mt7621-pci-phy"; reg = <0x1e14a000 0x0700>; #phy-cells = <1>; -- 2.7.4