From f11ebbf8d4308795129bc6651cf701b61b812abf Mon Sep 17 00:00:00 2001 From: Tom Musta Date: Tue, 12 Aug 2014 08:45:07 -0500 Subject: [PATCH] target-ppc: Bug Fix: mullwo On 64-bit implementations, the mullwo result is the 64 bit product of the signed 32 bit operands. Fix the implementation to properly deposit the upper 32 bits into the target register. Example: R3 0407DED115077586 R4 53778DF3CA992E09 mullwo 3,3,4 R3 expected : FB9D02730D7735B6 R3 actual : 000000000D7735B6 (without this patch) Signed-off-by: Tom Musta Signed-off-by: Alexander Graf --- target-ppc/translate.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/target-ppc/translate.c b/target-ppc/translate.c index fab4f01..dc80b02 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -1140,11 +1140,20 @@ static void gen_mullwo(DisasContext *ctx) { TCGv_i32 t0 = tcg_temp_new_i32(); TCGv_i32 t1 = tcg_temp_new_i32(); +#if defined(TARGET_PPC64) + TCGv_i64 t2 = tcg_temp_new_i64(); +#endif tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); tcg_gen_muls2_i32(t0, t1, t0, t1); tcg_gen_ext_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); +#if defined(TARGET_PPC64) + tcg_gen_ext_i32_tl(t2, t1); + tcg_gen_deposit_i64(cpu_gpr[rD(ctx->opcode)], + cpu_gpr[rD(ctx->opcode)], t2, 32, 32); + tcg_temp_free(t2); +#endif tcg_gen_sari_i32(t0, t0, 31); tcg_gen_setcond_i32(TCG_COND_NE, t0, t0, t1); -- 2.7.4