From f104eb6e15503b770734e3a59937c9df865b2814 Mon Sep 17 00:00:00 2001 From: pvanhout Date: Mon, 15 May 2023 11:23:09 +0200 Subject: [PATCH] [AMDGPU] Reintroduce CC exception for non-inlined functions in Promote Alloca limits This is basically a partial revert of https://reviews.llvm.org/D145586 ( fd1d60873fdc ) D145586 was originally introduced to help with SWDEV-363662, and it did, but it also caused a 25% drop in performance in some MIOpen benchmarks where, it seems, functions are inlined more conservatively. This patch restores the pre-D145586 behavior for PromoteAlloca: functions with a non-entry CC have a 32 VGPRs threshold, but only if the function is not marked with "alwaysinline". A good number of AMDGPU code makes uses of the AMDGPUAlwaysInline pass anyway, so in our backend "alwaysinline" seems very common. This change does not affect SWDEV-363662 (the motivating issue for introducing D145586). Fixes SWDEV-399519 Reviewed By: rampitec, #amdgpu Differential Revision: https://reviews.llvm.org/D150551 --- llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp | 10 +++++++++- llvm/test/CodeGen/AMDGPU/vector-alloca-limits.ll | 18 +++++++++++++++++- 2 files changed, 26 insertions(+), 2 deletions(-) diff --git a/llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp b/llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp index 7a98d79..cd289e6 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp @@ -162,7 +162,15 @@ unsigned getMaxVGPRs(const TargetMachine &TM, const Function &F) { return 128; const GCNSubtarget &ST = TM.getSubtarget(F); - return ST.getMaxNumVGPRs(ST.getWavesPerEU(F).first); + unsigned MaxVGPRs = ST.getMaxNumVGPRs(ST.getWavesPerEU(F).first); + + // A non-entry function has only 32 caller preserved registers. + // Do not promote alloca which will force spilling unless we know the function + // will be inlined. + if (!F.hasFnAttribute(Attribute::AlwaysInline) && + !AMDGPU::isEntryFunctionCC(F.getCallingConv())) + MaxVGPRs = std::min(MaxVGPRs, 32u); + return MaxVGPRs; } } // end anonymous namespace diff --git a/llvm/test/CodeGen/AMDGPU/vector-alloca-limits.ll b/llvm/test/CodeGen/AMDGPU/vector-alloca-limits.ll index dccf1c7..64d7c78 100644 --- a/llvm/test/CodeGen/AMDGPU/vector-alloca-limits.ll +++ b/llvm/test/CodeGen/AMDGPU/vector-alloca-limits.ll @@ -139,11 +139,26 @@ entry: } ; OPT-LABEL: @func_alloca_9xi64_max256( +; OPT: alloca +; OPT-NOT: <9 x i64> +; LIMIT32: alloca +; LIMIT32-NOT: <9 x i64> +define void @func_alloca_9xi64_max256(ptr addrspace(1) %out, i32 %index) #2 { +entry: + %tmp = alloca [9 x i64], addrspace(5) + store i64 0, ptr addrspace(5) %tmp + %tmp1 = getelementptr [9 x i64], ptr addrspace(5) %tmp, i32 0, i32 %index + %tmp2 = load i64, ptr addrspace(5) %tmp1 + store i64 %tmp2, ptr addrspace(1) %out + ret void +} + +; OPT-LABEL: @alwaysinlined_func_alloca_9xi64_max256( ; OPT-NOT: alloca ; OPT: <9 x i64> ; LIMIT32: alloca ; LIMIT32-NOT: <9 x i64> -define void @func_alloca_9xi64_max256(ptr addrspace(1) %out, i32 %index) #2 { +define void @alwaysinlined_func_alloca_9xi64_max256(ptr addrspace(1) %out, i32 %index) #3 { entry: %tmp = alloca [9 x i64], addrspace(5) store i64 0, ptr addrspace(5) %tmp @@ -156,3 +171,4 @@ entry: attributes #0 = { "amdgpu-flat-work-group-size"="1,1024" } attributes #1 = { "amdgpu-flat-work-group-size"="1,512" } attributes #2 = { "amdgpu-flat-work-group-size"="1,256" } +attributes #3 = { alwaysinline "amdgpu-flat-work-group-size"="1,256" } -- 2.7.4