From f0c3a66f0e8634e11b471a3ddb1896dafdf6d6bb Mon Sep 17 00:00:00 2001 From: Rob Clark Date: Mon, 20 Mar 2023 11:54:13 -0700 Subject: [PATCH] drm/msm/a6xx: Some reg64 conversion The next generated header update will drop the _LO/_HI suffix, now that the userspace tooling properly understands 64b vs 32b regs (and the _LO/ _HI workarounds are getting cleaned up). So convert to using the 64b reg helpers in prep. Signed-off-by: Rob Clark Reviewed-by: Konrad Dybcio Patchwork: https://patchwork.freedesktop.org/patch/527923/ Link: https://lore.kernel.org/r/20230320185416.938842-1-robdclark@gmail.com --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index eb442a7..134f12fe 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -1037,12 +1037,9 @@ static int hw_init(struct msm_gpu *gpu) gpu_write(gpu, REG_A6XX_RBBM_PERFCTR_GPU_BUSY_MASKED, 0xffffffff); /* Disable L2 bypass in the UCHE */ - gpu_write(gpu, REG_A6XX_UCHE_WRITE_RANGE_MAX_LO, 0xffffffc0); - gpu_write(gpu, REG_A6XX_UCHE_WRITE_RANGE_MAX_HI, 0x0001ffff); - gpu_write(gpu, REG_A6XX_UCHE_TRAP_BASE_LO, 0xfffff000); - gpu_write(gpu, REG_A6XX_UCHE_TRAP_BASE_HI, 0x0001ffff); - gpu_write(gpu, REG_A6XX_UCHE_WRITE_THRU_BASE_LO, 0xfffff000); - gpu_write(gpu, REG_A6XX_UCHE_WRITE_THRU_BASE_HI, 0x0001ffff); + gpu_write64(gpu, REG_A6XX_UCHE_WRITE_RANGE_MAX_LO, 0x0001ffffffffffc0llu); + gpu_write64(gpu, REG_A6XX_UCHE_TRAP_BASE_LO, 0x0001fffffffff000llu); + gpu_write64(gpu, REG_A6XX_UCHE_WRITE_THRU_BASE_LO, 0x0001fffffffff000llu); if (!adreno_is_a650_family(adreno_gpu)) { /* Set the GMEM VA range [0x100000:0x100000 + gpu->gmem - 1] */ -- 2.7.4