From f0a98ad820afa5019bb009300a120a7f4a360925 Mon Sep 17 00:00:00 2001 From: Mircea Trofin Date: Tue, 27 Oct 2020 14:30:18 -0700 Subject: [PATCH] [NFC] Use Register in RegisterPressure APIs Some related changes as well. Differential Revision: https://reviews.llvm.org/D90268 --- llvm/include/llvm/CodeGen/MachineRegisterInfo.h | 13 ++-- llvm/include/llvm/CodeGen/RegisterPressure.h | 34 +++++------ llvm/include/llvm/CodeGen/TargetRegisterInfo.h | 21 ++++--- llvm/lib/CodeGen/MachineScheduler.cpp | 4 +- llvm/lib/CodeGen/RegisterPressure.cpp | 80 +++++++++++++------------ 5 files changed, 76 insertions(+), 76 deletions(-) diff --git a/llvm/include/llvm/CodeGen/MachineRegisterInfo.h b/llvm/include/llvm/CodeGen/MachineRegisterInfo.h index 9cb948f..a4da62d 100644 --- a/llvm/include/llvm/CodeGen/MachineRegisterInfo.h +++ b/llvm/include/llvm/CodeGen/MachineRegisterInfo.h @@ -632,7 +632,7 @@ public: /// Get an iterator over the pressure sets affected by the given physical or /// virtual register. If RegUnit is physical, it must be a register unit (from /// MCRegUnitIterator). - PSetIterator getPressureSets(unsigned RegUnit) const; + PSetIterator getPressureSets(Register RegUnit) const; //===--------------------------------------------------------------------===// // Virtual Register Info @@ -1187,14 +1187,13 @@ class PSetIterator { public: PSetIterator() = default; - PSetIterator(unsigned RegUnit, const MachineRegisterInfo *MRI) { + PSetIterator(Register RegUnit, const MachineRegisterInfo *MRI) { const TargetRegisterInfo *TRI = MRI->getTargetRegisterInfo(); - if (Register::isVirtualRegister(RegUnit)) { + if (RegUnit.isVirtual()) { const TargetRegisterClass *RC = MRI->getRegClass(RegUnit); PSet = TRI->getRegClassPressureSets(RC); Weight = TRI->getRegClassWeight(RC).RegWeight; - } - else { + } else { PSet = TRI->getRegUnitPressureSets(RegUnit); Weight = TRI->getRegUnitWeight(RegUnit); } @@ -1216,8 +1215,8 @@ public: } }; -inline PSetIterator MachineRegisterInfo:: -getPressureSets(unsigned RegUnit) const { +inline PSetIterator +MachineRegisterInfo::getPressureSets(Register RegUnit) const { return PSetIterator(RegUnit, this); } diff --git a/llvm/include/llvm/CodeGen/RegisterPressure.h b/llvm/include/llvm/CodeGen/RegisterPressure.h index 92333b8..1deeb4d 100644 --- a/llvm/include/llvm/CodeGen/RegisterPressure.h +++ b/llvm/include/llvm/CodeGen/RegisterPressure.h @@ -37,10 +37,10 @@ class MachineRegisterInfo; class RegisterClassInfo; struct RegisterMaskPair { - unsigned RegUnit; ///< Virtual register or register unit. + Register RegUnit; ///< Virtual register or register unit. LaneBitmask LaneMask; - RegisterMaskPair(unsigned RegUnit, LaneBitmask LaneMask) + RegisterMaskPair(Register RegUnit, LaneBitmask LaneMask) : RegUnit(RegUnit), LaneMask(LaneMask) {} }; @@ -157,7 +157,7 @@ public: const_iterator begin() const { return &PressureChanges[0]; } const_iterator end() const { return &PressureChanges[MaxPSets]; } - void addPressureChange(unsigned RegUnit, bool IsDec, + void addPressureChange(Register RegUnit, bool IsDec, const MachineRegisterInfo *MRI); void dump(const TargetRegisterInfo &TRI) const; @@ -275,24 +275,24 @@ private: RegSet Regs; unsigned NumRegUnits; - unsigned getSparseIndexFromReg(unsigned Reg) const { - if (Register::isVirtualRegister(Reg)) + unsigned getSparseIndexFromReg(Register Reg) const { + if (Reg.isVirtual()) return Register::virtReg2Index(Reg) + NumRegUnits; assert(Reg < NumRegUnits); return Reg; } - unsigned getRegFromSparseIndex(unsigned SparseIndex) const { + Register getRegFromSparseIndex(unsigned SparseIndex) const { if (SparseIndex >= NumRegUnits) - return Register::index2VirtReg(SparseIndex-NumRegUnits); - return SparseIndex; + return Register::index2VirtReg(SparseIndex - NumRegUnits); + return Register(SparseIndex); } public: void clear(); void init(const MachineRegisterInfo &MRI); - LaneBitmask contains(unsigned Reg) const { + LaneBitmask contains(Register Reg) const { unsigned SparseIndex = getSparseIndexFromReg(Reg); RegSet::const_iterator I = Regs.find(SparseIndex); if (I == Regs.end()) @@ -332,7 +332,7 @@ public: template void appendTo(ContainerT &To) const { for (const IndexMaskPair &P : Regs) { - unsigned Reg = getRegFromSparseIndex(P.Index); + Register Reg = getRegFromSparseIndex(P.Index); if (P.LaneMask.any()) To.push_back(RegisterMaskPair(Reg, P.LaneMask)); } @@ -390,7 +390,7 @@ class RegPressureTracker { LiveRegSet LiveRegs; /// Set of vreg defs that start a live range. - SparseSet UntiedDefs; + SparseSet UntiedDefs; /// Live-through pressure. std::vector LiveThruPressure; @@ -532,7 +532,7 @@ public: return getDownwardPressure(MI, PressureResult, MaxPressureResult); } - bool hasUntiedDef(unsigned VirtReg) const { + bool hasUntiedDef(Register VirtReg) const { return UntiedDefs.count(VirtReg); } @@ -548,9 +548,9 @@ protected: /// after the current position. SlotIndex getCurrSlot() const; - void increaseRegPressure(unsigned RegUnit, LaneBitmask PreviousMask, + void increaseRegPressure(Register RegUnit, LaneBitmask PreviousMask, LaneBitmask NewMask); - void decreaseRegPressure(unsigned RegUnit, LaneBitmask PreviousMask, + void decreaseRegPressure(Register RegUnit, LaneBitmask PreviousMask, LaneBitmask NewMask); void bumpDeadDefs(ArrayRef DeadDefs); @@ -561,9 +561,9 @@ protected: void discoverLiveInOrOut(RegisterMaskPair Pair, SmallVectorImpl &LiveInOrOut); - LaneBitmask getLastUsedLanes(unsigned RegUnit, SlotIndex Pos) const; - LaneBitmask getLiveLanesAt(unsigned RegUnit, SlotIndex Pos) const; - LaneBitmask getLiveThroughAt(unsigned RegUnit, SlotIndex Pos) const; + LaneBitmask getLastUsedLanes(Register RegUnit, SlotIndex Pos) const; + LaneBitmask getLiveLanesAt(Register RegUnit, SlotIndex Pos) const; + LaneBitmask getLiveThroughAt(Register RegUnit, SlotIndex Pos) const; }; void dumpRegSetPressure(ArrayRef SetPressure, diff --git a/llvm/include/llvm/CodeGen/TargetRegisterInfo.h b/llvm/include/llvm/CodeGen/TargetRegisterInfo.h index 8f60a5f..ff5104c 100644 --- a/llvm/include/llvm/CodeGen/TargetRegisterInfo.h +++ b/llvm/include/llvm/CodeGen/TargetRegisterInfo.h @@ -87,22 +87,21 @@ public: /// Return true if the specified register is included in this register class. /// This does not include virtual registers. - bool contains(unsigned Reg) const { + bool contains(Register Reg) const { /// FIXME: Historically this function has returned false when given vregs /// but it should probably only receive physical registers - if (!Register::isPhysicalRegister(Reg)) + if (!Reg.isPhysical()) return false; - return MC->contains(Reg); + return MC->contains(Reg.asMCReg()); } /// Return true if both registers are in this class. - bool contains(unsigned Reg1, unsigned Reg2) const { + bool contains(Register Reg1, Register Reg2) const { /// FIXME: Historically this function has returned false when given a vregs /// but it should probably only receive physical registers - if (!Register::isPhysicalRegister(Reg1) || - !Register::isPhysicalRegister(Reg2)) + if (!Reg1.isPhysical() || !Reg2.isPhysical()) return false; - return MC->contains(Reg1, Reg2); + return MC->contains(Reg1.asMCReg(), Reg2.asMCReg()); } /// Return the cost of copying a value between two registers in this class. @@ -401,9 +400,9 @@ public: } /// Returns true if Reg contains RegUnit. - bool hasRegUnit(MCRegister Reg, unsigned RegUnit) const { + bool hasRegUnit(MCRegister Reg, Register RegUnit) const { for (MCRegUnitIterator Units(Reg, this); Units.isValid(); ++Units) - if (*Units == RegUnit) + if (Register(*Units) == RegUnit) return true; return false; } @@ -1183,8 +1182,8 @@ public: // This is useful when building IndexedMaps keyed on virtual registers struct VirtReg2IndexFunctor { - using argument_type = unsigned; - unsigned operator()(unsigned Reg) const { + using argument_type = Register; + unsigned operator()(Register Reg) const { return Register::virtReg2Index(Reg); } }; diff --git a/llvm/lib/CodeGen/MachineScheduler.cpp b/llvm/lib/CodeGen/MachineScheduler.cpp index 6d24e3b..b239131 100644 --- a/llvm/lib/CodeGen/MachineScheduler.cpp +++ b/llvm/lib/CodeGen/MachineScheduler.cpp @@ -1101,7 +1101,7 @@ updateScheduledPressure(const SUnit *SU, void ScheduleDAGMILive::updatePressureDiffs( ArrayRef LiveUses) { for (const RegisterMaskPair &P : LiveUses) { - unsigned Reg = P.RegUnit; + Register Reg = P.RegUnit; /// FIXME: Currently assuming single-use physregs. if (!Register::isVirtualRegister(Reg)) continue; @@ -1326,7 +1326,7 @@ unsigned ScheduleDAGMILive::computeCyclicCriticalPath() { unsigned MaxCyclicLatency = 0; // Visit each live out vreg def to find def/use pairs that cross iterations. for (const RegisterMaskPair &P : RPTracker.getPressure().LiveOutRegs) { - unsigned Reg = P.RegUnit; + Register Reg = P.RegUnit; if (!Register::isVirtualRegister(Reg)) continue; const LiveInterval &LI = LIS->getInterval(Reg); diff --git a/llvm/lib/CodeGen/RegisterPressure.cpp b/llvm/lib/CodeGen/RegisterPressure.cpp index ecbc4ed..8f1fc10 100644 --- a/llvm/lib/CodeGen/RegisterPressure.cpp +++ b/llvm/lib/CodeGen/RegisterPressure.cpp @@ -62,7 +62,7 @@ static void increaseSetPressure(std::vector &CurrSetPressure, /// Decrease pressure for each pressure set provided by TargetRegisterInfo. static void decreaseSetPressure(std::vector &CurrSetPressure, - const MachineRegisterInfo &MRI, unsigned Reg, + const MachineRegisterInfo &MRI, Register Reg, LaneBitmask PrevMask, LaneBitmask NewMask) { //assert((NewMask & !PrevMask) == 0 && "Must not add bits"); if (NewMask.any() || PrevMask.none()) @@ -152,7 +152,7 @@ void RegPressureDelta::dump() const { #endif -void RegPressureTracker::increaseRegPressure(unsigned RegUnit, +void RegPressureTracker::increaseRegPressure(Register RegUnit, LaneBitmask PreviousMask, LaneBitmask NewMask) { if (PreviousMask.any() || NewMask.none()) @@ -167,7 +167,7 @@ void RegPressureTracker::increaseRegPressure(unsigned RegUnit, } } -void RegPressureTracker::decreaseRegPressure(unsigned RegUnit, +void RegPressureTracker::decreaseRegPressure(Register RegUnit, LaneBitmask PreviousMask, LaneBitmask NewMask) { decreaseSetPressure(CurrSetPressure, *MRI, RegUnit, PreviousMask, NewMask); @@ -360,7 +360,7 @@ void RegPressureTracker::initLiveThru(const RegPressureTracker &RPTracker) { LiveThruPressure.assign(TRI->getNumRegPressureSets(), 0); assert(isBottomClosed() && "need bottom-up tracking to intialize."); for (const RegisterMaskPair &Pair : P.LiveOutRegs) { - unsigned RegUnit = Pair.RegUnit; + Register RegUnit = Pair.RegUnit; if (Register::isVirtualRegister(RegUnit) && !RPTracker.hasUntiedDef(RegUnit)) increaseSetPressure(LiveThruPressure, *MRI, RegUnit, @@ -369,7 +369,7 @@ void RegPressureTracker::initLiveThru(const RegPressureTracker &RPTracker) { } static LaneBitmask getRegLanes(ArrayRef RegUnits, - unsigned RegUnit) { + Register RegUnit) { auto I = llvm::find_if(RegUnits, [RegUnit](const RegisterMaskPair Other) { return Other.RegUnit == RegUnit; }); @@ -380,7 +380,7 @@ static LaneBitmask getRegLanes(ArrayRef RegUnits, static void addRegLanes(SmallVectorImpl &RegUnits, RegisterMaskPair Pair) { - unsigned RegUnit = Pair.RegUnit; + Register RegUnit = Pair.RegUnit; assert(Pair.LaneMask.any()); auto I = llvm::find_if(RegUnits, [RegUnit](const RegisterMaskPair Other) { return Other.RegUnit == RegUnit; @@ -393,7 +393,7 @@ static void addRegLanes(SmallVectorImpl &RegUnits, } static void setRegZero(SmallVectorImpl &RegUnits, - unsigned RegUnit) { + Register RegUnit) { auto I = llvm::find_if(RegUnits, [RegUnit](const RegisterMaskPair Other) { return Other.RegUnit == RegUnit; }); @@ -406,7 +406,7 @@ static void setRegZero(SmallVectorImpl &RegUnits, static void removeRegLanes(SmallVectorImpl &RegUnits, RegisterMaskPair Pair) { - unsigned RegUnit = Pair.RegUnit; + Register RegUnit = Pair.RegUnit; assert(Pair.LaneMask.any()); auto I = llvm::find_if(RegUnits, [RegUnit](const RegisterMaskPair Other) { return Other.RegUnit == RegUnit; @@ -418,11 +418,12 @@ static void removeRegLanes(SmallVectorImpl &RegUnits, } } -static LaneBitmask getLanesWithProperty(const LiveIntervals &LIS, - const MachineRegisterInfo &MRI, bool TrackLaneMasks, unsigned RegUnit, - SlotIndex Pos, LaneBitmask SafeDefault, - bool(*Property)(const LiveRange &LR, SlotIndex Pos)) { - if (Register::isVirtualRegister(RegUnit)) { +static LaneBitmask +getLanesWithProperty(const LiveIntervals &LIS, const MachineRegisterInfo &MRI, + bool TrackLaneMasks, Register RegUnit, SlotIndex Pos, + LaneBitmask SafeDefault, + bool (*Property)(const LiveRange &LR, SlotIndex Pos)) { + if (RegUnit.isVirtual()) { const LiveInterval &LI = LIS.getInterval(RegUnit); LaneBitmask Result; if (TrackLaneMasks && LI.hasSubRanges()) { @@ -448,7 +449,7 @@ static LaneBitmask getLanesWithProperty(const LiveIntervals &LIS, static LaneBitmask getLiveLanesAt(const LiveIntervals &LIS, const MachineRegisterInfo &MRI, - bool TrackLaneMasks, unsigned RegUnit, + bool TrackLaneMasks, Register RegUnit, SlotIndex Pos) { return getLanesWithProperty(LIS, MRI, TrackLaneMasks, RegUnit, Pos, LaneBitmask::getAll(), @@ -457,7 +458,6 @@ static LaneBitmask getLiveLanesAt(const LiveIntervals &LIS, }); } - namespace { /// Collect this instruction's unique uses and defs into SmallVectors for @@ -517,12 +517,13 @@ class RegisterOperandsCollector { } } - void pushReg(unsigned Reg, + void pushReg(Register Reg, SmallVectorImpl &RegUnits) const { - if (Register::isVirtualRegister(Reg)) { + if (Reg.isVirtual()) { addRegLanes(RegUnits, RegisterMaskPair(Reg, LaneBitmask::getAll())); } else if (MRI.isAllocatable(Reg)) { - for (MCRegUnitIterator Units(Reg, &TRI); Units.isValid(); ++Units) + for (MCRegUnitIterator Units(Reg.asMCReg(), &TRI); Units.isValid(); + ++Units) addRegLanes(RegUnits, RegisterMaskPair(*Units, LaneBitmask::getAll())); } } @@ -549,15 +550,16 @@ class RegisterOperandsCollector { } } - void pushRegLanes(unsigned Reg, unsigned SubRegIdx, + void pushRegLanes(Register Reg, unsigned SubRegIdx, SmallVectorImpl &RegUnits) const { - if (Register::isVirtualRegister(Reg)) { + if (Reg.isVirtual()) { LaneBitmask LaneMask = SubRegIdx != 0 ? TRI.getSubRegIndexLaneMask(SubRegIdx) : MRI.getMaxLaneMaskForVReg(Reg); addRegLanes(RegUnits, RegisterMaskPair(Reg, LaneMask)); } else if (MRI.isAllocatable(Reg)) { - for (MCRegUnitIterator Units(Reg, &TRI); Units.isValid(); ++Units) + for (MCRegUnitIterator Units(Reg.asMCReg(), &TRI); Units.isValid(); + ++Units) addRegLanes(RegUnits, RegisterMaskPair(*Units, LaneBitmask::getAll())); } } @@ -580,7 +582,7 @@ void RegisterOperands::detectDeadDefs(const MachineInstr &MI, const LiveIntervals &LIS) { SlotIndex SlotIdx = LIS.getInstructionIndex(MI); for (auto RI = Defs.begin(); RI != Defs.end(); /*empty*/) { - unsigned Reg = RI->RegUnit; + Register Reg = RI->RegUnit; const LiveRange *LR = getLiveRange(LIS, Reg); if (LR != nullptr) { LiveQueryResult LRQ = LR->Query(SlotIdx); @@ -605,7 +607,7 @@ void RegisterOperands::adjustLaneLiveness(const LiveIntervals &LIS, Pos.getDeadSlot()); // If the def is all that is live after the instruction, then in case // of a subregister def we need a read-undef flag. - unsigned RegUnit = I->RegUnit; + Register RegUnit = I->RegUnit; if (Register::isVirtualRegister(RegUnit) && AddFlagsMI != nullptr && (LiveAfter & ~I->LaneMask).none()) AddFlagsMI->setRegisterDefReadUndef(RegUnit); @@ -631,7 +633,7 @@ void RegisterOperands::adjustLaneLiveness(const LiveIntervals &LIS, } if (AddFlagsMI != nullptr) { for (const RegisterMaskPair &P : DeadDefs) { - unsigned RegUnit = P.RegUnit; + Register RegUnit = P.RegUnit; if (!Register::isVirtualRegister(RegUnit)) continue; LaneBitmask LiveAfter = getLiveLanesAt(LIS, MRI, true, RegUnit, @@ -667,7 +669,7 @@ void PressureDiffs::addInstruction(unsigned Idx, } /// Add a change in pressure to the pressure diff of a given instruction. -void PressureDiff::addPressureChange(unsigned RegUnit, bool IsDec, +void PressureDiff::addPressureChange(Register RegUnit, bool IsDec, const MachineRegisterInfo *MRI) { PSetIterator PSetI = MRI->getPressureSets(RegUnit); int Weight = IsDec ? -PSetI.getWeight() : PSetI.getWeight(); @@ -714,7 +716,7 @@ void RegPressureTracker::discoverLiveInOrOut(RegisterMaskPair Pair, SmallVectorImpl &LiveInOrOut) { assert(Pair.LaneMask.any()); - unsigned RegUnit = Pair.RegUnit; + Register RegUnit = Pair.RegUnit; auto I = llvm::find_if(LiveInOrOut, [RegUnit](const RegisterMaskPair &Other) { return Other.RegUnit == RegUnit; }); @@ -742,13 +744,13 @@ void RegPressureTracker::discoverLiveOut(RegisterMaskPair Pair) { void RegPressureTracker::bumpDeadDefs(ArrayRef DeadDefs) { for (const RegisterMaskPair &P : DeadDefs) { - unsigned Reg = P.RegUnit; + Register Reg = P.RegUnit; LaneBitmask LiveMask = LiveRegs.contains(Reg); LaneBitmask BumpedMask = LiveMask | P.LaneMask; increaseRegPressure(Reg, LiveMask, BumpedMask); } for (const RegisterMaskPair &P : DeadDefs) { - unsigned Reg = P.RegUnit; + Register Reg = P.RegUnit; LaneBitmask LiveMask = LiveRegs.contains(Reg); LaneBitmask BumpedMask = LiveMask | P.LaneMask; decreaseRegPressure(Reg, BumpedMask, LiveMask); @@ -770,7 +772,7 @@ void RegPressureTracker::recede(const RegisterOperands &RegOpers, // Kill liveness at live defs. // TODO: consider earlyclobbers? for (const RegisterMaskPair &Def : RegOpers.Defs) { - unsigned Reg = Def.RegUnit; + Register Reg = Def.RegUnit; LaneBitmask PreviousMask = LiveRegs.erase(Def); LaneBitmask NewMask = PreviousMask & ~Def.LaneMask; @@ -800,7 +802,7 @@ void RegPressureTracker::recede(const RegisterOperands &RegOpers, // Generate liveness for uses. for (const RegisterMaskPair &Use : RegOpers.Uses) { - unsigned Reg = Use.RegUnit; + Register Reg = Use.RegUnit; assert(Use.LaneMask.any()); LaneBitmask PreviousMask = LiveRegs.insert(Use); LaneBitmask NewMask = PreviousMask | Use.LaneMask; @@ -840,7 +842,7 @@ void RegPressureTracker::recede(const RegisterOperands &RegOpers, } if (TrackUntiedDefs) { for (const RegisterMaskPair &Def : RegOpers.Defs) { - unsigned RegUnit = Def.RegUnit; + Register RegUnit = Def.RegUnit; if (Register::isVirtualRegister(RegUnit) && (LiveRegs.contains(RegUnit) & Def.LaneMask).none()) UntiedDefs.insert(RegUnit); @@ -911,7 +913,7 @@ void RegPressureTracker::advance(const RegisterOperands &RegOpers) { } for (const RegisterMaskPair &Use : RegOpers.Uses) { - unsigned Reg = Use.RegUnit; + Register Reg = Use.RegUnit; LaneBitmask LiveMask = LiveRegs.contains(Reg); LaneBitmask LiveIn = Use.LaneMask & ~LiveMask; if (LiveIn.any()) { @@ -1060,7 +1062,7 @@ void RegPressureTracker::bumpUpwardPressure(const MachineInstr *MI) { // Kill liveness at live defs. for (const RegisterMaskPair &P : RegOpers.Defs) { - unsigned Reg = P.RegUnit; + Register Reg = P.RegUnit; LaneBitmask LiveLanes = LiveRegs.contains(Reg); LaneBitmask UseLanes = getRegLanes(RegOpers.Uses, Reg); LaneBitmask DefLanes = P.LaneMask; @@ -1069,7 +1071,7 @@ void RegPressureTracker::bumpUpwardPressure(const MachineInstr *MI) { } // Generate liveness for uses. for (const RegisterMaskPair &P : RegOpers.Uses) { - unsigned Reg = P.RegUnit; + Register Reg = P.RegUnit; LaneBitmask LiveLanes = LiveRegs.contains(Reg); LaneBitmask LiveAfter = LiveLanes | P.LaneMask; increaseRegPressure(Reg, LiveLanes, LiveAfter); @@ -1240,7 +1242,7 @@ static LaneBitmask findUseBetween(unsigned Reg, LaneBitmask LastUseMask, return LastUseMask; } -LaneBitmask RegPressureTracker::getLiveLanesAt(unsigned RegUnit, +LaneBitmask RegPressureTracker::getLiveLanesAt(Register RegUnit, SlotIndex Pos) const { assert(RequireIntervals); return getLanesWithProperty(*LIS, *MRI, TrackLaneMasks, RegUnit, Pos, @@ -1250,7 +1252,7 @@ LaneBitmask RegPressureTracker::getLiveLanesAt(unsigned RegUnit, }); } -LaneBitmask RegPressureTracker::getLastUsedLanes(unsigned RegUnit, +LaneBitmask RegPressureTracker::getLastUsedLanes(Register RegUnit, SlotIndex Pos) const { assert(RequireIntervals); return getLanesWithProperty(*LIS, *MRI, TrackLaneMasks, RegUnit, @@ -1261,7 +1263,7 @@ LaneBitmask RegPressureTracker::getLastUsedLanes(unsigned RegUnit, }); } -LaneBitmask RegPressureTracker::getLiveThroughAt(unsigned RegUnit, +LaneBitmask RegPressureTracker::getLiveThroughAt(Register RegUnit, SlotIndex Pos) const { assert(RequireIntervals); return getLanesWithProperty(*LIS, *MRI, TrackLaneMasks, RegUnit, Pos, @@ -1294,7 +1296,7 @@ void RegPressureTracker::bumpDownwardPressure(const MachineInstr *MI) { if (RequireIntervals) { for (const RegisterMaskPair &Use : RegOpers.Uses) { - unsigned Reg = Use.RegUnit; + Register Reg = Use.RegUnit; LaneBitmask LastUseMask = getLastUsedLanes(Reg, SlotIdx); if (LastUseMask.none()) continue; @@ -1317,7 +1319,7 @@ void RegPressureTracker::bumpDownwardPressure(const MachineInstr *MI) { // Generate liveness for defs. for (const RegisterMaskPair &Def : RegOpers.Defs) { - unsigned Reg = Def.RegUnit; + Register Reg = Def.RegUnit; LaneBitmask LiveMask = LiveRegs.contains(Reg); LaneBitmask NewMask = LiveMask | Def.LaneMask; increaseRegPressure(Reg, LiveMask, NewMask); -- 2.7.4