From f00ef8b9b294ab7520a929b0b3d9c74cba9059b1 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Sun, 2 Apr 2023 19:14:22 -0700 Subject: [PATCH] [X86] Rename Flag->Glue in SelectionDAG. NFC Long long ago Glue was called Flag, and it was never completely renamed. More patches for other targets will follow. Differential Revision: https://reviews.llvm.org/D147418 --- llvm/lib/Target/X86/X86ISelLowering.cpp | 114 ++++++++++----------- llvm/lib/Target/X86/X86ISelLowering.h | 4 +- llvm/lib/Target/X86/X86InstrControl.td | 4 +- llvm/lib/Target/X86/X86InstrInfo.td | 2 +- .../X86/merge-store-partially-alias-loads.ll | 2 +- llvm/test/CodeGen/X86/selectiondag-debug-loc.ll | 2 +- 6 files changed, 64 insertions(+), 64 deletions(-) diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 21f0b73..f8800fb 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -3308,7 +3308,7 @@ X86TargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv, } } - SDValue Flag; + SDValue Glue; SmallVector RetOps; RetOps.push_back(Chain); // Operand #0 = Chain (updated below) // Operand #1 = Bytes To Pop @@ -3322,8 +3322,8 @@ X86TargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv, continue; // Don't emit a copytoreg. } - Chain = DAG.getCopyToReg(Chain, dl, RetVal.first, RetVal.second, Flag); - Flag = Chain.getValue(1); + Chain = DAG.getCopyToReg(Chain, dl, RetVal.first, RetVal.second, Glue); + Glue = Chain.getValue(1); RetOps.push_back( DAG.getRegister(RetVal.first, RetVal.second.getValueType())); } @@ -3366,8 +3366,8 @@ X86TargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv, Register RetValReg = (Subtarget.is64Bit() && !Subtarget.isTarget64BitILP32()) ? X86::RAX : X86::EAX; - Chain = DAG.getCopyToReg(Chain, dl, RetValReg, Val, Flag); - Flag = Chain.getValue(1); + Chain = DAG.getCopyToReg(Chain, dl, RetValReg, Val, Glue); + Glue = Chain.getValue(1); // RAX/EAX now acts like a return value. RetOps.push_back( @@ -3396,11 +3396,11 @@ X86TargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv, RetOps[0] = Chain; // Update chain. - // Add the flag if we have it. - if (Flag.getNode()) - RetOps.push_back(Flag); + // Add the glue if we have it. + if (Glue.getNode()) + RetOps.push_back(Glue); - X86ISD::NodeType opcode = X86ISD::RET_FLAG; + X86ISD::NodeType opcode = X86ISD::RET_GLUE; if (CallConv == CallingConv::X86_INTR) opcode = X86ISD::IRET; return DAG.getNode(opcode, dl, MVT::Other, RetOps); @@ -3423,7 +3423,7 @@ bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const { bool HasRet = false; for (const SDNode *U : Copy->uses()) { - if (U->getOpcode() != X86ISD::RET_FLAG) + if (U->getOpcode() != X86ISD::RET_GLUE) return false; // If we are returning more than one value, we can definitely // not make a tail call see PR19530 @@ -3464,15 +3464,15 @@ EVT X86TargetLowering::getTypeForExtReturn(LLVMContext &Context, EVT VT, /// \param VA The current 32 bit value that need to be assigned. /// \param NextVA The next 32 bit value that need to be assigned. /// \param Root The parent DAG node. -/// \param [in,out] InFlag Represents SDvalue in the parent DAG node for +/// \param [in,out] InGlue Represents SDvalue in the parent DAG node for /// glue purposes. In the case the DAG is already using /// physical register instead of virtual, we should glue -/// our new SDValue to InFlag SDvalue. +/// our new SDValue to InGlue SDvalue. /// \return a new SDvalue of size 64bit. static SDValue getv64i1Argument(CCValAssign &VA, CCValAssign &NextVA, SDValue &Root, SelectionDAG &DAG, const SDLoc &Dl, const X86Subtarget &Subtarget, - SDValue *InFlag = nullptr) { + SDValue *InGlue = nullptr) { assert((Subtarget.hasBWI()) && "Expected AVX512BW target!"); assert(Subtarget.is32Bit() && "Expecting 32 bit target"); assert(VA.getValVT() == MVT::v64i1 && @@ -3489,7 +3489,7 @@ static SDValue getv64i1Argument(CCValAssign &VA, CCValAssign &NextVA, const TargetRegisterClass *RC = &X86::GR32RegClass; // Read a 32 bit value from the registers. - if (nullptr == InFlag) { + if (nullptr == InGlue) { // When no physical register is present, // create an intermediate virtual register. Register Reg = MF.addLiveIn(VA.getLocReg(), RC); @@ -3500,11 +3500,11 @@ static SDValue getv64i1Argument(CCValAssign &VA, CCValAssign &NextVA, // When a physical register is available read the value from it and glue // the reads together. ArgValueLo = - DAG.getCopyFromReg(Root, Dl, VA.getLocReg(), MVT::i32, *InFlag); - *InFlag = ArgValueLo.getValue(2); + DAG.getCopyFromReg(Root, Dl, VA.getLocReg(), MVT::i32, *InGlue); + *InGlue = ArgValueLo.getValue(2); ArgValueHi = - DAG.getCopyFromReg(Root, Dl, NextVA.getLocReg(), MVT::i32, *InFlag); - *InFlag = ArgValueHi.getValue(2); + DAG.getCopyFromReg(Root, Dl, NextVA.getLocReg(), MVT::i32, *InGlue); + *InGlue = ArgValueHi.getValue(2); } // Convert the i32 type into v32i1 type. @@ -3557,7 +3557,7 @@ static SDValue lowerRegToMasks(const SDValue &ValArg, const EVT &ValVT, /// appropriate copies out of appropriate physical registers. /// SDValue X86TargetLowering::LowerCallResult( - SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg, + SDValue Chain, SDValue InGlue, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl &Ins, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl &InVals, uint32_t *RegMask) const { @@ -3617,12 +3617,12 @@ SDValue X86TargetLowering::LowerCallResult( assert(VA.getValVT() == MVT::v64i1 && "Currently the only custom case is when we split v64i1 to 2 regs"); Val = - getv64i1Argument(VA, RVLocs[++I], Chain, DAG, dl, Subtarget, &InFlag); + getv64i1Argument(VA, RVLocs[++I], Chain, DAG, dl, Subtarget, &InGlue); } else { - Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), CopyVT, InFlag) + Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), CopyVT, InGlue) .getValue(1); Val = Chain.getValue(0); - InFlag = Chain.getValue(2); + InGlue = Chain.getValue(2); } if (RoundAfterCopy) @@ -4842,12 +4842,12 @@ X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, } // Build a sequence of copy-to-reg nodes chained together with token chain - // and flag operands which copy the outgoing args into registers. - SDValue InFlag; + // and glue operands which copy the outgoing args into registers. + SDValue InGlue; for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, - RegsToPass[i].second, InFlag); - InFlag = Chain.getValue(1); + RegsToPass[i].second, InGlue); + InGlue = Chain.getValue(1); } if (DAG.getTarget().getCodeModel() == CodeModel::Large) { @@ -4869,13 +4869,13 @@ X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, Callee = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Callee); } - // Returns a chain & a flag for retval copy to use. + // Returns a chain & a glue for retval copy to use. SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); SmallVector Ops; if (!IsSibcall && isTailCall && !IsMustTail) { - Chain = DAG.getCALLSEQ_END(Chain, NumBytesToPop, 0, InFlag, dl); - InFlag = Chain.getValue(1); + Chain = DAG.getCALLSEQ_END(Chain, NumBytesToPop, 0, InGlue, dl); + InGlue = Chain.getValue(1); } Ops.push_back(Chain); @@ -4953,8 +4953,8 @@ X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, Ops.push_back(DAG.getRegisterMask(Mask)); } - if (InFlag.getNode()) - Ops.push_back(InFlag); + if (InGlue.getNode()) + Ops.push_back(InGlue); if (isTailCall) { // We used to do: @@ -4997,7 +4997,7 @@ X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, if (IsCFICall) Chain.getNode()->setCFIType(CLI.CFIType->getZExtValue()); - InFlag = Chain.getValue(1); + InGlue = Chain.getValue(1); DAG.addNoMergeSiteInfo(Chain.getNode(), CLI.NoMerge); DAG.addCallSiteInfo(Chain.getNode(), std::move(CSInfo)); @@ -5016,16 +5016,16 @@ X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, // pops that struct pointer. NumBytesForCalleeToPop = 4; - // Returns a flag for retval copy to use. + // Returns a glue for retval copy to use. if (!IsSibcall) { Chain = DAG.getCALLSEQ_END(Chain, NumBytesToPop, NumBytesForCalleeToPop, - InFlag, dl); - InFlag = Chain.getValue(1); + InGlue, dl); + InGlue = Chain.getValue(1); } // Handle result values, copying them out of physregs into vregs that we // return. - return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, dl, DAG, + return LowerCallResult(Chain, InGlue, CallConv, isVarArg, Ins, dl, DAG, InVals, RegMask); } @@ -20966,7 +20966,7 @@ X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const { static SDValue GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA, - SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg, + SDValue *InGlue, const EVT PtrVT, unsigned ReturnReg, unsigned char OperandFlags, bool LocalDynamic = false) { MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo(); SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); @@ -20979,8 +20979,8 @@ GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA, X86ISD::NodeType CallType = LocalDynamic ? X86ISD::TLSBASEADDR : X86ISD::TLSADDR; - if (InFlag) { - SDValue Ops[] = { Chain, TGA, *InFlag }; + if (InGlue) { + SDValue Ops[] = { Chain, TGA, *InGlue }; Chain = DAG.getNode(CallType, dl, NodeTys, Ops); } else { SDValue Ops[] = { Chain, TGA }; @@ -20991,22 +20991,22 @@ GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA, MFI.setAdjustsStack(true); MFI.setHasCalls(true); - SDValue Flag = Chain.getValue(1); - return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag); + SDValue Glue = Chain.getValue(1); + return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Glue); } // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit static SDValue LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG, const EVT PtrVT) { - SDValue InFlag; + SDValue InGlue; SDLoc dl(GA); // ? function entry point might be better SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX, DAG.getNode(X86ISD::GlobalBaseReg, - SDLoc(), PtrVT), InFlag); - InFlag = Chain.getValue(1); + SDLoc(), PtrVT), InGlue); + InGlue = Chain.getValue(1); - return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD); + return GetTLSADDR(DAG, Chain, GA, &InGlue, PtrVT, X86::EAX, X86II::MO_TLSGD); } // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit LP64 @@ -21041,11 +21041,11 @@ static SDValue LowerToTLSLocalDynamicModel(GlobalAddressSDNode *GA, Base = GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT, ReturnReg, X86II::MO_TLSLD, /*LocalDynamic=*/true); } else { - SDValue InFlag; + SDValue InGlue; SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX, - DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), InFlag); - InFlag = Chain.getValue(1); - Base = GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, + DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), InGlue); + InGlue = Chain.getValue(1); + Base = GetTLSADDR(DAG, Chain, GA, &InGlue, PtrVT, X86::EAX, X86II::MO_TLSLDM, /*LocalDynamic=*/true); } @@ -34989,7 +34989,7 @@ const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const { NODE_NAME_CASE(FSETCCM_SAE) NODE_NAME_CASE(CMOV) NODE_NAME_CASE(BRCOND) - NODE_NAME_CASE(RET_FLAG) + NODE_NAME_CASE(RET_GLUE) NODE_NAME_CASE(IRET) NODE_NAME_CASE(REP_STOS) NODE_NAME_CASE(REP_MOVS) @@ -58035,7 +58035,7 @@ LowerXConstraint(EVT ConstraintVT) const { // Lower @cc targets via setcc. SDValue X86TargetLowering::LowerAsmOutputForConstraint( - SDValue &Chain, SDValue &Flag, const SDLoc &DL, + SDValue &Chain, SDValue &Glue, const SDLoc &DL, const AsmOperandInfo &OpInfo, SelectionDAG &DAG) const { X86::CondCode Cond = parseConstraintCode(OpInfo.ConstraintCode); if (Cond == X86::COND_INVALID) @@ -58043,16 +58043,16 @@ SDValue X86TargetLowering::LowerAsmOutputForConstraint( // Check that return type is valid. if (OpInfo.ConstraintVT.isVector() || !OpInfo.ConstraintVT.isInteger() || OpInfo.ConstraintVT.getSizeInBits() < 8) - report_fatal_error("Flag output operand is of invalid type"); + report_fatal_error("Glue output operand is of invalid type"); // Get EFLAGS register. Only update chain when copyfrom is glued. - if (Flag.getNode()) { - Flag = DAG.getCopyFromReg(Chain, DL, X86::EFLAGS, MVT::i32, Flag); - Chain = Flag.getValue(1); + if (Glue.getNode()) { + Glue = DAG.getCopyFromReg(Chain, DL, X86::EFLAGS, MVT::i32, Glue); + Chain = Glue.getValue(1); } else - Flag = DAG.getCopyFromReg(Chain, DL, X86::EFLAGS, MVT::i32); + Glue = DAG.getCopyFromReg(Chain, DL, X86::EFLAGS, MVT::i32); // Extract CC code. - SDValue CC = getSETCC(Cond, Flag, DL, DAG); + SDValue CC = getSETCC(Cond, Glue, DL, DAG); // Extend to 32-bits SDValue Result = DAG.getNode(ISD::ZERO_EXTEND, DL, OpInfo.ConstraintVT, CC); diff --git a/llvm/lib/Target/X86/X86ISelLowering.h b/llvm/lib/Target/X86/X86ISelLowering.h index ab0d661..de170e5 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.h +++ b/llvm/lib/Target/X86/X86ISelLowering.h @@ -126,9 +126,9 @@ namespace llvm { /// operand 1 is the target address. NT_BRIND, - /// Return with a flag operand. Operand 0 is the chain operand, operand + /// Return with a glue operand. Operand 0 is the chain operand, operand /// 1 is the number of bytes of stack to pop. - RET_FLAG, + RET_GLUE, /// Return from interrupt. Operand 0 is the number of bytes to pop. IRET, diff --git a/llvm/lib/Target/X86/X86InstrControl.td b/llvm/lib/Target/X86/X86InstrControl.td index 475371d..8687990 100644 --- a/llvm/lib/Target/X86/X86InstrControl.td +++ b/llvm/lib/Target/X86/X86InstrControl.td @@ -16,7 +16,7 @@ // Return instructions. // -// The X86retflag return instructions are variadic because we may add ST0 and +// The X86retglue return instructions are variadic because we may add ST0 and // ST1 arguments when returning values on the x87 stack. let isTerminator = 1, isReturn = 1, isBarrier = 1, hasCtrlDep = 1, FPForm = SpecialFP, SchedRW = [WriteJumpLd] in { @@ -54,7 +54,7 @@ let isTerminator = 1, isReturn = 1, isBarrier = 1, def IRET64 : RI <0xcf, RawFrm, (outs), (ins), "iretq", []>, Requires<[In64BitMode]>; let isCodeGenOnly = 1 in def IRET : PseudoI<(outs), (ins i32imm:$adj), [(X86iret timm:$adj)]>; - def RET : PseudoI<(outs), (ins i32imm:$adj, variable_ops), [(X86retflag timm:$adj)]>; + def RET : PseudoI<(outs), (ins i32imm:$adj, variable_ops), [(X86retglue timm:$adj)]>; } // Unconditional branches. diff --git a/llvm/lib/Target/X86/X86InstrInfo.td b/llvm/lib/Target/X86/X86InstrInfo.td index d295208..1c7cb1d 100644 --- a/llvm/lib/Target/X86/X86InstrInfo.td +++ b/llvm/lib/Target/X86/X86InstrInfo.td @@ -173,7 +173,7 @@ def X86cas16 : SDNode<"X86ISD::LCMPXCHG16_DAG", SDTX86cas16pair, [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; -def X86retflag : SDNode<"X86ISD::RET_FLAG", SDTX86Ret, +def X86retglue : SDNode<"X86ISD::RET_GLUE", SDTX86Ret, [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; def X86iret : SDNode<"X86ISD::IRET", SDTX86Ret, [SDNPHasChain, SDNPOptInGlue]>; diff --git a/llvm/test/CodeGen/X86/merge-store-partially-alias-loads.ll b/llvm/test/CodeGen/X86/merge-store-partially-alias-loads.ll index 4d0d05e..76fedc3 100644 --- a/llvm/test/CodeGen/X86/merge-store-partially-alias-loads.ll +++ b/llvm/test/CodeGen/X86/merge-store-partially-alias-loads.ll @@ -25,7 +25,7 @@ ; DBGDAG-DAG: [[LOADTOKEN:t[0-9]+]]: ch = TokenFactor [[LD2]]:1, [[LD1]]:1 ; DBGDAG-DAG: [[ST2:t[0-9]+]]: ch = store<(store (s16) into %ir.tmp10, align 1)> [[LOADTOKEN]], [[LD2]], t{{[0-9]+}}, undef:i64 -; DBGDAG: X86ISD::RET_FLAG t{{[0-9]+}}, +; DBGDAG: X86ISD::RET_GLUE t{{[0-9]+}}, ; DBGDAG-LABEL: Instruction selection begins define void @merge_store_partial_overlap_load([4 x i8]* %tmp) { diff --git a/llvm/test/CodeGen/X86/selectiondag-debug-loc.ll b/llvm/test/CodeGen/X86/selectiondag-debug-loc.ll index 1f5397a..620b885 100644 --- a/llvm/test/CodeGen/X86/selectiondag-debug-loc.ll +++ b/llvm/test/CodeGen/X86/selectiondag-debug-loc.ll @@ -22,7 +22,7 @@ entry: %3 = load i8, ptr %2, align 1, !dbg !20 %conv = sext i8 %3 to i32, !dbg !20 - ; CHECK: X86ISD::RET_FLAG {{.*}}, TargetConstant:i32<0>, Register:i32 $eax, {{.*}}, :2:3 + ; CHECK: X86ISD::RET_GLUE {{.*}}, TargetConstant:i32<0>, Register:i32 $eax, {{.*}}, :2:3 ret i32 %conv, !dbg !22 } -- 2.7.4