From efd5acf1201f593a70937b140da72e49b7d0e7b3 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Tue, 13 Sep 2022 09:07:56 -0700 Subject: [PATCH] [LegalizeTypes][NVPTX] Remove extra compare from fallback code for ISD::ADD in ExpandIntRes_ADDSUB. This is the ultimate fallback code if UADDO isn't supported. If the target uses 0/1 we used one compare, but if the target doesn't use 0/1 we emitted two compares. Regardless of boolean constants we should only need to check that the Result is less than one of the original operands. So we only need one compare. Reviewed By: spatel Differential Revision: https://reviews.llvm.org/D133708 --- .../CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp | 24 ++++++++-------------- llvm/test/CodeGen/NVPTX/add-sub-128bit.ll | 3 +-- 2 files changed, 10 insertions(+), 17 deletions(-) diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp index 98d080f..1684e8c 100644 --- a/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp @@ -2988,23 +2988,17 @@ void DAGTypeLegalizer::ExpandIntRes_ADDSUB(SDNode *N, if (N->getOpcode() == ISD::ADD) { Lo = DAG.getNode(ISD::ADD, dl, NVT, LoOps); Hi = DAG.getNode(ISD::ADD, dl, NVT, makeArrayRef(HiOps, 2)); - SDValue Cmp1 = DAG.getSetCC(dl, getSetCCResultType(NVT), Lo, LoOps[0], - ISD::SETULT); + SDValue Cmp = DAG.getSetCC(dl, getSetCCResultType(NVT), Lo, LoOps[0], + ISD::SETULT); - if (BoolType == TargetLoweringBase::ZeroOrOneBooleanContent) { - SDValue Carry = DAG.getZExtOrTrunc(Cmp1, dl, NVT); - Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, Carry); - return; - } + SDValue Carry; + if (BoolType == TargetLoweringBase::ZeroOrOneBooleanContent) + Carry = DAG.getZExtOrTrunc(Cmp, dl, NVT); + else + Carry = DAG.getSelect(dl, NVT, Cmp, DAG.getConstant(1, dl, NVT), + DAG.getConstant(0, dl, NVT)); - SDValue Carry1 = DAG.getSelect(dl, NVT, Cmp1, - DAG.getConstant(1, dl, NVT), - DAG.getConstant(0, dl, NVT)); - SDValue Cmp2 = DAG.getSetCC(dl, getSetCCResultType(NVT), Lo, LoOps[1], - ISD::SETULT); - SDValue Carry2 = DAG.getSelect(dl, NVT, Cmp2, - DAG.getConstant(1, dl, NVT), Carry1); - Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, Carry2); + Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, Carry); } else { Lo = DAG.getNode(ISD::SUB, dl, NVT, LoOps); Hi = DAG.getNode(ISD::SUB, dl, NVT, makeArrayRef(HiOps, 2)); diff --git a/llvm/test/CodeGen/NVPTX/add-sub-128bit.ll b/llvm/test/CodeGen/NVPTX/add-sub-128bit.ll index f096bad..7c68971 100644 --- a/llvm/test/CodeGen/NVPTX/add-sub-128bit.ll +++ b/llvm/test/CodeGen/NVPTX/add-sub-128bit.ll @@ -7,10 +7,9 @@ target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f3 ; COMMON-LABEL: test_add define i128 @test_add(i128 %a, i128 %b) { ; NOCARRY: add.s64 -; NOCARRY-NEXT: setp.lt.u64 +; NOCARRY-NEXT: add.s64 ; NOCARRY-NEXT: setp.lt.u64 ; NOCARRY-NEXT: selp.u64 -; NOCARRY-NEXT: selp.b64 ; NOCARRY-NEXT: add.s64 ; CARRY: add.cc.s64 -- 2.7.4