From ef979cb3605ced6b420a8a9227b518997ee08aab Mon Sep 17 00:00:00 2001 From: Minkyu Kang Date: Thu, 23 Jul 2009 11:23:09 +0900 Subject: [PATCH] s5pc100: smdkc100: build fix Signed-off-by: Minkyu Kang --- board/samsung/smdkc100/lowlevel_init.S | 32 +++++++++++------- board/samsung/smdkc100/mem_setup.S | 1 + board/samsung/smdkc100/onenand.c | 61 +++++++++++++++++++--------------- include/configs/smdkc100.h | 1 + 4 files changed, 57 insertions(+), 38 deletions(-) diff --git a/board/samsung/smdkc100/lowlevel_init.S b/board/samsung/smdkc100/lowlevel_init.S index bf52dfb..00d9b4d 100644 --- a/board/samsung/smdkc100/lowlevel_init.S +++ b/board/samsung/smdkc100/lowlevel_init.S @@ -26,6 +26,12 @@ #include #include #include +#include +#include +#include +#include +#include +#include #ifdef CONFIG_SERIAL0 #define UART_CONSOLE_BASE UARTx_OFFSET(0) @@ -50,17 +56,23 @@ _TEXT_BASE: lowlevel_init: mov r9, lr + /* r5 has always zero */ + mov r5, #0 + + ldr r8, =S5PC100_GPIO_BASE(0) + +#if 0 /* IO retension release */ ldr r0, =S5P_OTHERS @0xE0108200 ldr r1, [r0] ldr r2, =(1 << 31) @IO_RET_REL orr r1, r1, r2 str r1, [r0] +#endif /* Disable Watchdog */ ldr r0, =S5P_WATCHDOG_BASE(0x0) @0xEA200000 orr r0, r0, #0x0 - mov r5, #0 str r5, [r0] #ifndef CONFIG_ONENAND_IPL @@ -93,9 +105,6 @@ lowlevel_init: str r5, [r2, #VIC_INTADDRESS_OFFSET] #endif - /* init system clock */ - bl system_clock_init - #ifndef CONFIG_ONENAND_IPL /* for UART */ bl uart_asm_init @@ -104,6 +113,9 @@ lowlevel_init: #endif #ifdef CONFIG_ONENAND_IPL + /* init system clock */ + bl system_clock_init + bl mem_ctrl_asm_init /* Wakeup support. Don't know if it's going to be used, untested. */ @@ -195,15 +207,11 @@ system_clock_init: * uart_asm_init: Initialize UART's pins */ uart_asm_init: - /* set GPIO to enable UART */ - ldr r0, =S5P_GPIO_A0_CON + mov r0, r8 ldr r1, =0x22222222 - str r1, [r0] - - /* uart_sel GPK0[5] */ - ldr r0, =S5P_GPIO_A1_CON - ldr r1, =0x2222 - ldr r1, [r0] + str r1, [r0, #S5PC100_GPIO_A0_OFFSET] @ GPA0_CON + ldr r1, =0x00022222 + str r1, [r0, #S5PC100_GPIO_A1_OFFSET] @ GPA1_CON mov pc, lr diff --git a/board/samsung/smdkc100/mem_setup.S b/board/samsung/smdkc100/mem_setup.S index 7b426e9..7e5ba72 100644 --- a/board/samsung/smdkc100/mem_setup.S +++ b/board/samsung/smdkc100/mem_setup.S @@ -27,6 +27,7 @@ */ #include +#include .globl mem_ctrl_asm_init mem_ctrl_asm_init: diff --git a/board/samsung/smdkc100/onenand.c b/board/samsung/smdkc100/onenand.c index 11c6379..94deab5 100644 --- a/board/samsung/smdkc100/onenand.c +++ b/board/samsung/smdkc100/onenand.c @@ -9,66 +9,78 @@ #include -#include +#include #include +#include -#define DPRINTK(format, args...) \ -do { \ - printk("%s[%d]: " format "\n", __func__, __LINE__, ##args); \ -} while (0) +extern void s3c_onenand_init(struct mtd_info *); + +static inline int onenand_read_reg(int offset) +{ + return readl(CONFIG_SYS_ONENAND_BASE + offset); +} + +static inline void onenand_write_reg(int value, int offset) +{ + writel(value, CONFIG_SYS_ONENAND_BASE + offset); +} void onenand_board_init(struct mtd_info *mtd) { struct onenand_chip *this = mtd->priv; int value; + this->base = (void *)CONFIG_SYS_ONENAND_BASE; + +#if 0 /* D0 Domain system 1 clock gating */ - value = S5P_CLK_GATE_D00_REG; + value = readl(S5P_CLK_GATE_D00); value &= ~(1 << 2); /* CFCON */ value |= (1 << 2); - S5P_CLK_GATE_D00_REG = value; + writel(value, S5P_CLK_GATE_D00); /* D0 Domain memory clock gating */ - value = S5P_CLK_GATE_D01_REG; + value = readl(S5P_CLK_GATE_D01); value &= ~(1 << 2); /* CLK_ONENANDC */ value |= (1 << 2); - S5P_CLK_GATE_D01_REG = value; + writel(value, S5P_CLK_GATE_D01); +#endif /* System Special clock gating */ - value = S5P_CLK_GATE_SCLK0_REG; + value = readl(S5P_CLK_GATE_SCLK0); value &= ~(1 << 2); /* OneNAND */ value |= (1 << 2); - S5P_CLK_GATE_SCLK0_REG = value; + writel(value, S5P_CLK_GATE_SCLK0); - value = S5P_CLK_SRC0_REG; + value = readl(S5P_CLK_SRC0); value &= ~(1 << 24); /* MUX_1nand: 0 from HCLKD0 */ // value |= (1 << 24); /* MUX_1nand: 1 from DIV_D1_BUS */ value &= ~(1 << 20); /* MUX_HREF: 0 from FIN_27M */ - S5P_CLK_SRC0_REG = value; + writel(value, S5P_CLK_SRC0); - value = S5P_CLK_DIV1_REG; + value = readl(S5P_CLK_DIV1); // value &= ~(3 << 20); /* DIV_1nand: 1 / (ratio+1) */ // value |= (0 << 20); /* ratio = 1 */ value &= ~(3 << 16); value |= (1 << 16); - S5P_CLK_DIV1_REG = value; + writel(value, S5P_CLK_DIV1); - MEM_RESET0_REG = ONENAND_MEM_RESET_COLD; + onenand_write_reg(ONENAND_MEM_RESET_COLD, MEM_RESET_OFFSET); - while (!(INT_ERR_STAT0_REG & RST_CMP)) + while (!(onenand_read_reg(INT_ERR_STAT_OFFSET) & RST_CMP)) continue; - INT_ERR_ACK0_REG = RST_CMP; + onenand_write_reg(RST_CMP, INT_ERR_ACK_OFFSET); - ACC_CLOCK0_REG = 0x3; + onenand_write_reg(0x3, ACC_CLOCK_OFFSET); - INT_ERR_MASK0_REG = 0x3fff; - INT_PIN_ENABLE0_REG = (1 << 0); /* Enable */ + onenand_write_reg(0x3fff, INT_ERR_MASK_OFFSET); + onenand_write_reg(1 << 0, INT_PIN_ENABLE_OFFSET); /* Enable */ - value = INT_ERR_MASK0_REG; + value = onenand_read_reg(INT_ERR_MASK_OFFSET); value &= ~RDY_ACT; - INT_ERR_MASK0_REG = value; + onenand_write_reg(value, INT_ERR_MASK_OFFSET); #if 0 MEM_CFG0_REG |= @@ -86,8 +98,5 @@ void onenand_board_init(struct mtd_info *mtd) // MEM_CFG0_REG |= ONENAND_SYS_CFG1_VHF; // MEM_CFG0_REG |= ONENAND_SYS_CFG1_HF; - this->base = (void *) 0xe7100000; - this->base = (void *)CONFIG_SYS_ONENAND_BASE; - s3c_onenand_init(mtd); } diff --git a/include/configs/smdkc100.h b/include/configs/smdkc100.h index 0132c3b..c63f78f2 100644 --- a/include/configs/smdkc100.h +++ b/include/configs/smdkc100.h @@ -134,6 +134,7 @@ #define CONFIG_BOOTARGS "root=/dev/mtdblock5 ubi.mtd=4" \ " rootfstype=cramfs " CONFIG_COMMON_BOOT +#define CONFIG_USE_BIG_UBOOT #ifdef CONFIG_USE_BIG_UBOOT #define CONFIG_UPDATEB "updateb=onenand erase 0x0 0x40000;" \ " onenand write 0x22008000 0x0 0x40000\0" -- 2.7.4