From ef03b401266b687dab522dcf9a4e411074262898 Mon Sep 17 00:00:00 2001 From: Tomi Valkeinen Date: Wed, 18 May 2016 13:52:14 +0300 Subject: [PATCH] drm/omap: cleanup dispc_fclk_rate() With the new PLL helpers, we can clean up the dispc_fclk_rate(). This will also make dispc_fclk_rate() support clock sources it didn't support earlier. Signed-off-by: Tomi Valkeinen --- drivers/gpu/drm/omapdrm/dss/dispc.c | 31 +++++++++++-------------------- 1 file changed, 11 insertions(+), 20 deletions(-) diff --git a/drivers/gpu/drm/omapdrm/dss/dispc.c b/drivers/gpu/drm/omapdrm/dss/dispc.c index 01994d0..7b78da6 100644 --- a/drivers/gpu/drm/omapdrm/dss/dispc.c +++ b/drivers/gpu/drm/omapdrm/dss/dispc.c @@ -3299,30 +3299,21 @@ static void dispc_mgr_get_lcd_divisor(enum omap_channel channel, int *lck_div, static unsigned long dispc_fclk_rate(void) { - struct dss_pll *pll; - unsigned long r = 0; + unsigned long r; + enum dss_clk_source src; - switch (dss_get_dispc_clk_source()) { - case DSS_CLK_SRC_FCK: + src = dss_get_dispc_clk_source(); + + if (src == DSS_CLK_SRC_FCK) { r = dss_get_dispc_clk_rate(); - break; - case DSS_CLK_SRC_PLL1_1: - pll = dss_pll_find("dsi0"); - if (!pll) - pll = dss_pll_find("video0"); + } else { + struct dss_pll *pll; + unsigned clkout_idx; - r = pll->cinfo.clkout[0]; - break; - case DSS_CLK_SRC_PLL2_1: - pll = dss_pll_find("dsi1"); - if (!pll) - pll = dss_pll_find("video1"); + pll = dss_pll_find_by_src(src); + clkout_idx = dss_pll_get_clkout_idx_for_src(src); - r = pll->cinfo.clkout[0]; - break; - default: - BUG(); - return 0; + r = pll->cinfo.clkout[clkout_idx]; } return r; -- 2.7.4