From eebb2dedb27652761f9c59c4a489ba46c583ab4e Mon Sep 17 00:00:00 2001 From: Jason Ekstrand Date: Tue, 9 Nov 2021 22:55:49 -0600 Subject: [PATCH] intel/fs: Add a NONE scheduling mode MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit While our LIFO scheduling mode attempts to optimize for register pressure, it's often hard for a scheduling algorithm to do better than the instruction order provided by the shader author. Shader authors often do perfectly reasonable things like using texture results immediately after fetching them or constructing texture coordinates immediately before the texture op. When we throw all the instruction ordering information away, we loose any help the author may have given us. By attempting NONE before we fall back to the worst case LIFO mode. And, yes, I tried this with NONE both before and after LIFO and doing NONE before LIFO is substantially better, according to shader-db. total instructions in shared programs: 19673152 -> 19665202 (-0.04%) instructions in affected programs: 33669 -> 25719 (-23.61%) helped: 20 HURT: 0 helped stats (abs) min: 15 max: 4609 x̄: 397.50 x̃: 107 helped stats (rel) min: 2.33% max: 67.50% x̄: 14.60% x̃: 9.12% 95% mean confidence interval for instructions value: -867.61 72.61 95% mean confidence interval for instructions %-change: -21.74% -7.46% Inconclusive result (value mean confidence interval includes 0). total cycles in shared programs: 935562500 -> 935020920 (-0.06%) cycles in affected programs: 18620349 -> 18078769 (-2.91%) helped: 104 HURT: 48 helped stats (abs) min: 88 max: 60986 x̄: 8031.48 x̃: 3680 helped stats (rel) min: 0.61% max: 51.44% x̄: 14.95% x̃: 8.87% HURT stats (abs) min: 10 max: 54724 x̄: 6118.62 x̃: 1530 HURT stats (rel) min: 0.13% max: 46.45% x̄: 10.28% x̃: 6.46% 95% mean confidence interval for cycles value: -5724.34 -1401.71 95% mean confidence interval for cycles %-change: -9.86% -4.10% Cycles are helped. total spills in shared programs: 12158 -> 10327 (-15.06%) spills in affected programs: 1831 -> 0 helped: 20 HURT: 0 total fills in shared programs: 14749 -> 12635 (-14.33%) fills in affected programs: 2114 -> 0 helped: 20 HURT: 0 LOST: 8 GAINED: 649 Reviewed-by: Ian Romanick Part-of: --- src/intel/compiler/brw_fs.cpp | 5 ++++- src/intel/compiler/brw_shader.h | 1 + 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp index 32adfea..a3c2eb4 100644 --- a/src/intel/compiler/brw_fs.cpp +++ b/src/intel/compiler/brw_fs.cpp @@ -8652,12 +8652,14 @@ fs_visitor::allocate_registers(bool allow_spilling) static const enum instruction_scheduler_mode pre_modes[] = { SCHEDULE_PRE, SCHEDULE_PRE_NON_LIFO, + SCHEDULE_NONE, SCHEDULE_PRE_LIFO, }; static const char *scheduler_mode_name[] = { "top-down", "non-lifo", + "none", "lifo" }; @@ -8697,7 +8699,8 @@ fs_visitor::allocate_registers(bool allow_spilling) invalidate_analysis(DEPENDENCY_INSTRUCTIONS); } - schedule_instructions(pre_modes[i]); + if (pre_modes[i] != SCHEDULE_NONE) + schedule_instructions(pre_modes[i]); this->shader_stats.scheduler_mode = scheduler_mode_name[i]; if (0) { diff --git a/src/intel/compiler/brw_shader.h b/src/intel/compiler/brw_shader.h index d2eb75d..6afe9c7 100644 --- a/src/intel/compiler/brw_shader.h +++ b/src/intel/compiler/brw_shader.h @@ -38,6 +38,7 @@ enum instruction_scheduler_mode { SCHEDULE_PRE_NON_LIFO, SCHEDULE_PRE_LIFO, SCHEDULE_POST, + SCHEDULE_NONE, }; #define UBO_START ((1 << 16) - 4) -- 2.7.4