From eeb3bfd74ab37c04810c325775ba149740dc1039 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Sun, 13 Mar 2022 13:57:43 -0700 Subject: [PATCH] [RISCV] Merge ReplaceNodeResults code for SHFL and GREV/GORC. NFC --- llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 18 ++---------------- 1 file changed, 2 insertions(+), 16 deletions(-) diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp index eb42a13..43fc52d 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -6816,7 +6816,8 @@ void RISCVTargetLowering::ReplaceNodeResults(SDNode *N, break; } case RISCVISD::GREV: - case RISCVISD::GORC: { + case RISCVISD::GORC: + case RISCVISD::SHFL: { MVT VT = N->getSimpleValueType(0); MVT XLenVT = Subtarget.getXLenVT(); assert((VT == MVT::i16 || (VT == MVT::i32 && Subtarget.is64Bit())) && @@ -6835,21 +6836,6 @@ void RISCVTargetLowering::ReplaceNodeResults(SDNode *N, Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, VT, NewRes)); break; } - case RISCVISD::SHFL: { - // There is no SHFLIW instruction, but we can just promote the operation. - assert(N->getValueType(0) == MVT::i32 && Subtarget.is64Bit() && - "Unexpected custom legalisation"); - assert(isa(N->getOperand(1)) && "Expected constant"); - SDValue NewOp0 = - DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, N->getOperand(0)); - SDValue NewOp1 = - DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, N->getOperand(1)); - SDValue NewRes = DAG.getNode(RISCVISD::SHFL, DL, MVT::i64, NewOp0, NewOp1); - // ReplaceNodeResults requires we maintain the same type for the return - // value. - Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, NewRes)); - break; - } case ISD::BSWAP: case ISD::BITREVERSE: { MVT VT = N->getSimpleValueType(0); -- 2.7.4