From ee72359c658f5e6759f9bbd2964bf5fc86e679ef Mon Sep 17 00:00:00 2001 From: Simon Pilgrim Date: Mon, 3 Jul 2023 17:18:23 +0100 Subject: [PATCH] [X86] Remove unnecessary VPDPB/VPDPW overrides from AlderlakeP model Noticed while trying to resurrect D138359 - the overrides matched the base class schedule WriteVecIMul definition --- llvm/lib/Target/X86/X86SchedAlderlakeP.td | 7 ------- 1 file changed, 7 deletions(-) diff --git a/llvm/lib/Target/X86/X86SchedAlderlakeP.td b/llvm/lib/Target/X86/X86SchedAlderlakeP.td index 2cf5c6fe..eb7dcfc 100644 --- a/llvm/lib/Target/X86/X86SchedAlderlakeP.td +++ b/llvm/lib/Target/X86/X86SchedAlderlakeP.td @@ -2304,13 +2304,6 @@ def ADLPWriteResGroup264 : SchedWriteRes<[ADLPPort01_05, ADLPPort02_03_11]> { def : InstRW<[ADLPWriteResGroup264, ReadAfterVecYLd], (instregex "^VSHUFP(D|S)Yrmi$")>; def : InstRW<[ADLPWriteResGroup264, ReadAfterVecYLd], (instrs VPBLENDWYrmi)>; -def ADLPWriteResGroup265 : SchedWriteRes<[ADLPPort00_01, ADLPPort02_03_11]> { - let Latency = 13; - let NumMicroOps = 2; -} -def : InstRW<[ADLPWriteResGroup265], (instregex "^VPDP(BU|WS)SD((SY)?)rm$", - "^VPDP(BU|WS)SD(S|Y)rm$")>; - def ADLPWriteResGroup266 : SchedWriteRes<[ADLPPort00_01, ADLPPort01_05, ADLPPort02_03_11]> { let ResourceCycles = [1, 2, 1]; let Latency = 10; -- 2.7.4