From ee718489fe58ec4230b9eb6582e49ec7113ab8e8 Mon Sep 17 00:00:00 2001 From: "bmeurer@chromium.org" Date: Thu, 22 Aug 2013 11:58:20 +0000 Subject: [PATCH] Drop unused rdtsc instruction. We do not use rdtsc anywhere and we won't ever use that in the future, as it is totally unusable with multicore and out of order execution. R=jkummerow@chromium.org Review URL: https://codereview.chromium.org/23112016 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@16268 ce2b1a6d-e550-0410-aec6-3dcde31c8c00 --- src/flag-definitions.h | 2 -- src/ia32/assembler-ia32.cc | 8 -------- src/ia32/assembler-ia32.h | 2 -- src/ia32/disasm-ia32.cc | 1 - src/platform-posix.cc | 2 +- src/v8globals.h | 1 - src/x64/assembler-x64.cc | 7 ------- src/x64/assembler-x64.h | 2 -- src/x64/disasm-x64.cc | 6 ++---- test/cctest/test-disasm-ia32.cc | 5 ----- test/cctest/test-disasm-x64.cc | 5 ----- 11 files changed, 3 insertions(+), 38 deletions(-) diff --git a/src/flag-definitions.h b/src/flag-definitions.h index f5f2ef3..aed8591 100644 --- a/src/flag-definitions.h +++ b/src/flag-definitions.h @@ -356,8 +356,6 @@ DEFINE_bool(enable_sse4_1, true, "enable use of SSE4.1 instructions if available") DEFINE_bool(enable_cmov, true, "enable use of CMOV instruction if available") -DEFINE_bool(enable_rdtsc, true, - "enable use of RDTSC instruction if available") DEFINE_bool(enable_sahf, true, "enable use of SAHF instruction if available (X64 only)") DEFINE_bool(enable_vfp3, ENABLE_VFP3_DEFAULT, diff --git a/src/ia32/assembler-ia32.cc b/src/ia32/assembler-ia32.cc index 37218e5..ab4e0a4 100644 --- a/src/ia32/assembler-ia32.cc +++ b/src/ia32/assembler-ia32.cc @@ -1310,14 +1310,6 @@ void Assembler::nop() { } -void Assembler::rdtsc() { - ASSERT(IsEnabled(RDTSC)); - EnsureSpace ensure_space(this); - EMIT(0x0F); - EMIT(0x31); -} - - void Assembler::ret(int imm16) { EnsureSpace ensure_space(this); ASSERT(is_uint16(imm16)); diff --git a/src/ia32/assembler-ia32.h b/src/ia32/assembler-ia32.h index c102937..d6b6dab 100644 --- a/src/ia32/assembler-ia32.h +++ b/src/ia32/assembler-ia32.h @@ -537,7 +537,6 @@ class CpuFeatures : public AllStatic { if (f == SSE3 && !FLAG_enable_sse3) return false; if (f == SSE4_1 && !FLAG_enable_sse4_1) return false; if (f == CMOV && !FLAG_enable_cmov) return false; - if (f == RDTSC && !FLAG_enable_rdtsc) return false; return (supported_ & (static_cast(1) << f)) != 0; } @@ -870,7 +869,6 @@ class Assembler : public AssemblerBase { void hlt(); void int3(); void nop(); - void rdtsc(); void ret(int imm16); // Label operations & relative jumps (PPUM Appendix D) diff --git a/src/ia32/disasm-ia32.cc b/src/ia32/disasm-ia32.cc index c43f11c..892b66e 100644 --- a/src/ia32/disasm-ia32.cc +++ b/src/ia32/disasm-ia32.cc @@ -862,7 +862,6 @@ static const char* F0Mnem(byte f0byte) { switch (f0byte) { case 0x18: return "prefetch"; case 0xA2: return "cpuid"; - case 0x31: return "rdtsc"; case 0xBE: return "movsx_b"; case 0xBF: return "movsx_w"; case 0xB6: return "movzx_b"; diff --git a/src/platform-posix.cc b/src/platform-posix.cc index 13b819b..f7ab8a1 100644 --- a/src/platform-posix.cc +++ b/src/platform-posix.cc @@ -83,7 +83,7 @@ uint64_t OS::CpuFeaturesImpliedByPlatform() { // Mac OS X requires all these to install so we can assume they are present. // These constants are defined by the CPUid instructions. const uint64_t one = 1; - return (one << SSE2) | (one << CMOV) | (one << RDTSC) | (one << CPUID); + return (one << SSE2) | (one << CMOV) | (one << CPUID); #else return 0; // Nothing special about the other systems. #endif diff --git a/src/v8globals.h b/src/v8globals.h index 6ec7547..00693fa 100644 --- a/src/v8globals.h +++ b/src/v8globals.h @@ -438,7 +438,6 @@ enum CpuFeature { SSE4_1 = 32 + 19, // x86 SSE3 = 32 + 0, // x86 SSE2 = 26, // x86 CMOV = 15, // x86 - RDTSC = 4, // x86 CPUID = 10, // x86 VFP3 = 1, // ARM ARMv7 = 2, // ARM diff --git a/src/x64/assembler-x64.cc b/src/x64/assembler-x64.cc index 8969d89..68d2c05 100644 --- a/src/x64/assembler-x64.cc +++ b/src/x64/assembler-x64.cc @@ -1919,13 +1919,6 @@ void Assembler::pushfq() { } -void Assembler::rdtsc() { - EnsureSpace ensure_space(this); - emit(0x0F); - emit(0x31); -} - - void Assembler::ret(int imm16) { EnsureSpace ensure_space(this); ASSERT(is_uint16(imm16)); diff --git a/src/x64/assembler-x64.h b/src/x64/assembler-x64.h index 4e36b6e..d92849a 100644 --- a/src/x64/assembler-x64.h +++ b/src/x64/assembler-x64.h @@ -475,7 +475,6 @@ class CpuFeatures : public AllStatic { if (f == SSE3 && !FLAG_enable_sse3) return false; if (f == SSE4_1 && !FLAG_enable_sse4_1) return false; if (f == CMOV && !FLAG_enable_cmov) return false; - if (f == RDTSC && !FLAG_enable_rdtsc) return false; if (f == SAHF && !FLAG_enable_sahf) return false; return (supported_ & (static_cast(1) << f)) != 0; } @@ -1176,7 +1175,6 @@ class Assembler : public AssemblerBase { void hlt(); void int3(); void nop(); - void rdtsc(); void ret(int imm16); void setcc(Condition cc, Register reg); diff --git a/src/x64/disasm-x64.cc b/src/x64/disasm-x64.cc index eefa703..e9ace15 100644 --- a/src/x64/disasm-x64.cc +++ b/src/x64/disasm-x64.cc @@ -1229,8 +1229,8 @@ int DisassemblerX64::TwoByteOpcodeInstruction(byte* data) { current += PrintRightXMMOperand(current); AppendToBuffer(", %s", NameOfXMMRegister(regop)); - } else if (opcode == 0xA2 || opcode == 0x31) { - // RDTSC or CPUID + } else if (opcode == 0xA2) { + // CPUID AppendToBuffer("%s", mnemonic); } else if ((opcode & 0xF0) == 0x40) { @@ -1294,8 +1294,6 @@ const char* DisassemblerX64::TwoByteMnemonic(byte opcode) { return "nop"; case 0x2A: // F2/F3 prefix. return "cvtsi2s"; - case 0x31: - return "rdtsc"; case 0x51: // F2 prefix. return "sqrtsd"; case 0x58: // F2 prefix. diff --git a/test/cctest/test-disasm-ia32.cc b/test/cctest/test-disasm-ia32.cc index 14447b2..90469e5 100644 --- a/test/cctest/test-disasm-ia32.cc +++ b/test/cctest/test-disasm-ia32.cc @@ -104,11 +104,6 @@ TEST(DisasmIa320) { CpuFeatureScope fscope(&assm, CPUID); __ cpuid(); } - { - CHECK(CpuFeatures::IsSupported(RDTSC)); - CpuFeatureScope fscope(&assm, RDTSC); - __ rdtsc(); - } __ movsx_b(edx, ecx); __ movsx_w(edx, ecx); __ movzx_b(edx, ecx); diff --git a/test/cctest/test-disasm-x64.cc b/test/cctest/test-disasm-x64.cc index 1c7f416..1ff9fd3 100644 --- a/test/cctest/test-disasm-x64.cc +++ b/test/cctest/test-disasm-x64.cc @@ -95,11 +95,6 @@ TEST(DisasmX64) { CpuFeatures::Scope fscope(CPUID); __ cpuid(); } - { - CHECK(CpuFeatures::IsSupported(RDTSC)); - CpuFeatures::Scope fscope(RDTSC); - __ rdtsc(); - } __ movsxbq(rdx, Operand(rcx, 0)); __ movsxwq(rdx, Operand(rcx, 0)); __ movzxbl(rdx, Operand(rcx, 0)); -- 2.7.4