From ee6872beb1912af41a506c8aea34af7d2f873d04 Mon Sep 17 00:00:00 2001 From: Igor Tsimbalist Date: Fri, 20 Oct 2017 23:56:30 +0300 Subject: [PATCH] Enable Intel AVX512_BITALG instructions. Intel has disclosed a set of new instructions. The spec is https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf gas/ * config/tc-i386.c (cpu_arch): Add .avx512_bitalg. (cpu_noarch): noavx512_bitalg. * doc/c-i386.texi: Document .avx512_bitalg, noavx512_bitalg. * testsuite/gas/i386/i386.exp: Add AVX512_BITALG tests. * testsuite/gas/i386/avx512f_bitalg-intel.d: New test. * testsuite/gas/i386/avx512f_bitalg.d: Likewise. * testsuite/gas/i386/avx512f_bitalg.s: Likewise. * testsuite/gas/i386/avx512vl_bitalg-intel.d: Likewise. * testsuite/gas/i386/avx512vl_bitalg.d: Likewise. * testsuite/gas/i386/avx512vl_bitalg.s: Likewise. * testsuite/gas/i386/x86-64-avx512f_bitalg-intel.d: Likewise. * testsuite/gas/i386/x86-64-avx512f_bitalg.d: Likewise. * testsuite/gas/i386/x86-64-avx512f_bitalg.s: Likewise. * testsuite/gas/i386/x86-64-avx512vl_bitalg-intel.d: Likewise. * testsuite/gas/i386/x86-64-avx512vl_bitalg.d: Likewise. * testsuite/gas/i386/x86-64-avx512vl_bitalg.s: Likewise. opcodes/ * i386-dis.c (enum): Add PREFIX_EVEX_0F3854, PREFIX_EVEX_0F388F. (enum): Add EVEX_W_0F3854_P_2. * i386-dis-evex.h (evex_table): Updated. * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BITALG, CPU_ANY_AVX512_BITALG_FLAGS. Update CPU_ANY_AVX512F_FLAGS. (cpu_flags): Add CpuAVX512_BITALG. * i386-opc.h (enum): Add CpuAVX512_BITALG. (i386_cpu_flags): Add cpuavx512_bitalg.. * i386-opc.tbl: Add Intel AVX512_BITALG instructions. * i386-init.h: Regenerate. * i386-tbl.h: Likewise. --- gas/config/tc-i386.c | 3 + gas/doc/c-i386.texi | 3 + gas/testsuite/gas/i386/avx512bitalg-intel.d | 64 +++++++++++ gas/testsuite/gas/i386/avx512bitalg.d | 64 +++++++++++ gas/testsuite/gas/i386/avx512bitalg.s | 67 ++++++++++++ gas/testsuite/gas/i386/avx512bitalg_vl-intel.d | 96 +++++++++++++++++ gas/testsuite/gas/i386/avx512bitalg_vl.d | 96 +++++++++++++++++ gas/testsuite/gas/i386/avx512bitalg_vl.s | 99 +++++++++++++++++ gas/testsuite/gas/i386/i386.exp | 8 ++ gas/testsuite/gas/i386/x86-64-avx512bitalg-intel.d | 64 +++++++++++ gas/testsuite/gas/i386/x86-64-avx512bitalg.d | 64 +++++++++++ gas/testsuite/gas/i386/x86-64-avx512bitalg.s | 67 ++++++++++++ .../gas/i386/x86-64-avx512bitalg_vl-intel.d | 116 ++++++++++++++++++++ gas/testsuite/gas/i386/x86-64-avx512bitalg_vl.d | 116 ++++++++++++++++++++ gas/testsuite/gas/i386/x86-64-avx512bitalg_vl.s | 119 +++++++++++++++++++++ opcodes/i386-dis-evex.h | 21 +++- opcodes/i386-dis.c | 3 + opcodes/i386-gen.c | 7 +- opcodes/i386-opc.h | 3 + opcodes/i386-opc.tbl | 20 ++++ 20 files changed, 1097 insertions(+), 3 deletions(-) create mode 100644 gas/testsuite/gas/i386/avx512bitalg-intel.d create mode 100644 gas/testsuite/gas/i386/avx512bitalg.d create mode 100644 gas/testsuite/gas/i386/avx512bitalg.s create mode 100644 gas/testsuite/gas/i386/avx512bitalg_vl-intel.d create mode 100644 gas/testsuite/gas/i386/avx512bitalg_vl.d create mode 100644 gas/testsuite/gas/i386/avx512bitalg_vl.s create mode 100644 gas/testsuite/gas/i386/x86-64-avx512bitalg-intel.d create mode 100644 gas/testsuite/gas/i386/x86-64-avx512bitalg.d create mode 100644 gas/testsuite/gas/i386/x86-64-avx512bitalg.s create mode 100644 gas/testsuite/gas/i386/x86-64-avx512bitalg_vl-intel.d create mode 100644 gas/testsuite/gas/i386/x86-64-avx512bitalg_vl.d create mode 100644 gas/testsuite/gas/i386/x86-64-avx512bitalg_vl.s diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c index 1f2efdc..5cde092 100644 --- a/gas/config/tc-i386.c +++ b/gas/config/tc-i386.c @@ -986,6 +986,8 @@ static const arch_entry cpu_arch[] = CPU_AVX512_VBMI2_FLAGS, 0 }, { STRING_COMMA_LEN (".avx512_vnni"), PROCESSOR_UNKNOWN, CPU_AVX512_VNNI_FLAGS, 0 }, + { STRING_COMMA_LEN (".avx512_bitalg"), PROCESSOR_UNKNOWN, + CPU_AVX512_BITALG_FLAGS, 0 }, { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN, CPU_CLZERO_FLAGS, 0 }, { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN, @@ -1036,6 +1038,7 @@ static const noarch_entry cpu_noarch[] = { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS }, { STRING_COMMA_LEN ("noavx512_vbmi2"), CPU_ANY_AVX512_VBMI2_FLAGS }, { STRING_COMMA_LEN ("noavx512_vnni"), CPU_ANY_AVX512_VNNI_FLAGS }, + { STRING_COMMA_LEN ("noavx512_bitalg"), CPU_ANY_AVX512_BITALG_FLAGS }, }; #ifdef I386COFF diff --git a/gas/doc/c-i386.texi b/gas/doc/c-i386.texi index f2e8f4e..a1d33bd 100644 --- a/gas/doc/c-i386.texi +++ b/gas/doc/c-i386.texi @@ -189,6 +189,7 @@ accept various extension mnemonics. For example, @code{avx512_vpopcntdq}, @code{avx512_vbmi2}, @code{avx512_vnni}, +@code{avx512_bitalg}, @code{noavx512f}, @code{noavx512cd}, @code{noavx512er}, @@ -203,6 +204,7 @@ accept various extension mnemonics. For example, @code{noavx512_vpopcntdq}, @code{noavx512_vbmi2}, @code{noavx512_vnni}, +@code{noavx512_bitalg}, @code{vmx}, @code{vmfunc}, @code{smx}, @@ -1226,6 +1228,7 @@ supported on the CPU specified. The choices for @var{cpu_type} are: @item @samp{.avx512vl} @tab @samp{.avx512bw} @tab @samp{.avx512dq} @tab @samp{.avx512ifma} @item @samp{.avx512vbmi} @tab @samp{.avx512_4fmaps} @tab @samp{.avx512_4vnniw} @item @samp{.avx512_vpopcntdq} @tab @samp{.avx512_vbmi2} @tab @samp{.avx512_vnni} +@item @samp{.avx512_bitalg} @item @samp{.clwb} @tab @samp{.rdpid} @tab @samp{.ptwrite} @tab @item @samp{.cet} @item @samp{.3dnow} @tab @samp{.3dnowa} @tab @samp{.sse4a} @tab @samp{.sse5} @item @samp{.syscall} @tab @samp{.rdtscp} @tab @samp{.svme} @tab @samp{.abm} diff --git a/gas/testsuite/gas/i386/avx512bitalg-intel.d b/gas/testsuite/gas/i386/avx512bitalg-intel.d new file mode 100644 index 0000000..0b24bdb --- /dev/null +++ b/gas/testsuite/gas/i386/avx512bitalg-intel.d @@ -0,0 +1,64 @@ +#as: +#objdump: -dw -Mintel +#name: i386 AVX512BITALG insns (Intel disassembly) +#source: avx512bitalg.s + +.*: +file format .* + + +Disassembly of section \.text: + +00000000 <_start>: +[ ]*[a-f0-9]+:[ ]*62 f2 55 48 8f ec[ ]*vpshufbitqmb k5,zmm5,zmm4 +[ ]*[a-f0-9]+:[ ]*62 f2 55 4f 8f ec[ ]*vpshufbitqmb k5\{k7\},zmm5,zmm4 +[ ]*[a-f0-9]+:[ ]*62 f2 55 48 8f ac f4 c0 1d fe ff[ ]*vpshufbitqmb k5,zmm5,ZMMWORD PTR \[esp\+esi\*8-0x1e240\] +[ ]*[a-f0-9]+:[ ]*62 f2 55 48 8f 6a 7f[ ]*vpshufbitqmb k5,zmm5,ZMMWORD PTR \[edx\+0x1fc0\] +[ ]*[a-f0-9]+:[ ]*62 f2 7d 48 54 f5[ ]*vpopcntb zmm6,zmm5 +[ ]*[a-f0-9]+:[ ]*62 f2 7d 4f 54 f5[ ]*vpopcntb zmm6\{k7\},zmm5 +[ ]*[a-f0-9]+:[ ]*62 f2 7d cf 54 f5[ ]*vpopcntb zmm6\{k7\}\{z\},zmm5 +[ ]*[a-f0-9]+:[ ]*62 f2 7d 48 54 b4 f4 c0 1d fe ff[ ]*vpopcntb zmm6,ZMMWORD PTR \[esp\+esi\*8-0x1e240\] +[ ]*[a-f0-9]+:[ ]*62 f2 7d 48 54 72 7f[ ]*vpopcntb zmm6,ZMMWORD PTR \[edx\+0x1fc0\] +[ ]*[a-f0-9]+:[ ]*62 f2 fd 48 54 f5[ ]*vpopcntw zmm6,zmm5 +[ ]*[a-f0-9]+:[ ]*62 f2 fd 4f 54 f5[ ]*vpopcntw zmm6\{k7\},zmm5 +[ ]*[a-f0-9]+:[ ]*62 f2 fd cf 54 f5[ ]*vpopcntw zmm6\{k7\}\{z\},zmm5 +[ ]*[a-f0-9]+:[ ]*62 f2 fd 48 54 b4 f4 c0 1d fe ff[ ]*vpopcntw zmm6,ZMMWORD PTR \[esp\+esi\*8-0x1e240\] +[ ]*[a-f0-9]+:[ ]*62 f2 fd 48 54 72 7f[ ]*vpopcntw zmm6,ZMMWORD PTR \[edx\+0x1fc0\] +[ ]*[a-f0-9]+:[ ]*62 f2 7d 48 55 f5[ ]*vpopcntd zmm6,zmm5 +[ ]*[a-f0-9]+:[ ]*62 f2 7d 4f 55 f5[ ]*vpopcntd zmm6\{k7\},zmm5 +[ ]*[a-f0-9]+:[ ]*62 f2 7d cf 55 f5[ ]*vpopcntd zmm6\{k7\}\{z\},zmm5 +[ ]*[a-f0-9]+:[ ]*62 f2 7d 48 55 b4 f4 c0 1d fe ff[ ]*vpopcntd zmm6,ZMMWORD PTR \[esp\+esi\*8-0x1e240\] +[ ]*[a-f0-9]+:[ ]*62 f2 7d 48 55 72 7f[ ]*vpopcntd zmm6,ZMMWORD PTR \[edx\+0x1fc0\] +[ ]*[a-f0-9]+:[ ]*62 f2 7d 58 55 72 7f[ ]*vpopcntd zmm6,DWORD PTR \[edx\+0x1fc\]\{1to16\} +[ ]*[a-f0-9]+:[ ]*62 f2 fd 48 55 f5[ ]*vpopcntq zmm6,zmm5 +[ ]*[a-f0-9]+:[ ]*62 f2 fd 4f 55 f5[ ]*vpopcntq zmm6\{k7\},zmm5 +[ ]*[a-f0-9]+:[ ]*62 f2 fd cf 55 f5[ ]*vpopcntq zmm6\{k7\}\{z\},zmm5 +[ ]*[a-f0-9]+:[ ]*62 f2 fd 48 55 b4 f4 c0 1d fe ff[ ]*vpopcntq zmm6,ZMMWORD PTR \[esp\+esi\*8-0x1e240\] +[ ]*[a-f0-9]+:[ ]*62 f2 fd 48 55 72 7f[ ]*vpopcntq zmm6,ZMMWORD PTR \[edx\+0x1fc0\] +[ ]*[a-f0-9]+:[ ]*62 f2 fd 58 55 72 7f[ ]*vpopcntq zmm6,QWORD PTR \[edx\+0x3f8\]\{1to8\} +[ ]*[a-f0-9]+:[ ]*62 f2 55 48 8f ec[ ]*vpshufbitqmb k5,zmm5,zmm4 +[ ]*[a-f0-9]+:[ ]*62 f2 55 4f 8f ec[ ]*vpshufbitqmb k5\{k7\},zmm5,zmm4 +[ ]*[a-f0-9]+:[ ]*62 f2 55 48 8f ac f4 c0 1d fe ff[ ]*vpshufbitqmb k5,zmm5,ZMMWORD PTR \[esp\+esi\*8-0x1e240\] +[ ]*[a-f0-9]+:[ ]*62 f2 55 48 8f 6a 7f[ ]*vpshufbitqmb k5,zmm5,ZMMWORD PTR \[edx\+0x1fc0\] +[ ]*[a-f0-9]+:[ ]*62 f2 7d 48 54 f5[ ]*vpopcntb zmm6,zmm5 +[ ]*[a-f0-9]+:[ ]*62 f2 7d 4f 54 f5[ ]*vpopcntb zmm6\{k7\},zmm5 +[ ]*[a-f0-9]+:[ ]*62 f2 7d cf 54 f5[ ]*vpopcntb zmm6\{k7\}\{z\},zmm5 +[ ]*[a-f0-9]+:[ ]*62 f2 7d 48 54 b4 f4 c0 1d fe ff[ ]*vpopcntb zmm6,ZMMWORD PTR \[esp\+esi\*8-0x1e240\] +[ ]*[a-f0-9]+:[ ]*62 f2 7d 48 54 72 7f[ ]*vpopcntb zmm6,ZMMWORD PTR \[edx\+0x1fc0\] +[ ]*[a-f0-9]+:[ ]*62 f2 fd 48 54 f5[ ]*vpopcntw zmm6,zmm5 +[ ]*[a-f0-9]+:[ ]*62 f2 fd 4f 54 f5[ ]*vpopcntw zmm6\{k7\},zmm5 +[ ]*[a-f0-9]+:[ ]*62 f2 fd cf 54 f5[ ]*vpopcntw zmm6\{k7\}\{z\},zmm5 +[ ]*[a-f0-9]+:[ ]*62 f2 fd 48 54 b4 f4 c0 1d fe ff[ ]*vpopcntw zmm6,ZMMWORD PTR \[esp\+esi\*8-0x1e240\] +[ ]*[a-f0-9]+:[ ]*62 f2 fd 48 54 72 7f[ ]*vpopcntw zmm6,ZMMWORD PTR \[edx\+0x1fc0\] +[ ]*[a-f0-9]+:[ ]*62 f2 7d 48 55 f5[ ]*vpopcntd zmm6,zmm5 +[ ]*[a-f0-9]+:[ ]*62 f2 7d 4f 55 f5[ ]*vpopcntd zmm6\{k7\},zmm5 +[ ]*[a-f0-9]+:[ ]*62 f2 7d cf 55 f5[ ]*vpopcntd zmm6\{k7\}\{z\},zmm5 +[ ]*[a-f0-9]+:[ ]*62 f2 7d 48 55 b4 f4 c0 1d fe ff[ ]*vpopcntd zmm6,ZMMWORD PTR \[esp\+esi\*8-0x1e240\] +[ ]*[a-f0-9]+:[ ]*62 f2 7d 48 55 72 7f[ ]*vpopcntd zmm6,ZMMWORD PTR \[edx\+0x1fc0\] +[ ]*[a-f0-9]+:[ ]*62 f2 7d 58 55 72 7f[ ]*vpopcntd zmm6,DWORD PTR \[edx\+0x1fc\]\{1to16\} +[ ]*[a-f0-9]+:[ ]*62 f2 fd 48 55 f5[ ]*vpopcntq zmm6,zmm5 +[ ]*[a-f0-9]+:[ ]*62 f2 fd 4f 55 f5[ ]*vpopcntq zmm6\{k7\},zmm5 +[ ]*[a-f0-9]+:[ ]*62 f2 fd cf 55 f5[ ]*vpopcntq zmm6\{k7\}\{z\},zmm5 +[ ]*[a-f0-9]+:[ ]*62 f2 fd 48 55 b4 f4 c0 1d fe ff[ ]*vpopcntq zmm6,ZMMWORD PTR \[esp\+esi\*8-0x1e240\] +[ ]*[a-f0-9]+:[ ]*62 f2 fd 48 55 72 7f[ ]*vpopcntq zmm6,ZMMWORD PTR \[edx\+0x1fc0\] +[ ]*[a-f0-9]+:[ ]*62 f2 fd 58 55 72 7f[ ]*vpopcntq zmm6,QWORD PTR \[edx\+0x3f8\]\{1to8\} +#pass diff --git a/gas/testsuite/gas/i386/avx512bitalg.d b/gas/testsuite/gas/i386/avx512bitalg.d new file mode 100644 index 0000000..0c053af --- /dev/null +++ b/gas/testsuite/gas/i386/avx512bitalg.d @@ -0,0 +1,64 @@ +#as: +#objdump: -dw +#name: i386 AVX512BITALG insns +#source: avx512bitalg.s + +.*: +file format .* + + +Disassembly of section \.text: + +00000000 <_start>: +[ ]*[a-f0-9]+:[ ]*62 f2 55 48 8f ec[ ]*vpshufbitqmb %zmm4,%zmm5,%k5 +[ ]*[a-f0-9]+:[ ]*62 f2 55 4f 8f ec[ ]*vpshufbitqmb %zmm4,%zmm5,%k5\{%k7\} +[ ]*[a-f0-9]+:[ ]*62 f2 55 48 8f ac f4 c0 1d fe ff[ ]*vpshufbitqmb -0x1e240\(%esp,%esi,8\),%zmm5,%k5 +[ ]*[a-f0-9]+:[ ]*62 f2 55 48 8f 6a 7f[ ]*vpshufbitqmb 0x1fc0\(%edx\),%zmm5,%k5 +[ ]*[a-f0-9]+:[ ]*62 f2 7d 48 54 f5[ ]*vpopcntb %zmm5,%zmm6 +[ ]*[a-f0-9]+:[ ]*62 f2 7d 4f 54 f5[ ]*vpopcntb %zmm5,%zmm6\{%k7\} +[ ]*[a-f0-9]+:[ ]*62 f2 7d cf 54 f5[ ]*vpopcntb %zmm5,%zmm6\{%k7\}\{z\} +[ ]*[a-f0-9]+:[ ]*62 f2 7d 48 54 b4 f4 c0 1d fe ff[ ]*vpopcntb -0x1e240\(%esp,%esi,8\),%zmm6 +[ ]*[a-f0-9]+:[ ]*62 f2 7d 48 54 72 7f[ ]*vpopcntb 0x1fc0\(%edx\),%zmm6 +[ ]*[a-f0-9]+:[ ]*62 f2 fd 48 54 f5[ ]*vpopcntw %zmm5,%zmm6 +[ ]*[a-f0-9]+:[ ]*62 f2 fd 4f 54 f5[ ]*vpopcntw %zmm5,%zmm6\{%k7\} +[ ]*[a-f0-9]+:[ ]*62 f2 fd cf 54 f5[ ]*vpopcntw %zmm5,%zmm6\{%k7\}\{z\} +[ ]*[a-f0-9]+:[ ]*62 f2 fd 48 54 b4 f4 c0 1d fe ff[ ]*vpopcntw -0x1e240\(%esp,%esi,8\),%zmm6 +[ ]*[a-f0-9]+:[ ]*62 f2 fd 48 54 72 7f[ ]*vpopcntw 0x1fc0\(%edx\),%zmm6 +[ ]*[a-f0-9]+:[ ]*62 f2 7d 48 55 f5[ ]*vpopcntd %zmm5,%zmm6 +[ ]*[a-f0-9]+:[ ]*62 f2 7d 4f 55 f5[ ]*vpopcntd %zmm5,%zmm6\{%k7\} +[ ]*[a-f0-9]+:[ ]*62 f2 7d cf 55 f5[ ]*vpopcntd %zmm5,%zmm6\{%k7\}\{z\} +[ ]*[a-f0-9]+:[ ]*62 f2 7d 48 55 b4 f4 c0 1d fe ff[ ]*vpopcntd -0x1e240\(%esp,%esi,8\),%zmm6 +[ ]*[a-f0-9]+:[ ]*62 f2 7d 48 55 72 7f[ ]*vpopcntd 0x1fc0\(%edx\),%zmm6 +[ ]*[a-f0-9]+:[ ]*62 f2 7d 58 55 72 7f[ ]*vpopcntd 0x1fc\(%edx\)\{1to16\},%zmm6 +[ ]*[a-f0-9]+:[ ]*62 f2 fd 48 55 f5[ ]*vpopcntq %zmm5,%zmm6 +[ ]*[a-f0-9]+:[ ]*62 f2 fd 4f 55 f5[ ]*vpopcntq %zmm5,%zmm6\{%k7\} +[ ]*[a-f0-9]+:[ ]*62 f2 fd cf 55 f5[ ]*vpopcntq %zmm5,%zmm6\{%k7\}\{z\} +[ ]*[a-f0-9]+:[ ]*62 f2 fd 48 55 b4 f4 c0 1d fe ff[ ]*vpopcntq -0x1e240\(%esp,%esi,8\),%zmm6 +[ ]*[a-f0-9]+:[ ]*62 f2 fd 48 55 72 7f[ ]*vpopcntq 0x1fc0\(%edx\),%zmm6 +[ ]*[a-f0-9]+:[ ]*62 f2 fd 58 55 72 7f[ ]*vpopcntq 0x3f8\(%edx\)\{1to8\},%zmm6 +[ ]*[a-f0-9]+:[ ]*62 f2 55 48 8f ec[ ]*vpshufbitqmb %zmm4,%zmm5,%k5 +[ ]*[a-f0-9]+:[ ]*62 f2 55 4f 8f ec[ ]*vpshufbitqmb %zmm4,%zmm5,%k5\{%k7\} +[ ]*[a-f0-9]+:[ ]*62 f2 55 48 8f ac f4 c0 1d fe ff[ ]*vpshufbitqmb -0x1e240\(%esp,%esi,8\),%zmm5,%k5 +[ ]*[a-f0-9]+:[ ]*62 f2 55 48 8f 6a 7f[ ]*vpshufbitqmb 0x1fc0\(%edx\),%zmm5,%k5 +[ ]*[a-f0-9]+:[ ]*62 f2 7d 48 54 f5[ ]*vpopcntb %zmm5,%zmm6 +[ ]*[a-f0-9]+:[ ]*62 f2 7d 4f 54 f5[ ]*vpopcntb %zmm5,%zmm6\{%k7\} +[ ]*[a-f0-9]+:[ ]*62 f2 7d cf 54 f5[ ]*vpopcntb %zmm5,%zmm6\{%k7\}\{z\} +[ ]*[a-f0-9]+:[ ]*62 f2 7d 48 54 b4 f4 c0 1d fe ff[ ]*vpopcntb -0x1e240\(%esp,%esi,8\),%zmm6 +[ ]*[a-f0-9]+:[ ]*62 f2 7d 48 54 72 7f[ ]*vpopcntb 0x1fc0\(%edx\),%zmm6 +[ ]*[a-f0-9]+:[ ]*62 f2 fd 48 54 f5[ ]*vpopcntw %zmm5,%zmm6 +[ ]*[a-f0-9]+:[ ]*62 f2 fd 4f 54 f5[ ]*vpopcntw %zmm5,%zmm6\{%k7\} +[ ]*[a-f0-9]+:[ ]*62 f2 fd cf 54 f5[ ]*vpopcntw %zmm5,%zmm6\{%k7\}\{z\} +[ ]*[a-f0-9]+:[ ]*62 f2 fd 48 54 b4 f4 c0 1d fe ff[ ]*vpopcntw -0x1e240\(%esp,%esi,8\),%zmm6 +[ ]*[a-f0-9]+:[ ]*62 f2 fd 48 54 72 7f[ ]*vpopcntw 0x1fc0\(%edx\),%zmm6 +[ ]*[a-f0-9]+:[ ]*62 f2 7d 48 55 f5[ ]*vpopcntd %zmm5,%zmm6 +[ ]*[a-f0-9]+:[ ]*62 f2 7d 4f 55 f5[ ]*vpopcntd %zmm5,%zmm6\{%k7\} +[ ]*[a-f0-9]+:[ ]*62 f2 7d cf 55 f5[ ]*vpopcntd %zmm5,%zmm6\{%k7\}\{z\} +[ ]*[a-f0-9]+:[ ]*62 f2 7d 48 55 b4 f4 c0 1d fe ff[ ]*vpopcntd -0x1e240\(%esp,%esi,8\),%zmm6 +[ ]*[a-f0-9]+:[ ]*62 f2 7d 48 55 72 7f[ ]*vpopcntd 0x1fc0\(%edx\),%zmm6 +[ ]*[a-f0-9]+:[ ]*62 f2 7d 58 55 72 7f[ ]*vpopcntd 0x1fc\(%edx\)\{1to16\},%zmm6 +[ ]*[a-f0-9]+:[ ]*62 f2 fd 48 55 f5[ ]*vpopcntq %zmm5,%zmm6 +[ ]*[a-f0-9]+:[ ]*62 f2 fd 4f 55 f5[ ]*vpopcntq %zmm5,%zmm6\{%k7\} +[ ]*[a-f0-9]+:[ ]*62 f2 fd cf 55 f5[ ]*vpopcntq %zmm5,%zmm6\{%k7\}\{z\} +[ ]*[a-f0-9]+:[ ]*62 f2 fd 48 55 b4 f4 c0 1d fe ff[ ]*vpopcntq -0x1e240\(%esp,%esi,8\),%zmm6 +[ ]*[a-f0-9]+:[ ]*62 f2 fd 48 55 72 7f[ ]*vpopcntq 0x1fc0\(%edx\),%zmm6 +[ ]*[a-f0-9]+:[ ]*62 f2 fd 58 55 72 7f[ ]*vpopcntq 0x3f8\(%edx\)\{1to8\},%zmm6 +#pass diff --git a/gas/testsuite/gas/i386/avx512bitalg.s b/gas/testsuite/gas/i386/avx512bitalg.s new file mode 100644 index 0000000..6d2b16e --- /dev/null +++ b/gas/testsuite/gas/i386/avx512bitalg.s @@ -0,0 +1,67 @@ +# Check 32bit AVX512BITALG instructions + + .allow_index_reg + .text +_start: + vpshufbitqmb %zmm4, %zmm5, %k5 # AVX512BITALG + vpshufbitqmb %zmm4, %zmm5, %k5{%k7} # AVX512BITALG + vpshufbitqmb -123456(%esp,%esi,8), %zmm5, %k5 # AVX512BITALG + vpshufbitqmb 8128(%edx), %zmm5, %k5 # AVX512BITALG Disp8 + + vpopcntb %zmm5, %zmm6 # AVX512BITALG + vpopcntb %zmm5, %zmm6{%k7} # AVX512BITALG + vpopcntb %zmm5, %zmm6{%k7}{z} # AVX512BITALG + vpopcntb -123456(%esp,%esi,8), %zmm6 # AVX512BITALG + vpopcntb 8128(%edx), %zmm6 # AVX512BITALG Disp8 + + vpopcntw %zmm5, %zmm6 # AVX512BITALG + vpopcntw %zmm5, %zmm6{%k7} # AVX512BITALG + vpopcntw %zmm5, %zmm6{%k7}{z} # AVX512BITALG + vpopcntw -123456(%esp,%esi,8), %zmm6 # AVX512BITALG + vpopcntw 8128(%edx), %zmm6 # AVX512BITALG Disp8 + vpopcntd %zmm5, %zmm6 # AVX512BITALG + + vpopcntd %zmm5, %zmm6{%k7} # AVX512BITALG + vpopcntd %zmm5, %zmm6{%k7}{z} # AVX512BITALG + vpopcntd -123456(%esp,%esi,8), %zmm6 # AVX512BITALG + vpopcntd 8128(%edx), %zmm6 # AVX512BITALG Disp8 + vpopcntd 508(%edx){1to16}, %zmm6 # AVX512BITALG Disp8 + vpopcntq %zmm5, %zmm6 # AVX512BITALG + + vpopcntq %zmm5, %zmm6{%k7} # AVX512BITALG + vpopcntq %zmm5, %zmm6{%k7}{z} # AVX512BITALG + vpopcntq -123456(%esp,%esi,8), %zmm6 # AVX512BITALG + vpopcntq 8128(%edx), %zmm6 # AVX512BITALG Disp8 + vpopcntq 1016(%edx){1to8}, %zmm6 # AVX512BITALG Disp8 + + .intel_syntax noprefix + vpshufbitqmb k5, zmm5, zmm4 # AVX512BITALG + vpshufbitqmb k5{k7}, zmm5, zmm4 # AVX512BITALG + vpshufbitqmb k5, zmm5, ZMMWORD PTR [esp+esi*8-123456] # AVX512BITALG + vpshufbitqmb k5, zmm5, ZMMWORD PTR [edx+8128] # AVX512BITALG Disp8 + vpopcntb zmm6, zmm5 # AVX512BITALG + + vpopcntb zmm6{k7}, zmm5 # AVX512BITALG + vpopcntb zmm6{k7}{z}, zmm5 # AVX512BITALG + vpopcntb zmm6, ZMMWORD PTR [esp+esi*8-123456] # AVX512BITALG + vpopcntb zmm6, ZMMWORD PTR [edx+8128] # AVX512BITALG Disp8 + vpopcntw zmm6, zmm5 # AVX512BITALG + + vpopcntw zmm6{k7}, zmm5 # AVX512BITALG + vpopcntw zmm6{k7}{z}, zmm5 # AVX512BITALG + vpopcntw zmm6, ZMMWORD PTR [esp+esi*8-123456] # AVX512BITALG + vpopcntw zmm6, ZMMWORD PTR [edx+8128] # AVX512BITALG Disp8 + vpopcntd zmm6, zmm5 # AVX512BITALG + + vpopcntd zmm6{k7}, zmm5 # AVX512BITALG + vpopcntd zmm6{k7}{z}, zmm5 # AVX512BITALG + vpopcntd zmm6, ZMMWORD PTR [esp+esi*8-123456] # AVX512BITALG + vpopcntd zmm6, ZMMWORD PTR [edx+8128] # AVX512BITALG Disp8 + vpopcntd zmm6, [edx+508]{1to16} # AVX512BITALG Disp8 + vpopcntq zmm6, zmm5 # AVX512BITALG + + vpopcntq zmm6{k7}, zmm5 # AVX512BITALG + vpopcntq zmm6{k7}{z}, zmm5 # AVX512BITALG + vpopcntq zmm6, ZMMWORD PTR [esp+esi*8-123456] # AVX512BITALG + vpopcntq zmm6, ZMMWORD PTR [edx+8128] # AVX512BITALG Disp8 + vpopcntq zmm6, [edx+1016]{1to8} # AVX512BITALG Disp8 diff --git a/gas/testsuite/gas/i386/avx512bitalg_vl-intel.d b/gas/testsuite/gas/i386/avx512bitalg_vl-intel.d new file mode 100644 index 0000000..d3834bd --- /dev/null +++ b/gas/testsuite/gas/i386/avx512bitalg_vl-intel.d @@ -0,0 +1,96 @@ +#as: +#objdump: -dw -Mintel +#name: i386 AVX512BITALG/VL insns (Intel disassembly) +#source: avx512bitalg_vl.s + +.*: +file format .* + + +Disassembly of section \.text: + +00000000 <_start>: +[ ]*[a-f0-9]+:[ ]*62 f2 55 0f 8f ec[ ]*vpshufbitqmb k5\{k7\},xmm5,xmm4 +[ ]*[a-f0-9]+:[ ]*62 f2 55 0f 8f ac f4 c0 1d fe ff[ ]*vpshufbitqmb k5\{k7\},xmm5,XMMWORD PTR \[esp\+esi\*8-0x1e240\] +[ ]*[a-f0-9]+:[ ]*62 f2 55 0f 8f 6a 7f[ ]*vpshufbitqmb k5\{k7\},xmm5,XMMWORD PTR \[edx\+0x7f0\] +[ ]*[a-f0-9]+:[ ]*62 f2 55 2f 8f ec[ ]*vpshufbitqmb k5\{k7\},ymm5,ymm4 +[ ]*[a-f0-9]+:[ ]*62 f2 55 2f 8f ac f4 c0 1d fe ff[ ]*vpshufbitqmb k5\{k7\},ymm5,YMMWORD PTR \[esp\+esi\*8-0x1e240\] +[ ]*[a-f0-9]+:[ ]*62 f2 55 2f 8f 6a 7f[ ]*vpshufbitqmb k5\{k7\},ymm5,YMMWORD PTR \[edx\+0xfe0\] +[ ]*[a-f0-9]+:[ ]*62 f2 7d 0f 54 f5[ ]*vpopcntb xmm6\{k7\},xmm5 +[ ]*[a-f0-9]+:[ ]*62 f2 7d 8f 54 f5[ ]*vpopcntb xmm6\{k7\}\{z\},xmm5 +[ ]*[a-f0-9]+:[ ]*62 f2 7d 0f 54 b4 f4 c0 1d fe ff[ ]*vpopcntb xmm6\{k7\},XMMWORD PTR \[esp\+esi\*8-0x1e240\] +[ ]*[a-f0-9]+:[ ]*62 f2 7d 0f 54 72 7f[ ]*vpopcntb xmm6\{k7\},XMMWORD PTR \[edx\+0x7f0\] +[ ]*[a-f0-9]+:[ ]*62 f2 7d 2f 54 f5[ ]*vpopcntb ymm6\{k7\},ymm5 +[ ]*[a-f0-9]+:[ ]*62 f2 7d af 54 f5[ ]*vpopcntb ymm6\{k7\}\{z\},ymm5 +[ ]*[a-f0-9]+:[ ]*62 f2 7d 2f 54 b4 f4 c0 1d fe ff[ ]*vpopcntb ymm6\{k7\},YMMWORD PTR \[esp\+esi\*8-0x1e240\] +[ ]*[a-f0-9]+:[ ]*62 f2 7d 2f 54 72 7f[ ]*vpopcntb ymm6\{k7\},YMMWORD PTR \[edx\+0xfe0\] +[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 54 f5[ ]*vpopcntw xmm6\{k7\},xmm5 +[ ]*[a-f0-9]+:[ ]*62 f2 fd 8f 54 f5[ ]*vpopcntw xmm6\{k7\}\{z\},xmm5 +[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 54 b4 f4 c0 1d fe ff[ ]*vpopcntw xmm6\{k7\},XMMWORD PTR \[esp\+esi\*8-0x1e240\] +[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 54 72 7f[ ]*vpopcntw xmm6\{k7\},XMMWORD PTR \[edx\+0x7f0\] +[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 54 f5[ ]*vpopcntw ymm6\{k7\},ymm5 +[ ]*[a-f0-9]+:[ ]*62 f2 fd af 54 f5[ ]*vpopcntw ymm6\{k7\}\{z\},ymm5 +[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 54 b4 f4 c0 1d fe ff[ ]*vpopcntw ymm6\{k7\},YMMWORD PTR \[esp\+esi\*8-0x1e240\] +[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 54 72 7f[ ]*vpopcntw ymm6\{k7\},YMMWORD PTR \[edx\+0xfe0\] +[ ]*[a-f0-9]+:[ ]*62 f2 7d 0f 55 f5[ ]*vpopcntd xmm6\{k7\},xmm5 +[ ]*[a-f0-9]+:[ ]*62 f2 7d 8f 55 f5[ ]*vpopcntd xmm6\{k7\}\{z\},xmm5 +[ ]*[a-f0-9]+:[ ]*62 f2 7d 0f 55 b4 f4 c0 1d fe ff[ ]*vpopcntd xmm6\{k7\},XMMWORD PTR \[esp\+esi\*8-0x1e240\] +[ ]*[a-f0-9]+:[ ]*62 f2 7d 0f 55 72 7f[ ]*vpopcntd xmm6\{k7\},XMMWORD PTR \[edx\+0x7f0\] +[ ]*[a-f0-9]+:[ ]*62 f2 7d 1f 55 72 7f[ ]*vpopcntd xmm6\{k7\},DWORD PTR \[edx\+0x1fc\]\{1to4\} +[ ]*[a-f0-9]+:[ ]*62 f2 7d 2f 55 f5[ ]*vpopcntd ymm6\{k7\},ymm5 +[ ]*[a-f0-9]+:[ ]*62 f2 7d af 55 f5[ ]*vpopcntd ymm6\{k7\}\{z\},ymm5 +[ ]*[a-f0-9]+:[ ]*62 f2 7d 2f 55 b4 f4 c0 1d fe ff[ ]*vpopcntd ymm6\{k7\},YMMWORD PTR \[esp\+esi\*8-0x1e240\] +[ ]*[a-f0-9]+:[ ]*62 f2 7d 2f 55 72 7f[ ]*vpopcntd ymm6\{k7\},YMMWORD PTR \[edx\+0xfe0\] +[ ]*[a-f0-9]+:[ ]*62 f2 7d 3f 55 72 7f[ ]*vpopcntd ymm6\{k7\},DWORD PTR \[edx\+0x1fc\]\{1to8\} +[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 55 f5[ ]*vpopcntq xmm6\{k7\},xmm5 +[ ]*[a-f0-9]+:[ ]*62 f2 fd 8f 55 f5[ ]*vpopcntq xmm6\{k7\}\{z\},xmm5 +[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 55 b4 f4 c0 1d fe ff[ ]*vpopcntq xmm6\{k7\},XMMWORD PTR \[esp\+esi\*8-0x1e240\] +[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 55 72 7f[ ]*vpopcntq xmm6\{k7\},XMMWORD PTR \[edx\+0x7f0\] +[ ]*[a-f0-9]+:[ ]*62 f2 fd 1f 55 72 7f[ ]*vpopcntq xmm6\{k7\},QWORD PTR \[edx\+0x3f8\]\{1to2\} +[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 55 f5[ ]*vpopcntq ymm6\{k7\},ymm5 +[ ]*[a-f0-9]+:[ ]*62 f2 fd af 55 f5[ ]*vpopcntq ymm6\{k7\}\{z\},ymm5 +[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 55 b4 f4 c0 1d fe ff[ ]*vpopcntq ymm6\{k7\},YMMWORD PTR \[esp\+esi\*8-0x1e240\] +[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 55 72 7f[ ]*vpopcntq ymm6\{k7\},YMMWORD PTR \[edx\+0xfe0\] +[ ]*[a-f0-9]+:[ ]*62 f2 fd 3f 55 72 7f[ ]*vpopcntq ymm6\{k7\},QWORD PTR \[edx\+0x3f8\]\{1to4\} +[ ]*[a-f0-9]+:[ ]*62 f2 55 0f 8f ec[ ]*vpshufbitqmb k5\{k7\},xmm5,xmm4 +[ ]*[a-f0-9]+:[ ]*62 f2 55 0f 8f ac f4 c0 1d fe ff[ ]*vpshufbitqmb k5\{k7\},xmm5,XMMWORD PTR \[esp\+esi\*8-0x1e240\] +[ ]*[a-f0-9]+:[ ]*62 f2 55 0f 8f 6a 7f[ ]*vpshufbitqmb k5\{k7\},xmm5,XMMWORD PTR \[edx\+0x7f0\] +[ ]*[a-f0-9]+:[ ]*62 f2 55 2f 8f ec[ ]*vpshufbitqmb k5\{k7\},ymm5,ymm4 +[ ]*[a-f0-9]+:[ ]*62 f2 55 2f 8f ac f4 c0 1d fe ff[ ]*vpshufbitqmb k5\{k7\},ymm5,YMMWORD PTR \[esp\+esi\*8-0x1e240\] +[ ]*[a-f0-9]+:[ ]*62 f2 55 2f 8f 6a 7f[ ]*vpshufbitqmb k5\{k7\},ymm5,YMMWORD PTR \[edx\+0xfe0\] +[ ]*[a-f0-9]+:[ ]*62 f2 7d 0f 54 f5[ ]*vpopcntb xmm6\{k7\},xmm5 +[ ]*[a-f0-9]+:[ ]*62 f2 7d 8f 54 f5[ ]*vpopcntb xmm6\{k7\}\{z\},xmm5 +[ ]*[a-f0-9]+:[ ]*62 f2 7d 0f 54 b4 f4 c0 1d fe ff[ ]*vpopcntb xmm6\{k7\},XMMWORD PTR \[esp\+esi\*8-0x1e240\] +[ ]*[a-f0-9]+:[ ]*62 f2 7d 0f 54 72 7f[ ]*vpopcntb xmm6\{k7\},XMMWORD PTR \[edx\+0x7f0\] +[ ]*[a-f0-9]+:[ ]*62 f2 7d 2f 54 f5[ ]*vpopcntb ymm6\{k7\},ymm5 +[ ]*[a-f0-9]+:[ ]*62 f2 7d af 54 f5[ ]*vpopcntb ymm6\{k7\}\{z\},ymm5 +[ ]*[a-f0-9]+:[ ]*62 f2 7d 2f 54 b4 f4 c0 1d fe ff[ ]*vpopcntb ymm6\{k7\},YMMWORD PTR \[esp\+esi\*8-0x1e240\] +[ ]*[a-f0-9]+:[ ]*62 f2 7d 2f 54 72 7f[ ]*vpopcntb ymm6\{k7\},YMMWORD PTR \[edx\+0xfe0\] +[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 54 f5[ ]*vpopcntw xmm6\{k7\},xmm5 +[ ]*[a-f0-9]+:[ ]*62 f2 fd 8f 54 f5[ ]*vpopcntw xmm6\{k7\}\{z\},xmm5 +[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 54 b4 f4 c0 1d fe ff[ ]*vpopcntw xmm6\{k7\},XMMWORD PTR \[esp\+esi\*8-0x1e240\] +[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 54 72 7f[ ]*vpopcntw xmm6\{k7\},XMMWORD PTR \[edx\+0x7f0\] +[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 54 f5[ ]*vpopcntw ymm6\{k7\},ymm5 +[ ]*[a-f0-9]+:[ ]*62 f2 fd af 54 f5[ ]*vpopcntw ymm6\{k7\}\{z\},ymm5 +[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 54 b4 f4 c0 1d fe ff[ ]*vpopcntw ymm6\{k7\},YMMWORD PTR \[esp\+esi\*8-0x1e240\] +[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 54 72 7f[ ]*vpopcntw ymm6\{k7\},YMMWORD PTR \[edx\+0xfe0\] +[ ]*[a-f0-9]+:[ ]*62 f2 7d 0f 55 f5[ ]*vpopcntd xmm6\{k7\},xmm5 +[ ]*[a-f0-9]+:[ ]*62 f2 7d 8f 55 f5[ ]*vpopcntd xmm6\{k7\}\{z\},xmm5 +[ ]*[a-f0-9]+:[ ]*62 f2 7d 0f 55 b4 f4 c0 1d fe ff[ ]*vpopcntd xmm6\{k7\},XMMWORD PTR \[esp\+esi\*8-0x1e240\] +[ ]*[a-f0-9]+:[ ]*62 f2 7d 0f 55 72 7f[ ]*vpopcntd xmm6\{k7\},XMMWORD PTR \[edx\+0x7f0\] +[ ]*[a-f0-9]+:[ ]*62 f2 7d 1f 55 72 7f[ ]*vpopcntd xmm6\{k7\},DWORD PTR \[edx\+0x1fc\]\{1to4\} +[ ]*[a-f0-9]+:[ ]*62 f2 7d 2f 55 f5[ ]*vpopcntd ymm6\{k7\},ymm5 +[ ]*[a-f0-9]+:[ ]*62 f2 7d af 55 f5[ ]*vpopcntd ymm6\{k7\}\{z\},ymm5 +[ ]*[a-f0-9]+:[ ]*62 f2 7d 2f 55 b4 f4 c0 1d fe ff[ ]*vpopcntd ymm6\{k7\},YMMWORD PTR \[esp\+esi\*8-0x1e240\] +[ ]*[a-f0-9]+:[ ]*62 f2 7d 2f 55 72 7f[ ]*vpopcntd ymm6\{k7\},YMMWORD PTR \[edx\+0xfe0\] +[ ]*[a-f0-9]+:[ ]*62 f2 7d 3f 55 72 7f[ ]*vpopcntd ymm6\{k7\},DWORD PTR \[edx\+0x1fc\]\{1to8\} +[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 55 f5[ ]*vpopcntq xmm6\{k7\},xmm5 +[ ]*[a-f0-9]+:[ ]*62 f2 fd 8f 55 f5[ ]*vpopcntq xmm6\{k7\}\{z\},xmm5 +[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 55 b4 f4 c0 1d fe ff[ ]*vpopcntq xmm6\{k7\},XMMWORD PTR \[esp\+esi\*8-0x1e240\] +[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 55 72 7f[ ]*vpopcntq xmm6\{k7\},XMMWORD PTR \[edx\+0x7f0\] +[ ]*[a-f0-9]+:[ ]*62 f2 fd 1f 55 72 7f[ ]*vpopcntq xmm6\{k7\},QWORD PTR \[edx\+0x3f8\]\{1to2\} +[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 55 f5[ ]*vpopcntq ymm6\{k7\},ymm5 +[ ]*[a-f0-9]+:[ ]*62 f2 fd af 55 f5[ ]*vpopcntq ymm6\{k7\}\{z\},ymm5 +[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 55 b4 f4 c0 1d fe ff[ ]*vpopcntq ymm6\{k7\},YMMWORD PTR \[esp\+esi\*8-0x1e240\] +[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 55 72 7f[ ]*vpopcntq ymm6\{k7\},YMMWORD PTR \[edx\+0xfe0\] +[ ]*[a-f0-9]+:[ ]*62 f2 fd 3f 55 72 7f[ ]*vpopcntq ymm6\{k7\},QWORD PTR \[edx\+0x3f8\]\{1to4\} +#pass diff --git a/gas/testsuite/gas/i386/avx512bitalg_vl.d b/gas/testsuite/gas/i386/avx512bitalg_vl.d new file mode 100644 index 0000000..1f9e773 --- /dev/null +++ b/gas/testsuite/gas/i386/avx512bitalg_vl.d @@ -0,0 +1,96 @@ +#as: +#objdump: -dw +#name: i386 AVX512BITALG/VL insns +#source: avx512bitalg_vl.s + +.*: +file format .* + + +Disassembly of section \.text: + +00000000 <_start>: +[ ]*[a-f0-9]+:[ ]*62 f2 55 0f 8f ec[ ]*vpshufbitqmb %xmm4,%xmm5,%k5\{%k7\} +[ ]*[a-f0-9]+:[ ]*62 f2 55 0f 8f ac f4 c0 1d fe ff[ ]*vpshufbitqmb -0x1e240\(%esp,%esi,8\),%xmm5,%k5\{%k7\} +[ ]*[a-f0-9]+:[ ]*62 f2 55 0f 8f 6a 7f[ ]*vpshufbitqmb 0x7f0\(%edx\),%xmm5,%k5\{%k7\} +[ ]*[a-f0-9]+:[ ]*62 f2 55 2f 8f ec[ ]*vpshufbitqmb %ymm4,%ymm5,%k5\{%k7\} +[ ]*[a-f0-9]+:[ ]*62 f2 55 2f 8f ac f4 c0 1d fe ff[ ]*vpshufbitqmb -0x1e240\(%esp,%esi,8\),%ymm5,%k5\{%k7\} +[ ]*[a-f0-9]+:[ ]*62 f2 55 2f 8f 6a 7f[ ]*vpshufbitqmb 0xfe0\(%edx\),%ymm5,%k5\{%k7\} +[ ]*[a-f0-9]+:[ ]*62 f2 7d 0f 54 f5[ ]*vpopcntb %xmm5,%xmm6\{%k7\} +[ ]*[a-f0-9]+:[ ]*62 f2 7d 8f 54 f5[ ]*vpopcntb %xmm5,%xmm6\{%k7\}\{z\} +[ ]*[a-f0-9]+:[ ]*62 f2 7d 0f 54 b4 f4 c0 1d fe ff[ ]*vpopcntb -0x1e240\(%esp,%esi,8\),%xmm6\{%k7\} +[ ]*[a-f0-9]+:[ ]*62 f2 7d 0f 54 72 7f[ ]*vpopcntb 0x7f0\(%edx\),%xmm6\{%k7\} +[ ]*[a-f0-9]+:[ ]*62 f2 7d 2f 54 f5[ ]*vpopcntb %ymm5,%ymm6\{%k7\} +[ ]*[a-f0-9]+:[ ]*62 f2 7d af 54 f5[ ]*vpopcntb %ymm5,%ymm6\{%k7\}\{z\} +[ ]*[a-f0-9]+:[ ]*62 f2 7d 2f 54 b4 f4 c0 1d fe ff[ ]*vpopcntb -0x1e240\(%esp,%esi,8\),%ymm6\{%k7\} +[ ]*[a-f0-9]+:[ ]*62 f2 7d 2f 54 72 7f[ ]*vpopcntb 0xfe0\(%edx\),%ymm6\{%k7\} +[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 54 f5[ ]*vpopcntw %xmm5,%xmm6\{%k7\} +[ ]*[a-f0-9]+:[ ]*62 f2 fd 8f 54 f5[ ]*vpopcntw %xmm5,%xmm6\{%k7\}\{z\} +[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 54 b4 f4 c0 1d fe ff[ ]*vpopcntw -0x1e240\(%esp,%esi,8\),%xmm6\{%k7\} +[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 54 72 7f[ ]*vpopcntw 0x7f0\(%edx\),%xmm6\{%k7\} +[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 54 f5[ ]*vpopcntw %ymm5,%ymm6\{%k7\} +[ ]*[a-f0-9]+:[ ]*62 f2 fd af 54 f5[ ]*vpopcntw %ymm5,%ymm6\{%k7\}\{z\} +[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 54 b4 f4 c0 1d fe ff[ ]*vpopcntw -0x1e240\(%esp,%esi,8\),%ymm6\{%k7\} +[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 54 72 7f[ ]*vpopcntw 0xfe0\(%edx\),%ymm6\{%k7\} +[ ]*[a-f0-9]+:[ ]*62 f2 7d 0f 55 f5[ ]*vpopcntd %xmm5,%xmm6\{%k7\} +[ ]*[a-f0-9]+:[ ]*62 f2 7d 8f 55 f5[ ]*vpopcntd %xmm5,%xmm6\{%k7\}\{z\} +[ ]*[a-f0-9]+:[ ]*62 f2 7d 0f 55 b4 f4 c0 1d fe ff[ ]*vpopcntd -0x1e240\(%esp,%esi,8\),%xmm6\{%k7\} +[ ]*[a-f0-9]+:[ ]*62 f2 7d 0f 55 72 7f[ ]*vpopcntd 0x7f0\(%edx\),%xmm6\{%k7\} +[ ]*[a-f0-9]+:[ ]*62 f2 7d 1f 55 72 7f[ ]*vpopcntd 0x1fc\(%edx\)\{1to4\},%xmm6\{%k7\} +[ ]*[a-f0-9]+:[ ]*62 f2 7d 2f 55 f5[ ]*vpopcntd %ymm5,%ymm6\{%k7\} +[ ]*[a-f0-9]+:[ ]*62 f2 7d af 55 f5[ ]*vpopcntd %ymm5,%ymm6\{%k7\}\{z\} +[ ]*[a-f0-9]+:[ ]*62 f2 7d 2f 55 b4 f4 c0 1d fe ff[ ]*vpopcntd -0x1e240\(%esp,%esi,8\),%ymm6\{%k7\} +[ ]*[a-f0-9]+:[ ]*62 f2 7d 2f 55 72 7f[ ]*vpopcntd 0xfe0\(%edx\),%ymm6\{%k7\} +[ ]*[a-f0-9]+:[ ]*62 f2 7d 3f 55 72 7f[ ]*vpopcntd 0x1fc\(%edx\)\{1to8\},%ymm6\{%k7\} +[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 55 f5[ ]*vpopcntq %xmm5,%xmm6\{%k7\} +[ ]*[a-f0-9]+:[ ]*62 f2 fd 8f 55 f5[ ]*vpopcntq %xmm5,%xmm6\{%k7\}\{z\} +[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 55 b4 f4 c0 1d fe ff[ ]*vpopcntq -0x1e240\(%esp,%esi,8\),%xmm6\{%k7\} +[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 55 72 7f[ ]*vpopcntq 0x7f0\(%edx\),%xmm6\{%k7\} +[ ]*[a-f0-9]+:[ ]*62 f2 fd 1f 55 72 7f[ ]*vpopcntq 0x3f8\(%edx\)\{1to2\},%xmm6\{%k7\} +[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 55 f5[ ]*vpopcntq %ymm5,%ymm6\{%k7\} +[ ]*[a-f0-9]+:[ ]*62 f2 fd af 55 f5[ ]*vpopcntq %ymm5,%ymm6\{%k7\}\{z\} +[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 55 b4 f4 c0 1d fe ff[ ]*vpopcntq -0x1e240\(%esp,%esi,8\),%ymm6\{%k7\} +[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 55 72 7f[ ]*vpopcntq 0xfe0\(%edx\),%ymm6\{%k7\} +[ ]*[a-f0-9]+:[ ]*62 f2 fd 3f 55 72 7f[ ]*vpopcntq 0x3f8\(%edx\)\{1to4\},%ymm6\{%k7\} +[ ]*[a-f0-9]+:[ ]*62 f2 55 0f 8f ec[ ]*vpshufbitqmb %xmm4,%xmm5,%k5\{%k7\} +[ ]*[a-f0-9]+:[ ]*62 f2 55 0f 8f ac f4 c0 1d fe ff[ ]*vpshufbitqmb -0x1e240\(%esp,%esi,8\),%xmm5,%k5\{%k7\} +[ ]*[a-f0-9]+:[ ]*62 f2 55 0f 8f 6a 7f[ ]*vpshufbitqmb 0x7f0\(%edx\),%xmm5,%k5\{%k7\} +[ ]*[a-f0-9]+:[ ]*62 f2 55 2f 8f ec[ ]*vpshufbitqmb %ymm4,%ymm5,%k5\{%k7\} +[ ]*[a-f0-9]+:[ ]*62 f2 55 2f 8f ac f4 c0 1d fe ff[ ]*vpshufbitqmb -0x1e240\(%esp,%esi,8\),%ymm5,%k5\{%k7\} +[ ]*[a-f0-9]+:[ ]*62 f2 55 2f 8f 6a 7f[ ]*vpshufbitqmb 0xfe0\(%edx\),%ymm5,%k5\{%k7\} +[ ]*[a-f0-9]+:[ ]*62 f2 7d 0f 54 f5[ ]*vpopcntb %xmm5,%xmm6\{%k7\} +[ ]*[a-f0-9]+:[ ]*62 f2 7d 8f 54 f5[ ]*vpopcntb %xmm5,%xmm6\{%k7\}\{z\} +[ ]*[a-f0-9]+:[ ]*62 f2 7d 0f 54 b4 f4 c0 1d fe ff[ ]*vpopcntb -0x1e240\(%esp,%esi,8\),%xmm6\{%k7\} +[ ]*[a-f0-9]+:[ ]*62 f2 7d 0f 54 72 7f[ ]*vpopcntb 0x7f0\(%edx\),%xmm6\{%k7\} +[ ]*[a-f0-9]+:[ ]*62 f2 7d 2f 54 f5[ ]*vpopcntb %ymm5,%ymm6\{%k7\} +[ ]*[a-f0-9]+:[ ]*62 f2 7d af 54 f5[ ]*vpopcntb %ymm5,%ymm6\{%k7\}\{z\} +[ ]*[a-f0-9]+:[ ]*62 f2 7d 2f 54 b4 f4 c0 1d fe ff[ ]*vpopcntb -0x1e240\(%esp,%esi,8\),%ymm6\{%k7\} +[ ]*[a-f0-9]+:[ ]*62 f2 7d 2f 54 72 7f[ ]*vpopcntb 0xfe0\(%edx\),%ymm6\{%k7\} +[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 54 f5[ ]*vpopcntw %xmm5,%xmm6\{%k7\} +[ ]*[a-f0-9]+:[ ]*62 f2 fd 8f 54 f5[ ]*vpopcntw %xmm5,%xmm6\{%k7\}\{z\} +[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 54 b4 f4 c0 1d fe ff[ ]*vpopcntw -0x1e240\(%esp,%esi,8\),%xmm6\{%k7\} +[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 54 72 7f[ ]*vpopcntw 0x7f0\(%edx\),%xmm6\{%k7\} +[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 54 f5[ ]*vpopcntw %ymm5,%ymm6\{%k7\} +[ ]*[a-f0-9]+:[ ]*62 f2 fd af 54 f5[ ]*vpopcntw %ymm5,%ymm6\{%k7\}\{z\} +[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 54 b4 f4 c0 1d fe ff[ ]*vpopcntw -0x1e240\(%esp,%esi,8\),%ymm6\{%k7\} +[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 54 72 7f[ ]*vpopcntw 0xfe0\(%edx\),%ymm6\{%k7\} +[ ]*[a-f0-9]+:[ ]*62 f2 7d 0f 55 f5[ ]*vpopcntd %xmm5,%xmm6\{%k7\} +[ ]*[a-f0-9]+:[ ]*62 f2 7d 8f 55 f5[ ]*vpopcntd %xmm5,%xmm6\{%k7\}\{z\} +[ ]*[a-f0-9]+:[ ]*62 f2 7d 0f 55 b4 f4 c0 1d fe ff[ ]*vpopcntd -0x1e240\(%esp,%esi,8\),%xmm6\{%k7\} +[ ]*[a-f0-9]+:[ ]*62 f2 7d 0f 55 72 7f[ ]*vpopcntd 0x7f0\(%edx\),%xmm6\{%k7\} +[ ]*[a-f0-9]+:[ ]*62 f2 7d 1f 55 72 7f[ ]*vpopcntd 0x1fc\(%edx\)\{1to4\},%xmm6\{%k7\} +[ ]*[a-f0-9]+:[ ]*62 f2 7d 2f 55 f5[ ]*vpopcntd %ymm5,%ymm6\{%k7\} +[ ]*[a-f0-9]+:[ ]*62 f2 7d af 55 f5[ ]*vpopcntd %ymm5,%ymm6\{%k7\}\{z\} +[ ]*[a-f0-9]+:[ ]*62 f2 7d 2f 55 b4 f4 c0 1d fe ff[ ]*vpopcntd -0x1e240\(%esp,%esi,8\),%ymm6\{%k7\} +[ ]*[a-f0-9]+:[ ]*62 f2 7d 2f 55 72 7f[ ]*vpopcntd 0xfe0\(%edx\),%ymm6\{%k7\} +[ ]*[a-f0-9]+:[ ]*62 f2 7d 3f 55 72 7f[ ]*vpopcntd 0x1fc\(%edx\)\{1to8\},%ymm6\{%k7\} +[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 55 f5[ ]*vpopcntq %xmm5,%xmm6\{%k7\} +[ ]*[a-f0-9]+:[ ]*62 f2 fd 8f 55 f5[ ]*vpopcntq %xmm5,%xmm6\{%k7\}\{z\} +[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 55 b4 f4 c0 1d fe ff[ ]*vpopcntq -0x1e240\(%esp,%esi,8\),%xmm6\{%k7\} +[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 55 72 7f[ ]*vpopcntq 0x7f0\(%edx\),%xmm6\{%k7\} +[ ]*[a-f0-9]+:[ ]*62 f2 fd 1f 55 72 7f[ ]*vpopcntq 0x3f8\(%edx\)\{1to2\},%xmm6\{%k7\} +[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 55 f5[ ]*vpopcntq %ymm5,%ymm6\{%k7\} +[ ]*[a-f0-9]+:[ ]*62 f2 fd af 55 f5[ ]*vpopcntq %ymm5,%ymm6\{%k7\}\{z\} +[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 55 b4 f4 c0 1d fe ff[ ]*vpopcntq -0x1e240\(%esp,%esi,8\),%ymm6\{%k7\} +[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 55 72 7f[ ]*vpopcntq 0xfe0\(%edx\),%ymm6\{%k7\} +[ ]*[a-f0-9]+:[ ]*62 f2 fd 3f 55 72 7f[ ]*vpopcntq 0x3f8\(%edx\)\{1to4\},%ymm6\{%k7\} +#pass diff --git a/gas/testsuite/gas/i386/avx512bitalg_vl.s b/gas/testsuite/gas/i386/avx512bitalg_vl.s new file mode 100644 index 0000000..1b1e73e --- /dev/null +++ b/gas/testsuite/gas/i386/avx512bitalg_vl.s @@ -0,0 +1,99 @@ +# Check 32bit AVX512{BITALG,VL} instructions + + .allow_index_reg + .text +_start: + vpshufbitqmb %xmm4, %xmm5, %k5{%k7} # AVX512{BITALG,VL} + vpshufbitqmb -123456(%esp,%esi,8), %xmm5, %k5{%k7} # AVX512{BITALG,VL} + vpshufbitqmb 2032(%edx), %xmm5, %k5{%k7} # AVX512{BITALG,VL} Disp8 + vpshufbitqmb %ymm4, %ymm5, %k5{%k7} # AVX512{BITALG,VL} + vpshufbitqmb -123456(%esp,%esi,8), %ymm5, %k5{%k7} # AVX512{BITALG,VL} + vpshufbitqmb 4064(%edx), %ymm5, %k5{%k7} # AVX512{BITALG,VL} Disp8 + + vpopcntb %xmm5, %xmm6{%k7} # AVX512{BITALG,VL} + vpopcntb %xmm5, %xmm6{%k7}{z} # AVX512{BITALG,VL} + vpopcntb -123456(%esp,%esi,8), %xmm6{%k7} # AVX512{BITALG,VL} + vpopcntb 2032(%edx), %xmm6{%k7} # AVX512{BITALG,VL} Disp8 + vpopcntb %ymm5, %ymm6{%k7} # AVX512{BITALG,VL} + vpopcntb %ymm5, %ymm6{%k7}{z} # AVX512{BITALG,VL} + vpopcntb -123456(%esp,%esi,8), %ymm6{%k7} # AVX512{BITALG,VL} + vpopcntb 4064(%edx), %ymm6{%k7} # AVX512{BITALG,VL} Disp8 + + vpopcntw %xmm5, %xmm6{%k7} # AVX512{BITALG,VL} + vpopcntw %xmm5, %xmm6{%k7}{z} # AVX512{BITALG,VL} + vpopcntw -123456(%esp,%esi,8), %xmm6{%k7} # AVX512{BITALG,VL} + vpopcntw 2032(%edx), %xmm6{%k7} # AVX512{BITALG,VL} Disp8 + vpopcntw %ymm5, %ymm6{%k7} # AVX512{BITALG,VL} + vpopcntw %ymm5, %ymm6{%k7}{z} # AVX512{BITALG,VL} + vpopcntw -123456(%esp,%esi,8), %ymm6{%k7} # AVX512{BITALG,VL} + vpopcntw 4064(%edx), %ymm6{%k7} # AVX512{BITALG,VL} Disp8 + + vpopcntd %xmm5, %xmm6{%k7} # AVX512{BITALG,VL} + vpopcntd %xmm5, %xmm6{%k7}{z} # AVX512{BITALG,VL} + vpopcntd -123456(%esp,%esi,8), %xmm6{%k7} # AVX512{BITALG,VL} + vpopcntd 2032(%edx), %xmm6{%k7} # AVX512{BITALG,VL} Disp8 + vpopcntd 508(%edx){1to4}, %xmm6{%k7} # AVX512{BITALG,VL} Disp8 + vpopcntd %ymm5, %ymm6{%k7} # AVX512{BITALG,VL} + vpopcntd %ymm5, %ymm6{%k7}{z} # AVX512{BITALG,VL} + vpopcntd -123456(%esp,%esi,8), %ymm6{%k7} # AVX512{BITALG,VL} + vpopcntd 4064(%edx), %ymm6{%k7} # AVX512{BITALG,VL} Disp8 + vpopcntd 508(%edx){1to8}, %ymm6{%k7} # AVX512{BITALG,VL} Disp8 + + vpopcntq %xmm5, %xmm6{%k7} # AVX512{BITALG,VL} + vpopcntq %xmm5, %xmm6{%k7}{z} # AVX512{BITALG,VL} + vpopcntq -123456(%esp,%esi,8), %xmm6{%k7} # AVX512{BITALG,VL} + vpopcntq 2032(%edx), %xmm6{%k7} # AVX512{BITALG,VL} Disp8 + vpopcntq 1016(%edx){1to2}, %xmm6{%k7} # AVX512{BITALG,VL} Disp8 + vpopcntq %ymm5, %ymm6{%k7} # AVX512{BITALG,VL} + vpopcntq %ymm5, %ymm6{%k7}{z} # AVX512{BITALG,VL} + vpopcntq -123456(%esp,%esi,8), %ymm6{%k7} # AVX512{BITALG,VL} + vpopcntq 4064(%edx), %ymm6{%k7} # AVX512{BITALG,VL} Disp8 + vpopcntq 1016(%edx){1to4}, %ymm6{%k7} # AVX512{BITALG,VL} Disp8 + + .intel_syntax noprefix + vpshufbitqmb k5{k7}, xmm5, xmm4 # AVX512{BITALG,VL} + vpshufbitqmb k5{k7}, xmm5, XMMWORD PTR [esp+esi*8-123456] # AVX512{BITALG,VL} + vpshufbitqmb k5{k7}, xmm5, XMMWORD PTR [edx+2032] # AVX512{BITALG,VL} Disp8 + vpshufbitqmb k5{k7}, ymm5, ymm4 # AVX512{BITALG,VL} + vpshufbitqmb k5{k7}, ymm5, YMMWORD PTR [esp+esi*8-123456] # AVX512{BITALG,VL} + vpshufbitqmb k5{k7}, ymm5, YMMWORD PTR [edx+4064] # AVX512{BITALG,VL} Disp8 + + vpopcntb xmm6{k7}, xmm5 # AVX512{BITALG,VL} + vpopcntb xmm6{k7}{z}, xmm5 # AVX512{BITALG,VL} + vpopcntb xmm6{k7}, XMMWORD PTR [esp+esi*8-123456] # AVX512{BITALG,VL} + vpopcntb xmm6{k7}, XMMWORD PTR [edx+2032] # AVX512{BITALG,VL} Disp8 + vpopcntb ymm6{k7}, ymm5 # AVX512{BITALG,VL} + vpopcntb ymm6{k7}{z}, ymm5 # AVX512{BITALG,VL} + vpopcntb ymm6{k7}, YMMWORD PTR [esp+esi*8-123456] # AVX512{BITALG,VL} + vpopcntb ymm6{k7}, YMMWORD PTR [edx+4064] # AVX512{BITALG,VL} Disp8 + + vpopcntw xmm6{k7}, xmm5 # AVX512{BITALG,VL} + vpopcntw xmm6{k7}{z}, xmm5 # AVX512{BITALG,VL} + vpopcntw xmm6{k7}, XMMWORD PTR [esp+esi*8-123456] # AVX512{BITALG,VL} + vpopcntw xmm6{k7}, XMMWORD PTR [edx+2032] # AVX512{BITALG,VL} Disp8 + vpopcntw ymm6{k7}, ymm5 # AVX512{BITALG,VL} + vpopcntw ymm6{k7}{z}, ymm5 # AVX512{BITALG,VL} + vpopcntw ymm6{k7}, YMMWORD PTR [esp+esi*8-123456] # AVX512{BITALG,VL} + vpopcntw ymm6{k7}, YMMWORD PTR [edx+4064] # AVX512{BITALG,VL} Disp8 + + vpopcntd xmm6{k7}, xmm5 # AVX512{BITALG,VL} + vpopcntd xmm6{k7}{z}, xmm5 # AVX512{BITALG,VL} + vpopcntd xmm6{k7}, XMMWORD PTR [esp+esi*8-123456] # AVX512{BITALG,VL} + vpopcntd xmm6{k7}, XMMWORD PTR [edx+2032] # AVX512{BITALG,VL} Disp8 + vpopcntd xmm6{k7}, [edx+508]{1to4} # AVX512{BITALG,VL} Disp8 + vpopcntd ymm6{k7}, ymm5 # AVX512{BITALG,VL} + vpopcntd ymm6{k7}{z}, ymm5 # AVX512{BITALG,VL} + vpopcntd ymm6{k7}, YMMWORD PTR [esp+esi*8-123456] # AVX512{BITALG,VL} + vpopcntd ymm6{k7}, YMMWORD PTR [edx+4064] # AVX512{BITALG,VL} Disp8 + vpopcntd ymm6{k7}, [edx+508]{1to8} # AVX512{BITALG,VL} Disp8 + + vpopcntq xmm6{k7}, xmm5 # AVX512{BITALG,VL} + vpopcntq xmm6{k7}{z}, xmm5 # AVX512{BITALG,VL} + vpopcntq xmm6{k7}, XMMWORD PTR [esp+esi*8-123456] # AVX512{BITALG,VL} + vpopcntq xmm6{k7}, XMMWORD PTR [edx+2032] # AVX512{BITALG,VL} Disp8 + vpopcntq xmm6{k7}, [edx+1016]{1to2} # AVX512{BITALG,VL} Disp8 + vpopcntq ymm6{k7}, ymm5 # AVX512{BITALG,VL} + vpopcntq ymm6{k7}{z}, ymm5 # AVX512{BITALG,VL} + vpopcntq ymm6{k7}, YMMWORD PTR [esp+esi*8-123456] # AVX512{BITALG,VL} + vpopcntq ymm6{k7}, YMMWORD PTR [edx+4064] # AVX512{BITALG,VL} Disp8 + vpopcntq ymm6{k7}, [edx+1016]{1to4} # AVX512{BITALG,VL} Disp8 diff --git a/gas/testsuite/gas/i386/i386.exp b/gas/testsuite/gas/i386/i386.exp index 0c79bbf..b6eb40a 100644 --- a/gas/testsuite/gas/i386/i386.exp +++ b/gas/testsuite/gas/i386/i386.exp @@ -398,6 +398,10 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_32_check]] run_dump_test "avx512vnni-intel" run_dump_test "avx512vnni_vl" run_dump_test "avx512vnni_vl-intel" + run_dump_test "avx512bitalg" + run_dump_test "avx512bitalg-intel" + run_dump_test "avx512bitalg_vl" + run_dump_test "avx512bitalg_vl-intel" run_dump_test "clzero" run_dump_test "disassem" run_dump_test "mwaitx-bdver4" @@ -855,6 +859,10 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_64_check]] t run_dump_test "x86-64-avx512vnni-intel" run_dump_test "x86-64-avx512vnni_vl" run_dump_test "x86-64-avx512vnni_vl-intel" + run_dump_test "x86-64-avx512bitalg" + run_dump_test "x86-64-avx512bitalg-intel" + run_dump_test "x86-64-avx512bitalg_vl" + run_dump_test "x86-64-avx512bitalg_vl-intel" run_dump_test "x86-64-clzero" run_dump_test "x86-64-mwaitx-bdver4" run_list_test "x86-64-mwaitx-reg" diff --git a/gas/testsuite/gas/i386/x86-64-avx512bitalg-intel.d b/gas/testsuite/gas/i386/x86-64-avx512bitalg-intel.d new file mode 100644 index 0000000..0b84232 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-avx512bitalg-intel.d @@ -0,0 +1,64 @@ +#as: +#objdump: -dw -Mintel +#name: x86_64 AVX512BITALG insns (Intel disassembly) +#source: x86-64-avx512bitalg.s + +.*: +file format .* + + +Disassembly of section \.text: + +0+ <_start>: +[ ]*[a-f0-9]+:[ ]*62 92 15 40 8f ec[ ]*vpshufbitqmb k5,zmm29,zmm28 +[ ]*[a-f0-9]+:[ ]*62 92 15 47 8f ec[ ]*vpshufbitqmb k5\{k7\},zmm29,zmm28 +[ ]*[a-f0-9]+:[ ]*62 b2 15 40 8f ac f0 23 01 00 00[ ]*vpshufbitqmb k5,zmm29,ZMMWORD PTR \[rax\+r14\*8\+0x123\] +[ ]*[a-f0-9]+:[ ]*62 f2 15 40 8f 6a 7f[ ]*vpshufbitqmb k5,zmm29,ZMMWORD PTR \[rdx\+0x1fc0\] +[ ]*[a-f0-9]+:[ ]*62 02 7d 48 54 f5[ ]*vpopcntb zmm30,zmm29 +[ ]*[a-f0-9]+:[ ]*62 02 7d 4f 54 f5[ ]*vpopcntb zmm30\{k7\},zmm29 +[ ]*[a-f0-9]+:[ ]*62 02 7d cf 54 f5[ ]*vpopcntb zmm30\{k7\}\{z\},zmm29 +[ ]*[a-f0-9]+:[ ]*62 22 7d 48 54 b4 f0 23 01 00 00[ ]*vpopcntb zmm30,ZMMWORD PTR \[rax\+r14\*8\+0x123\] +[ ]*[a-f0-9]+:[ ]*62 62 7d 48 54 72 7f[ ]*vpopcntb zmm30,ZMMWORD PTR \[rdx\+0x1fc0\] +[ ]*[a-f0-9]+:[ ]*62 02 fd 48 54 f5[ ]*vpopcntw zmm30,zmm29 +[ ]*[a-f0-9]+:[ ]*62 02 fd 4f 54 f5[ ]*vpopcntw zmm30\{k7\},zmm29 +[ ]*[a-f0-9]+:[ ]*62 02 fd cf 54 f5[ ]*vpopcntw zmm30\{k7\}\{z\},zmm29 +[ ]*[a-f0-9]+:[ ]*62 22 fd 48 54 b4 f0 23 01 00 00[ ]*vpopcntw zmm30,ZMMWORD PTR \[rax\+r14\*8\+0x123\] +[ ]*[a-f0-9]+:[ ]*62 62 fd 48 54 72 7f[ ]*vpopcntw zmm30,ZMMWORD PTR \[rdx\+0x1fc0\] +[ ]*[a-f0-9]+:[ ]*62 02 7d 48 55 f5[ ]*vpopcntd zmm30,zmm29 +[ ]*[a-f0-9]+:[ ]*62 02 7d 4f 55 f5[ ]*vpopcntd zmm30\{k7\},zmm29 +[ ]*[a-f0-9]+:[ ]*62 02 7d cf 55 f5[ ]*vpopcntd zmm30\{k7\}\{z\},zmm29 +[ ]*[a-f0-9]+:[ ]*62 22 7d 48 55 b4 f0 23 01 00 00[ ]*vpopcntd zmm30,ZMMWORD PTR \[rax\+r14\*8\+0x123\] +[ ]*[a-f0-9]+:[ ]*62 62 7d 48 55 72 7f[ ]*vpopcntd zmm30,ZMMWORD PTR \[rdx\+0x1fc0\] +[ ]*[a-f0-9]+:[ ]*62 62 7d 58 55 72 7f[ ]*vpopcntd zmm30,DWORD PTR \[rdx\+0x1fc\]\{1to16\} +[ ]*[a-f0-9]+:[ ]*62 02 fd 48 55 f5[ ]*vpopcntq zmm30,zmm29 +[ ]*[a-f0-9]+:[ ]*62 02 fd 4f 55 f5[ ]*vpopcntq zmm30\{k7\},zmm29 +[ ]*[a-f0-9]+:[ ]*62 02 fd cf 55 f5[ ]*vpopcntq zmm30\{k7\}\{z\},zmm29 +[ ]*[a-f0-9]+:[ ]*62 22 fd 48 55 b4 f0 23 01 00 00[ ]*vpopcntq zmm30,ZMMWORD PTR \[rax\+r14\*8\+0x123\] +[ ]*[a-f0-9]+:[ ]*62 62 fd 48 55 72 7f[ ]*vpopcntq zmm30,ZMMWORD PTR \[rdx\+0x1fc0\] +[ ]*[a-f0-9]+:[ ]*62 62 fd 58 55 72 7f[ ]*vpopcntq zmm30,QWORD PTR \[rdx\+0x3f8\]\{1to8\} +[ ]*[a-f0-9]+:[ ]*62 92 15 40 8f ec[ ]*vpshufbitqmb k5,zmm29,zmm28 +[ ]*[a-f0-9]+:[ ]*62 92 15 47 8f ec[ ]*vpshufbitqmb k5\{k7\},zmm29,zmm28 +[ ]*[a-f0-9]+:[ ]*62 b2 15 40 8f ac f0 34 12 00 00[ ]*vpshufbitqmb k5,zmm29,ZMMWORD PTR \[rax\+r14\*8\+0x1234\] +[ ]*[a-f0-9]+:[ ]*62 f2 15 40 8f 6a 7f[ ]*vpshufbitqmb k5,zmm29,ZMMWORD PTR \[rdx\+0x1fc0\] +[ ]*[a-f0-9]+:[ ]*62 02 7d 48 54 f5[ ]*vpopcntb zmm30,zmm29 +[ ]*[a-f0-9]+:[ ]*62 02 7d 4f 54 f5[ ]*vpopcntb zmm30\{k7\},zmm29 +[ ]*[a-f0-9]+:[ ]*62 02 7d cf 54 f5[ ]*vpopcntb zmm30\{k7\}\{z\},zmm29 +[ ]*[a-f0-9]+:[ ]*62 22 7d 48 54 b4 f0 34 12 00 00[ ]*vpopcntb zmm30,ZMMWORD PTR \[rax\+r14\*8\+0x1234\] +[ ]*[a-f0-9]+:[ ]*62 62 7d 48 54 72 7f[ ]*vpopcntb zmm30,ZMMWORD PTR \[rdx\+0x1fc0\] +[ ]*[a-f0-9]+:[ ]*62 02 fd 48 54 f5[ ]*vpopcntw zmm30,zmm29 +[ ]*[a-f0-9]+:[ ]*62 02 fd 4f 54 f5[ ]*vpopcntw zmm30\{k7\},zmm29 +[ ]*[a-f0-9]+:[ ]*62 02 fd cf 54 f5[ ]*vpopcntw zmm30\{k7\}\{z\},zmm29 +[ ]*[a-f0-9]+:[ ]*62 22 fd 48 54 b4 f0 34 12 00 00[ ]*vpopcntw zmm30,ZMMWORD PTR \[rax\+r14\*8\+0x1234\] +[ ]*[a-f0-9]+:[ ]*62 62 fd 48 54 72 7f[ ]*vpopcntw zmm30,ZMMWORD PTR \[rdx\+0x1fc0\] +[ ]*[a-f0-9]+:[ ]*62 02 7d 48 55 f5[ ]*vpopcntd zmm30,zmm29 +[ ]*[a-f0-9]+:[ ]*62 02 7d 4f 55 f5[ ]*vpopcntd zmm30\{k7\},zmm29 +[ ]*[a-f0-9]+:[ ]*62 02 7d cf 55 f5[ ]*vpopcntd zmm30\{k7\}\{z\},zmm29 +[ ]*[a-f0-9]+:[ ]*62 22 7d 48 55 b4 f0 34 12 00 00[ ]*vpopcntd zmm30,ZMMWORD PTR \[rax\+r14\*8\+0x1234\] +[ ]*[a-f0-9]+:[ ]*62 62 7d 48 55 72 7f[ ]*vpopcntd zmm30,ZMMWORD PTR \[rdx\+0x1fc0\] +[ ]*[a-f0-9]+:[ ]*62 62 7d 58 55 72 7f[ ]*vpopcntd zmm30,DWORD PTR \[rdx\+0x1fc\]\{1to16\} +[ ]*[a-f0-9]+:[ ]*62 02 fd 48 55 f5[ ]*vpopcntq zmm30,zmm29 +[ ]*[a-f0-9]+:[ ]*62 02 fd 4f 55 f5[ ]*vpopcntq zmm30\{k7\},zmm29 +[ ]*[a-f0-9]+:[ ]*62 02 fd cf 55 f5[ ]*vpopcntq zmm30\{k7\}\{z\},zmm29 +[ ]*[a-f0-9]+:[ ]*62 22 fd 48 55 b4 f0 34 12 00 00[ ]*vpopcntq zmm30,ZMMWORD PTR \[rax\+r14\*8\+0x1234\] +[ ]*[a-f0-9]+:[ ]*62 62 fd 48 55 72 7f[ ]*vpopcntq zmm30,ZMMWORD PTR \[rdx\+0x1fc0\] +[ ]*[a-f0-9]+:[ ]*62 62 fd 58 55 72 7f[ ]*vpopcntq zmm30,QWORD PTR \[rdx\+0x3f8\]\{1to8\} +#pass diff --git a/gas/testsuite/gas/i386/x86-64-avx512bitalg.d b/gas/testsuite/gas/i386/x86-64-avx512bitalg.d new file mode 100644 index 0000000..27f2e90 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-avx512bitalg.d @@ -0,0 +1,64 @@ +#as: +#objdump: -dw +#name: x86_64 AVX512BITALG insns +#source: x86-64-avx512bitalg.s + +.*: +file format .* + + +Disassembly of section \.text: + +0+ <_start>: +[ ]*[a-f0-9]+:[ ]*62 92 15 40 8f ec[ ]*vpshufbitqmb %zmm28,%zmm29,%k5 +[ ]*[a-f0-9]+:[ ]*62 92 15 47 8f ec[ ]*vpshufbitqmb %zmm28,%zmm29,%k5\{%k7\} +[ ]*[a-f0-9]+:[ ]*62 b2 15 40 8f ac f0 23 01 00 00[ ]*vpshufbitqmb 0x123\(%rax,%r14,8\),%zmm29,%k5 +[ ]*[a-f0-9]+:[ ]*62 f2 15 40 8f 6a 7f[ ]*vpshufbitqmb 0x1fc0\(%rdx\),%zmm29,%k5 +[ ]*[a-f0-9]+:[ ]*62 02 7d 48 54 f5[ ]*vpopcntb %zmm29,%zmm30 +[ ]*[a-f0-9]+:[ ]*62 02 7d 4f 54 f5[ ]*vpopcntb %zmm29,%zmm30\{%k7\} +[ ]*[a-f0-9]+:[ ]*62 02 7d cf 54 f5[ ]*vpopcntb %zmm29,%zmm30\{%k7\}\{z\} +[ ]*[a-f0-9]+:[ ]*62 22 7d 48 54 b4 f0 23 01 00 00[ ]*vpopcntb 0x123\(%rax,%r14,8\),%zmm30 +[ ]*[a-f0-9]+:[ ]*62 62 7d 48 54 72 7f[ ]*vpopcntb 0x1fc0\(%rdx\),%zmm30 +[ ]*[a-f0-9]+:[ ]*62 02 fd 48 54 f5[ ]*vpopcntw %zmm29,%zmm30 +[ ]*[a-f0-9]+:[ ]*62 02 fd 4f 54 f5[ ]*vpopcntw %zmm29,%zmm30\{%k7\} +[ ]*[a-f0-9]+:[ ]*62 02 fd cf 54 f5[ ]*vpopcntw %zmm29,%zmm30\{%k7\}\{z\} +[ ]*[a-f0-9]+:[ ]*62 22 fd 48 54 b4 f0 23 01 00 00[ ]*vpopcntw 0x123\(%rax,%r14,8\),%zmm30 +[ ]*[a-f0-9]+:[ ]*62 62 fd 48 54 72 7f[ ]*vpopcntw 0x1fc0\(%rdx\),%zmm30 +[ ]*[a-f0-9]+:[ ]*62 02 7d 48 55 f5[ ]*vpopcntd %zmm29,%zmm30 +[ ]*[a-f0-9]+:[ ]*62 02 7d 4f 55 f5[ ]*vpopcntd %zmm29,%zmm30\{%k7\} +[ ]*[a-f0-9]+:[ ]*62 02 7d cf 55 f5[ ]*vpopcntd %zmm29,%zmm30\{%k7\}\{z\} +[ ]*[a-f0-9]+:[ ]*62 22 7d 48 55 b4 f0 23 01 00 00[ ]*vpopcntd 0x123\(%rax,%r14,8\),%zmm30 +[ ]*[a-f0-9]+:[ ]*62 62 7d 48 55 72 7f[ ]*vpopcntd 0x1fc0\(%rdx\),%zmm30 +[ ]*[a-f0-9]+:[ ]*62 62 7d 58 55 72 7f[ ]*vpopcntd 0x1fc\(%rdx\)\{1to16\},%zmm30 +[ ]*[a-f0-9]+:[ ]*62 02 fd 48 55 f5[ ]*vpopcntq %zmm29,%zmm30 +[ ]*[a-f0-9]+:[ ]*62 02 fd 4f 55 f5[ ]*vpopcntq %zmm29,%zmm30\{%k7\} +[ ]*[a-f0-9]+:[ ]*62 02 fd cf 55 f5[ ]*vpopcntq %zmm29,%zmm30\{%k7\}\{z\} +[ ]*[a-f0-9]+:[ ]*62 22 fd 48 55 b4 f0 23 01 00 00[ ]*vpopcntq 0x123\(%rax,%r14,8\),%zmm30 +[ ]*[a-f0-9]+:[ ]*62 62 fd 48 55 72 7f[ ]*vpopcntq 0x1fc0\(%rdx\),%zmm30 +[ ]*[a-f0-9]+:[ ]*62 62 fd 58 55 72 7f[ ]*vpopcntq 0x3f8\(%rdx\)\{1to8\},%zmm30 +[ ]*[a-f0-9]+:[ ]*62 92 15 40 8f ec[ ]*vpshufbitqmb %zmm28,%zmm29,%k5 +[ ]*[a-f0-9]+:[ ]*62 92 15 47 8f ec[ ]*vpshufbitqmb %zmm28,%zmm29,%k5\{%k7\} +[ ]*[a-f0-9]+:[ ]*62 b2 15 40 8f ac f0 34 12 00 00[ ]*vpshufbitqmb 0x1234\(%rax,%r14,8\),%zmm29,%k5 +[ ]*[a-f0-9]+:[ ]*62 f2 15 40 8f 6a 7f[ ]*vpshufbitqmb 0x1fc0\(%rdx\),%zmm29,%k5 +[ ]*[a-f0-9]+:[ ]*62 02 7d 48 54 f5[ ]*vpopcntb %zmm29,%zmm30 +[ ]*[a-f0-9]+:[ ]*62 02 7d 4f 54 f5[ ]*vpopcntb %zmm29,%zmm30\{%k7\} +[ ]*[a-f0-9]+:[ ]*62 02 7d cf 54 f5[ ]*vpopcntb %zmm29,%zmm30\{%k7\}\{z\} +[ ]*[a-f0-9]+:[ ]*62 22 7d 48 54 b4 f0 34 12 00 00[ ]*vpopcntb 0x1234\(%rax,%r14,8\),%zmm30 +[ ]*[a-f0-9]+:[ ]*62 62 7d 48 54 72 7f[ ]*vpopcntb 0x1fc0\(%rdx\),%zmm30 +[ ]*[a-f0-9]+:[ ]*62 02 fd 48 54 f5[ ]*vpopcntw %zmm29,%zmm30 +[ ]*[a-f0-9]+:[ ]*62 02 fd 4f 54 f5[ ]*vpopcntw %zmm29,%zmm30\{%k7\} +[ ]*[a-f0-9]+:[ ]*62 02 fd cf 54 f5[ ]*vpopcntw %zmm29,%zmm30\{%k7\}\{z\} +[ ]*[a-f0-9]+:[ ]*62 22 fd 48 54 b4 f0 34 12 00 00[ ]*vpopcntw 0x1234\(%rax,%r14,8\),%zmm30 +[ ]*[a-f0-9]+:[ ]*62 62 fd 48 54 72 7f[ ]*vpopcntw 0x1fc0\(%rdx\),%zmm30 +[ ]*[a-f0-9]+:[ ]*62 02 7d 48 55 f5[ ]*vpopcntd %zmm29,%zmm30 +[ ]*[a-f0-9]+:[ ]*62 02 7d 4f 55 f5[ ]*vpopcntd %zmm29,%zmm30\{%k7\} +[ ]*[a-f0-9]+:[ ]*62 02 7d cf 55 f5[ ]*vpopcntd %zmm29,%zmm30\{%k7\}\{z\} +[ ]*[a-f0-9]+:[ ]*62 22 7d 48 55 b4 f0 34 12 00 00[ ]*vpopcntd 0x1234\(%rax,%r14,8\),%zmm30 +[ ]*[a-f0-9]+:[ ]*62 62 7d 48 55 72 7f[ ]*vpopcntd 0x1fc0\(%rdx\),%zmm30 +[ ]*[a-f0-9]+:[ ]*62 62 7d 58 55 72 7f[ ]*vpopcntd 0x1fc\(%rdx\)\{1to16\},%zmm30 +[ ]*[a-f0-9]+:[ ]*62 02 fd 48 55 f5[ ]*vpopcntq %zmm29,%zmm30 +[ ]*[a-f0-9]+:[ ]*62 02 fd 4f 55 f5[ ]*vpopcntq %zmm29,%zmm30\{%k7\} +[ ]*[a-f0-9]+:[ ]*62 02 fd cf 55 f5[ ]*vpopcntq %zmm29,%zmm30\{%k7\}\{z\} +[ ]*[a-f0-9]+:[ ]*62 22 fd 48 55 b4 f0 34 12 00 00[ ]*vpopcntq 0x1234\(%rax,%r14,8\),%zmm30 +[ ]*[a-f0-9]+:[ ]*62 62 fd 48 55 72 7f[ ]*vpopcntq 0x1fc0\(%rdx\),%zmm30 +[ ]*[a-f0-9]+:[ ]*62 62 fd 58 55 72 7f[ ]*vpopcntq 0x3f8\(%rdx\)\{1to8\},%zmm30 +#pass diff --git a/gas/testsuite/gas/i386/x86-64-avx512bitalg.s b/gas/testsuite/gas/i386/x86-64-avx512bitalg.s new file mode 100644 index 0000000..73224e9 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-avx512bitalg.s @@ -0,0 +1,67 @@ +# Check 64bit AVX512BITALG instructions + + .allow_index_reg + .text +_start: + vpshufbitqmb %zmm28, %zmm29, %k5 # AVX512BITALG + vpshufbitqmb %zmm28, %zmm29, %k5{%k7} # AVX512BITALG + vpshufbitqmb 0x123(%rax,%r14,8), %zmm29, %k5 # AVX512BITALG + vpshufbitqmb 8128(%rdx), %zmm29, %k5 # AVX512BITALG Disp8 + + vpopcntb %zmm29, %zmm30 # AVX512BITALG + vpopcntb %zmm29, %zmm30{%k7} # AVX512BITALG + vpopcntb %zmm29, %zmm30{%k7}{z} # AVX512BITALG + vpopcntb 0x123(%rax,%r14,8), %zmm30 # AVX512BITALG + vpopcntb 8128(%rdx), %zmm30 # AVX512BITALG Disp8 + + vpopcntw %zmm29, %zmm30 # AVX512BITALG + vpopcntw %zmm29, %zmm30{%k7} # AVX512BITALG + vpopcntw %zmm29, %zmm30{%k7}{z} # AVX512BITALG + vpopcntw 0x123(%rax,%r14,8), %zmm30 # AVX512BITALG + vpopcntw 8128(%rdx), %zmm30 # AVX512BITALG Disp8 + + vpopcntd %zmm29, %zmm30 # AVX512BITALG + vpopcntd %zmm29, %zmm30{%k7} # AVX512BITALG + vpopcntd %zmm29, %zmm30{%k7}{z} # AVX512BITALG + vpopcntd 0x123(%rax,%r14,8), %zmm30 # AVX512BITALG + vpopcntd 8128(%rdx), %zmm30 # AVX512BITALG Disp8 + vpopcntd 508(%rdx){1to16}, %zmm30 # AVX512BITALG Disp8 + + vpopcntq %zmm29, %zmm30 # AVX512BITALG + vpopcntq %zmm29, %zmm30{%k7} # AVX512BITALG + vpopcntq %zmm29, %zmm30{%k7}{z} # AVX512BITALG + vpopcntq 0x123(%rax,%r14,8), %zmm30 # AVX512BITALG + vpopcntq 8128(%rdx), %zmm30 # AVX512BITALG Disp8 + vpopcntq 1016(%rdx){1to8}, %zmm30 # AVX512BITALG Disp8 + + .intel_syntax noprefix + vpshufbitqmb k5, zmm29, zmm28 # AVX512BITALG + vpshufbitqmb k5{k7}, zmm29, zmm28 # AVX512BITALG + vpshufbitqmb k5, zmm29, ZMMWORD PTR [rax+r14*8+0x1234] # AVX512BITALG + vpshufbitqmb k5, zmm29, ZMMWORD PTR [rdx+8128] # AVX512BITALG Disp8 + + vpopcntb zmm30, zmm29 # AVX512BITALG + vpopcntb zmm30{k7}, zmm29 # AVX512BITALG + vpopcntb zmm30{k7}{z}, zmm29 # AVX512BITALG + vpopcntb zmm30, ZMMWORD PTR [rax+r14*8+0x1234] # AVX512BITALG + vpopcntb zmm30, ZMMWORD PTR [rdx+8128] # AVX512BITALG Disp8 + + vpopcntw zmm30, zmm29 # AVX512BITALG + vpopcntw zmm30{k7}, zmm29 # AVX512BITALG + vpopcntw zmm30{k7}{z}, zmm29 # AVX512BITALG + vpopcntw zmm30, ZMMWORD PTR [rax+r14*8+0x1234] # AVX512BITALG + vpopcntw zmm30, ZMMWORD PTR [rdx+8128] # AVX512BITALG Disp8 + + vpopcntd zmm30, zmm29 # AVX512BITALG + vpopcntd zmm30{k7}, zmm29 # AVX512BITALG + vpopcntd zmm30{k7}{z}, zmm29 # AVX512BITALG + vpopcntd zmm30, ZMMWORD PTR [rax+r14*8+0x1234] # AVX512BITALG + vpopcntd zmm30, ZMMWORD PTR [rdx+8128] # AVX512BITALG Disp8 + vpopcntd zmm30, [rdx+508]{1to16} # AVX512BITALG Disp8 + + vpopcntq zmm30, zmm29 # AVX512BITALG + vpopcntq zmm30{k7}, zmm29 # AVX512BITALG + vpopcntq zmm30{k7}{z}, zmm29 # AVX512BITALG + vpopcntq zmm30, ZMMWORD PTR [rax+r14*8+0x1234] # AVX512BITALG + vpopcntq zmm30, ZMMWORD PTR [rdx+8128] # AVX512BITALG Disp8 + vpopcntq zmm30, [rdx+1016]{1to8} # AVX512BITALG Disp8 diff --git a/gas/testsuite/gas/i386/x86-64-avx512bitalg_vl-intel.d b/gas/testsuite/gas/i386/x86-64-avx512bitalg_vl-intel.d new file mode 100644 index 0000000..b9b795b --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-avx512bitalg_vl-intel.d @@ -0,0 +1,116 @@ +#as: +#objdump: -dw -Mintel +#name: x86_64 AVX512BITALG/VL insns (Intel disassembly) +#source: x86-64-avx512bitalg_vl.s + +.*: +file format .* + + +Disassembly of section \.text: + +0+ <_start>: +[ ]*[a-f0-9]+:[ ]*62 92 15 00 8f ec[ ]*vpshufbitqmb k5,xmm29,xmm28 +[ ]*[a-f0-9]+:[ ]*62 92 15 07 8f ec[ ]*vpshufbitqmb k5\{k7\},xmm29,xmm28 +[ ]*[a-f0-9]+:[ ]*62 b2 15 00 8f ac f0 23 01 00 00[ ]*vpshufbitqmb k5,xmm29,XMMWORD PTR \[rax\+r14\*8\+0x123\] +[ ]*[a-f0-9]+:[ ]*62 f2 15 00 8f 6a 7f[ ]*vpshufbitqmb k5,xmm29,XMMWORD PTR \[rdx\+0x7f0\] +[ ]*[a-f0-9]+:[ ]*62 92 15 20 8f ec[ ]*vpshufbitqmb k5,ymm29,ymm28 +[ ]*[a-f0-9]+:[ ]*62 92 15 27 8f ec[ ]*vpshufbitqmb k5\{k7\},ymm29,ymm28 +[ ]*[a-f0-9]+:[ ]*62 b2 15 20 8f ac f0 23 01 00 00[ ]*vpshufbitqmb k5,ymm29,YMMWORD PTR \[rax\+r14\*8\+0x123\] +[ ]*[a-f0-9]+:[ ]*62 f2 15 20 8f 6a 7f[ ]*vpshufbitqmb k5,ymm29,YMMWORD PTR \[rdx\+0xfe0\] +[ ]*[a-f0-9]+:[ ]*62 02 7d 08 54 f5[ ]*vpopcntb xmm30,xmm29 +[ ]*[a-f0-9]+:[ ]*62 02 7d 0f 54 f5[ ]*vpopcntb xmm30\{k7\},xmm29 +[ ]*[a-f0-9]+:[ ]*62 02 7d 8f 54 f5[ ]*vpopcntb xmm30\{k7\}\{z\},xmm29 +[ ]*[a-f0-9]+:[ ]*62 22 7d 08 54 b4 f0 23 01 00 00[ ]*vpopcntb xmm30,XMMWORD PTR \[rax\+r14\*8\+0x123\] +[ ]*[a-f0-9]+:[ ]*62 62 7d 08 54 72 7f[ ]*vpopcntb xmm30,XMMWORD PTR \[rdx\+0x7f0\] +[ ]*[a-f0-9]+:[ ]*62 02 7d 28 54 f5[ ]*vpopcntb ymm30,ymm29 +[ ]*[a-f0-9]+:[ ]*62 02 7d 2f 54 f5[ ]*vpopcntb ymm30\{k7\},ymm29 +[ ]*[a-f0-9]+:[ ]*62 02 7d af 54 f5[ ]*vpopcntb ymm30\{k7\}\{z\},ymm29 +[ ]*[a-f0-9]+:[ ]*62 22 7d 28 54 b4 f0 23 01 00 00[ ]*vpopcntb ymm30,YMMWORD PTR \[rax\+r14\*8\+0x123\] +[ ]*[a-f0-9]+:[ ]*62 62 7d 28 54 72 7f[ ]*vpopcntb ymm30,YMMWORD PTR \[rdx\+0xfe0\] +[ ]*[a-f0-9]+:[ ]*62 02 fd 08 54 f5[ ]*vpopcntw xmm30,xmm29 +[ ]*[a-f0-9]+:[ ]*62 02 fd 0f 54 f5[ ]*vpopcntw xmm30\{k7\},xmm29 +[ ]*[a-f0-9]+:[ ]*62 02 fd 8f 54 f5[ ]*vpopcntw xmm30\{k7\}\{z\},xmm29 +[ ]*[a-f0-9]+:[ ]*62 22 fd 08 54 b4 f0 23 01 00 00[ ]*vpopcntw xmm30,XMMWORD PTR \[rax\+r14\*8\+0x123\] +[ ]*[a-f0-9]+:[ ]*62 62 fd 08 54 72 7f[ ]*vpopcntw xmm30,XMMWORD PTR \[rdx\+0x7f0\] +[ ]*[a-f0-9]+:[ ]*62 02 fd 28 54 f5[ ]*vpopcntw ymm30,ymm29 +[ ]*[a-f0-9]+:[ ]*62 02 fd 2f 54 f5[ ]*vpopcntw ymm30\{k7\},ymm29 +[ ]*[a-f0-9]+:[ ]*62 02 fd af 54 f5[ ]*vpopcntw ymm30\{k7\}\{z\},ymm29 +[ ]*[a-f0-9]+:[ ]*62 22 fd 28 54 b4 f0 23 01 00 00[ ]*vpopcntw ymm30,YMMWORD PTR \[rax\+r14\*8\+0x123\] +[ ]*[a-f0-9]+:[ ]*62 62 fd 28 54 72 7f[ ]*vpopcntw ymm30,YMMWORD PTR \[rdx\+0xfe0\] +[ ]*[a-f0-9]+:[ ]*62 02 7d 08 55 f5[ ]*vpopcntd xmm30,xmm29 +[ ]*[a-f0-9]+:[ ]*62 02 7d 0f 55 f5[ ]*vpopcntd xmm30\{k7\},xmm29 +[ ]*[a-f0-9]+:[ ]*62 02 7d 8f 55 f5[ ]*vpopcntd xmm30\{k7\}\{z\},xmm29 +[ ]*[a-f0-9]+:[ ]*62 22 7d 08 55 b4 f0 23 01 00 00[ ]*vpopcntd xmm30,XMMWORD PTR \[rax\+r14\*8\+0x123\] +[ ]*[a-f0-9]+:[ ]*62 62 7d 08 55 72 7f[ ]*vpopcntd xmm30,XMMWORD PTR \[rdx\+0x7f0\] +[ ]*[a-f0-9]+:[ ]*62 62 7d 18 55 72 7f[ ]*vpopcntd xmm30,DWORD PTR \[rdx\+0x1fc\]\{1to4\} +[ ]*[a-f0-9]+:[ ]*62 02 7d 28 55 f5[ ]*vpopcntd ymm30,ymm29 +[ ]*[a-f0-9]+:[ ]*62 02 7d 2f 55 f5[ ]*vpopcntd ymm30\{k7\},ymm29 +[ ]*[a-f0-9]+:[ ]*62 02 7d af 55 f5[ ]*vpopcntd ymm30\{k7\}\{z\},ymm29 +[ ]*[a-f0-9]+:[ ]*62 22 7d 28 55 b4 f0 23 01 00 00[ ]*vpopcntd ymm30,YMMWORD PTR \[rax\+r14\*8\+0x123\] +[ ]*[a-f0-9]+:[ ]*62 62 7d 28 55 72 7f[ ]*vpopcntd ymm30,YMMWORD PTR \[rdx\+0xfe0\] +[ ]*[a-f0-9]+:[ ]*62 62 7d 38 55 72 7f[ ]*vpopcntd ymm30,DWORD PTR \[rdx\+0x1fc\]\{1to8\} +[ ]*[a-f0-9]+:[ ]*62 02 fd 08 55 f5[ ]*vpopcntq xmm30,xmm29 +[ ]*[a-f0-9]+:[ ]*62 02 fd 0f 55 f5[ ]*vpopcntq xmm30\{k7\},xmm29 +[ ]*[a-f0-9]+:[ ]*62 02 fd 8f 55 f5[ ]*vpopcntq xmm30\{k7\}\{z\},xmm29 +[ ]*[a-f0-9]+:[ ]*62 22 fd 08 55 b4 f0 23 01 00 00[ ]*vpopcntq xmm30,XMMWORD PTR \[rax\+r14\*8\+0x123\] +[ ]*[a-f0-9]+:[ ]*62 62 fd 08 55 72 7f[ ]*vpopcntq xmm30,XMMWORD PTR \[rdx\+0x7f0\] +[ ]*[a-f0-9]+:[ ]*62 62 fd 18 55 72 7f[ ]*vpopcntq xmm30,QWORD PTR \[rdx\+0x3f8\]\{1to2\} +[ ]*[a-f0-9]+:[ ]*62 02 fd 28 55 f5[ ]*vpopcntq ymm30,ymm29 +[ ]*[a-f0-9]+:[ ]*62 02 fd 2f 55 f5[ ]*vpopcntq ymm30\{k7\},ymm29 +[ ]*[a-f0-9]+:[ ]*62 02 fd af 55 f5[ ]*vpopcntq ymm30\{k7\}\{z\},ymm29 +[ ]*[a-f0-9]+:[ ]*62 22 fd 28 55 b4 f0 23 01 00 00[ ]*vpopcntq ymm30,YMMWORD PTR \[rax\+r14\*8\+0x123\] +[ ]*[a-f0-9]+:[ ]*62 62 fd 28 55 72 7f[ ]*vpopcntq ymm30,YMMWORD PTR \[rdx\+0xfe0\] +[ ]*[a-f0-9]+:[ ]*62 62 fd 38 55 72 7f[ ]*vpopcntq ymm30,QWORD PTR \[rdx\+0x3f8\]\{1to4\} +[ ]*[a-f0-9]+:[ ]*62 92 15 00 8f ec[ ]*vpshufbitqmb k5,xmm29,xmm28 +[ ]*[a-f0-9]+:[ ]*62 92 15 07 8f ec[ ]*vpshufbitqmb k5\{k7\},xmm29,xmm28 +[ ]*[a-f0-9]+:[ ]*62 b2 15 00 8f ac f0 34 12 00 00[ ]*vpshufbitqmb k5,xmm29,XMMWORD PTR \[rax\+r14\*8\+0x1234\] +[ ]*[a-f0-9]+:[ ]*62 f2 15 00 8f 6a 7f[ ]*vpshufbitqmb k5,xmm29,XMMWORD PTR \[rdx\+0x7f0\] +[ ]*[a-f0-9]+:[ ]*62 92 15 20 8f ec[ ]*vpshufbitqmb k5,ymm29,ymm28 +[ ]*[a-f0-9]+:[ ]*62 92 15 27 8f ec[ ]*vpshufbitqmb k5\{k7\},ymm29,ymm28 +[ ]*[a-f0-9]+:[ ]*62 b2 15 20 8f ac f0 34 12 00 00[ ]*vpshufbitqmb k5,ymm29,YMMWORD PTR \[rax\+r14\*8\+0x1234\] +[ ]*[a-f0-9]+:[ ]*62 f2 15 20 8f 6a 7f[ ]*vpshufbitqmb k5,ymm29,YMMWORD PTR \[rdx\+0xfe0\] +[ ]*[a-f0-9]+:[ ]*62 02 7d 08 54 f5[ ]*vpopcntb xmm30,xmm29 +[ ]*[a-f0-9]+:[ ]*62 02 7d 0f 54 f5[ ]*vpopcntb xmm30\{k7\},xmm29 +[ ]*[a-f0-9]+:[ ]*62 02 7d 8f 54 f5[ ]*vpopcntb xmm30\{k7\}\{z\},xmm29 +[ ]*[a-f0-9]+:[ ]*62 22 7d 08 54 b4 f0 34 12 00 00[ ]*vpopcntb xmm30,XMMWORD PTR \[rax\+r14\*8\+0x1234\] +[ ]*[a-f0-9]+:[ ]*62 62 7d 08 54 72 7f[ ]*vpopcntb xmm30,XMMWORD PTR \[rdx\+0x7f0\] +[ ]*[a-f0-9]+:[ ]*62 02 7d 28 54 f5[ ]*vpopcntb ymm30,ymm29 +[ ]*[a-f0-9]+:[ ]*62 02 7d 2f 54 f5[ ]*vpopcntb ymm30\{k7\},ymm29 +[ ]*[a-f0-9]+:[ ]*62 02 7d af 54 f5[ ]*vpopcntb ymm30\{k7\}\{z\},ymm29 +[ ]*[a-f0-9]+:[ ]*62 22 7d 28 54 b4 f0 34 12 00 00[ ]*vpopcntb ymm30,YMMWORD PTR \[rax\+r14\*8\+0x1234\] +[ ]*[a-f0-9]+:[ ]*62 62 7d 28 54 72 7f[ ]*vpopcntb ymm30,YMMWORD PTR \[rdx\+0xfe0\] +[ ]*[a-f0-9]+:[ ]*62 02 fd 08 54 f5[ ]*vpopcntw xmm30,xmm29 +[ ]*[a-f0-9]+:[ ]*62 02 fd 0f 54 f5[ ]*vpopcntw xmm30\{k7\},xmm29 +[ ]*[a-f0-9]+:[ ]*62 02 fd 8f 54 f5[ ]*vpopcntw xmm30\{k7\}\{z\},xmm29 +[ ]*[a-f0-9]+:[ ]*62 22 fd 08 54 b4 f0 34 12 00 00[ ]*vpopcntw xmm30,XMMWORD PTR \[rax\+r14\*8\+0x1234\] +[ ]*[a-f0-9]+:[ ]*62 62 fd 08 54 72 7f[ ]*vpopcntw xmm30,XMMWORD PTR \[rdx\+0x7f0\] +[ ]*[a-f0-9]+:[ ]*62 02 fd 28 54 f5[ ]*vpopcntw ymm30,ymm29 +[ ]*[a-f0-9]+:[ ]*62 02 fd 2f 54 f5[ ]*vpopcntw ymm30\{k7\},ymm29 +[ ]*[a-f0-9]+:[ ]*62 02 fd af 54 f5[ ]*vpopcntw ymm30\{k7\}\{z\},ymm29 +[ ]*[a-f0-9]+:[ ]*62 22 fd 28 54 b4 f0 34 12 00 00[ ]*vpopcntw ymm30,YMMWORD PTR \[rax\+r14\*8\+0x1234\] +[ ]*[a-f0-9]+:[ ]*62 62 fd 28 54 72 7f[ ]*vpopcntw ymm30,YMMWORD PTR \[rdx\+0xfe0\] +[ ]*[a-f0-9]+:[ ]*62 02 7d 08 55 f5[ ]*vpopcntd xmm30,xmm29 +[ ]*[a-f0-9]+:[ ]*62 02 7d 0f 55 f5[ ]*vpopcntd xmm30\{k7\},xmm29 +[ ]*[a-f0-9]+:[ ]*62 02 7d 8f 55 f5[ ]*vpopcntd xmm30\{k7\}\{z\},xmm29 +[ ]*[a-f0-9]+:[ ]*62 22 7d 08 55 b4 f0 34 12 00 00[ ]*vpopcntd xmm30,XMMWORD PTR \[rax\+r14\*8\+0x1234\] +[ ]*[a-f0-9]+:[ ]*62 62 7d 08 55 72 7f[ ]*vpopcntd xmm30,XMMWORD PTR \[rdx\+0x7f0\] +[ ]*[a-f0-9]+:[ ]*62 62 7d 18 55 72 7f[ ]*vpopcntd xmm30,DWORD PTR \[rdx\+0x1fc\]\{1to4\} +[ ]*[a-f0-9]+:[ ]*62 02 7d 28 55 f5[ ]*vpopcntd ymm30,ymm29 +[ ]*[a-f0-9]+:[ ]*62 02 7d 2f 55 f5[ ]*vpopcntd ymm30\{k7\},ymm29 +[ ]*[a-f0-9]+:[ ]*62 02 7d af 55 f5[ ]*vpopcntd ymm30\{k7\}\{z\},ymm29 +[ ]*[a-f0-9]+:[ ]*62 22 7d 28 55 b4 f0 34 12 00 00[ ]*vpopcntd ymm30,YMMWORD PTR \[rax\+r14\*8\+0x1234\] +[ ]*[a-f0-9]+:[ ]*62 62 7d 28 55 72 7f[ ]*vpopcntd ymm30,YMMWORD PTR \[rdx\+0xfe0\] +[ ]*[a-f0-9]+:[ ]*62 62 7d 38 55 72 7f[ ]*vpopcntd ymm30,DWORD PTR \[rdx\+0x1fc\]\{1to8\} +[ ]*[a-f0-9]+:[ ]*62 02 fd 08 55 f5[ ]*vpopcntq xmm30,xmm29 +[ ]*[a-f0-9]+:[ ]*62 02 fd 0f 55 f5[ ]*vpopcntq xmm30\{k7\},xmm29 +[ ]*[a-f0-9]+:[ ]*62 02 fd 8f 55 f5[ ]*vpopcntq xmm30\{k7\}\{z\},xmm29 +[ ]*[a-f0-9]+:[ ]*62 22 fd 08 55 b4 f0 34 12 00 00[ ]*vpopcntq xmm30,XMMWORD PTR \[rax\+r14\*8\+0x1234\] +[ ]*[a-f0-9]+:[ ]*62 62 fd 08 55 72 7f[ ]*vpopcntq xmm30,XMMWORD PTR \[rdx\+0x7f0\] +[ ]*[a-f0-9]+:[ ]*62 62 fd 18 55 72 7f[ ]*vpopcntq xmm30,QWORD PTR \[rdx\+0x3f8\]\{1to2\} +[ ]*[a-f0-9]+:[ ]*62 02 fd 28 55 f5[ ]*vpopcntq ymm30,ymm29 +[ ]*[a-f0-9]+:[ ]*62 02 fd 2f 55 f5[ ]*vpopcntq ymm30\{k7\},ymm29 +[ ]*[a-f0-9]+:[ ]*62 02 fd af 55 f5[ ]*vpopcntq ymm30\{k7\}\{z\},ymm29 +[ ]*[a-f0-9]+:[ ]*62 22 fd 28 55 b4 f0 34 12 00 00[ ]*vpopcntq ymm30,YMMWORD PTR \[rax\+r14\*8\+0x1234\] +[ ]*[a-f0-9]+:[ ]*62 62 fd 28 55 72 7f[ ]*vpopcntq ymm30,YMMWORD PTR \[rdx\+0xfe0\] +[ ]*[a-f0-9]+:[ ]*62 62 fd 38 55 72 7f[ ]*vpopcntq ymm30,QWORD PTR \[rdx\+0x3f8\]\{1to4\} +#pass diff --git a/gas/testsuite/gas/i386/x86-64-avx512bitalg_vl.d b/gas/testsuite/gas/i386/x86-64-avx512bitalg_vl.d new file mode 100644 index 0000000..7319ded --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-avx512bitalg_vl.d @@ -0,0 +1,116 @@ +#as: +#objdump: -dw +#name: x86_64 AVX512BITALG/VL insns +#source: x86-64-avx512bitalg_vl.s + +.*: +file format .* + + +Disassembly of section \.text: + +0+ <_start>: +[ ]*[a-f0-9]+:[ ]*62 92 15 00 8f ec[ ]*vpshufbitqmb %xmm28,%xmm29,%k5 +[ ]*[a-f0-9]+:[ ]*62 92 15 07 8f ec[ ]*vpshufbitqmb %xmm28,%xmm29,%k5\{%k7\} +[ ]*[a-f0-9]+:[ ]*62 b2 15 00 8f ac f0 23 01 00 00[ ]*vpshufbitqmb 0x123\(%rax,%r14,8\),%xmm29,%k5 +[ ]*[a-f0-9]+:[ ]*62 f2 15 00 8f 6a 7f[ ]*vpshufbitqmb 0x7f0\(%rdx\),%xmm29,%k5 +[ ]*[a-f0-9]+:[ ]*62 92 15 20 8f ec[ ]*vpshufbitqmb %ymm28,%ymm29,%k5 +[ ]*[a-f0-9]+:[ ]*62 92 15 27 8f ec[ ]*vpshufbitqmb %ymm28,%ymm29,%k5\{%k7\} +[ ]*[a-f0-9]+:[ ]*62 b2 15 20 8f ac f0 23 01 00 00[ ]*vpshufbitqmb 0x123\(%rax,%r14,8\),%ymm29,%k5 +[ ]*[a-f0-9]+:[ ]*62 f2 15 20 8f 6a 7f[ ]*vpshufbitqmb 0xfe0\(%rdx\),%ymm29,%k5 +[ ]*[a-f0-9]+:[ ]*62 02 7d 08 54 f5[ ]*vpopcntb %xmm29,%xmm30 +[ ]*[a-f0-9]+:[ ]*62 02 7d 0f 54 f5[ ]*vpopcntb %xmm29,%xmm30\{%k7\} +[ ]*[a-f0-9]+:[ ]*62 02 7d 8f 54 f5[ ]*vpopcntb %xmm29,%xmm30\{%k7\}\{z\} +[ ]*[a-f0-9]+:[ ]*62 22 7d 08 54 b4 f0 23 01 00 00[ ]*vpopcntb 0x123\(%rax,%r14,8\),%xmm30 +[ ]*[a-f0-9]+:[ ]*62 62 7d 08 54 72 7f[ ]*vpopcntb 0x7f0\(%rdx\),%xmm30 +[ ]*[a-f0-9]+:[ ]*62 02 7d 28 54 f5[ ]*vpopcntb %ymm29,%ymm30 +[ ]*[a-f0-9]+:[ ]*62 02 7d 2f 54 f5[ ]*vpopcntb %ymm29,%ymm30\{%k7\} +[ ]*[a-f0-9]+:[ ]*62 02 7d af 54 f5[ ]*vpopcntb %ymm29,%ymm30\{%k7\}\{z\} +[ ]*[a-f0-9]+:[ ]*62 22 7d 28 54 b4 f0 23 01 00 00[ ]*vpopcntb 0x123\(%rax,%r14,8\),%ymm30 +[ ]*[a-f0-9]+:[ ]*62 62 7d 28 54 72 7f[ ]*vpopcntb 0xfe0\(%rdx\),%ymm30 +[ ]*[a-f0-9]+:[ ]*62 02 fd 08 54 f5[ ]*vpopcntw %xmm29,%xmm30 +[ ]*[a-f0-9]+:[ ]*62 02 fd 0f 54 f5[ ]*vpopcntw %xmm29,%xmm30\{%k7\} +[ ]*[a-f0-9]+:[ ]*62 02 fd 8f 54 f5[ ]*vpopcntw %xmm29,%xmm30\{%k7\}\{z\} +[ ]*[a-f0-9]+:[ ]*62 22 fd 08 54 b4 f0 23 01 00 00[ ]*vpopcntw 0x123\(%rax,%r14,8\),%xmm30 +[ ]*[a-f0-9]+:[ ]*62 62 fd 08 54 72 7f[ ]*vpopcntw 0x7f0\(%rdx\),%xmm30 +[ ]*[a-f0-9]+:[ ]*62 02 fd 28 54 f5[ ]*vpopcntw %ymm29,%ymm30 +[ ]*[a-f0-9]+:[ ]*62 02 fd 2f 54 f5[ ]*vpopcntw %ymm29,%ymm30\{%k7\} +[ ]*[a-f0-9]+:[ ]*62 02 fd af 54 f5[ ]*vpopcntw %ymm29,%ymm30\{%k7\}\{z\} +[ ]*[a-f0-9]+:[ ]*62 22 fd 28 54 b4 f0 23 01 00 00[ ]*vpopcntw 0x123\(%rax,%r14,8\),%ymm30 +[ ]*[a-f0-9]+:[ ]*62 62 fd 28 54 72 7f[ ]*vpopcntw 0xfe0\(%rdx\),%ymm30 +[ ]*[a-f0-9]+:[ ]*62 02 7d 08 55 f5[ ]*vpopcntd %xmm29,%xmm30 +[ ]*[a-f0-9]+:[ ]*62 02 7d 0f 55 f5[ ]*vpopcntd %xmm29,%xmm30\{%k7\} +[ ]*[a-f0-9]+:[ ]*62 02 7d 8f 55 f5[ ]*vpopcntd %xmm29,%xmm30\{%k7\}\{z\} +[ ]*[a-f0-9]+:[ ]*62 22 7d 08 55 b4 f0 23 01 00 00[ ]*vpopcntd 0x123\(%rax,%r14,8\),%xmm30 +[ ]*[a-f0-9]+:[ ]*62 62 7d 08 55 72 7f[ ]*vpopcntd 0x7f0\(%rdx\),%xmm30 +[ ]*[a-f0-9]+:[ ]*62 62 7d 18 55 72 7f[ ]*vpopcntd 0x1fc\(%rdx\)\{1to4\},%xmm30 +[ ]*[a-f0-9]+:[ ]*62 02 7d 28 55 f5[ ]*vpopcntd %ymm29,%ymm30 +[ ]*[a-f0-9]+:[ ]*62 02 7d 2f 55 f5[ ]*vpopcntd %ymm29,%ymm30\{%k7\} +[ ]*[a-f0-9]+:[ ]*62 02 7d af 55 f5[ ]*vpopcntd %ymm29,%ymm30\{%k7\}\{z\} +[ ]*[a-f0-9]+:[ ]*62 22 7d 28 55 b4 f0 23 01 00 00[ ]*vpopcntd 0x123\(%rax,%r14,8\),%ymm30 +[ ]*[a-f0-9]+:[ ]*62 62 7d 28 55 72 7f[ ]*vpopcntd 0xfe0\(%rdx\),%ymm30 +[ ]*[a-f0-9]+:[ ]*62 62 7d 38 55 72 7f[ ]*vpopcntd 0x1fc\(%rdx\)\{1to8\},%ymm30 +[ ]*[a-f0-9]+:[ ]*62 02 fd 08 55 f5[ ]*vpopcntq %xmm29,%xmm30 +[ ]*[a-f0-9]+:[ ]*62 02 fd 0f 55 f5[ ]*vpopcntq %xmm29,%xmm30\{%k7\} +[ ]*[a-f0-9]+:[ ]*62 02 fd 8f 55 f5[ ]*vpopcntq %xmm29,%xmm30\{%k7\}\{z\} +[ ]*[a-f0-9]+:[ ]*62 22 fd 08 55 b4 f0 23 01 00 00[ ]*vpopcntq 0x123\(%rax,%r14,8\),%xmm30 +[ ]*[a-f0-9]+:[ ]*62 62 fd 08 55 72 7f[ ]*vpopcntq 0x7f0\(%rdx\),%xmm30 +[ ]*[a-f0-9]+:[ ]*62 62 fd 18 55 72 7f[ ]*vpopcntq 0x3f8\(%rdx\)\{1to2\},%xmm30 +[ ]*[a-f0-9]+:[ ]*62 02 fd 28 55 f5[ ]*vpopcntq %ymm29,%ymm30 +[ ]*[a-f0-9]+:[ ]*62 02 fd 2f 55 f5[ ]*vpopcntq %ymm29,%ymm30\{%k7\} +[ ]*[a-f0-9]+:[ ]*62 02 fd af 55 f5[ ]*vpopcntq %ymm29,%ymm30\{%k7\}\{z\} +[ ]*[a-f0-9]+:[ ]*62 22 fd 28 55 b4 f0 23 01 00 00[ ]*vpopcntq 0x123\(%rax,%r14,8\),%ymm30 +[ ]*[a-f0-9]+:[ ]*62 62 fd 28 55 72 7f[ ]*vpopcntq 0xfe0\(%rdx\),%ymm30 +[ ]*[a-f0-9]+:[ ]*62 62 fd 38 55 72 7f[ ]*vpopcntq 0x3f8\(%rdx\)\{1to4\},%ymm30 +[ ]*[a-f0-9]+:[ ]*62 92 15 00 8f ec[ ]*vpshufbitqmb %xmm28,%xmm29,%k5 +[ ]*[a-f0-9]+:[ ]*62 92 15 07 8f ec[ ]*vpshufbitqmb %xmm28,%xmm29,%k5\{%k7\} +[ ]*[a-f0-9]+:[ ]*62 b2 15 00 8f ac f0 34 12 00 00[ ]*vpshufbitqmb 0x1234\(%rax,%r14,8\),%xmm29,%k5 +[ ]*[a-f0-9]+:[ ]*62 f2 15 00 8f 6a 7f[ ]*vpshufbitqmb 0x7f0\(%rdx\),%xmm29,%k5 +[ ]*[a-f0-9]+:[ ]*62 92 15 20 8f ec[ ]*vpshufbitqmb %ymm28,%ymm29,%k5 +[ ]*[a-f0-9]+:[ ]*62 92 15 27 8f ec[ ]*vpshufbitqmb %ymm28,%ymm29,%k5\{%k7\} +[ ]*[a-f0-9]+:[ ]*62 b2 15 20 8f ac f0 34 12 00 00[ ]*vpshufbitqmb 0x1234\(%rax,%r14,8\),%ymm29,%k5 +[ ]*[a-f0-9]+:[ ]*62 f2 15 20 8f 6a 7f[ ]*vpshufbitqmb 0xfe0\(%rdx\),%ymm29,%k5 +[ ]*[a-f0-9]+:[ ]*62 02 7d 08 54 f5[ ]*vpopcntb %xmm29,%xmm30 +[ ]*[a-f0-9]+:[ ]*62 02 7d 0f 54 f5[ ]*vpopcntb %xmm29,%xmm30\{%k7\} +[ ]*[a-f0-9]+:[ ]*62 02 7d 8f 54 f5[ ]*vpopcntb %xmm29,%xmm30\{%k7\}\{z\} +[ ]*[a-f0-9]+:[ ]*62 22 7d 08 54 b4 f0 34 12 00 00[ ]*vpopcntb 0x1234\(%rax,%r14,8\),%xmm30 +[ ]*[a-f0-9]+:[ ]*62 62 7d 08 54 72 7f[ ]*vpopcntb 0x7f0\(%rdx\),%xmm30 +[ ]*[a-f0-9]+:[ ]*62 02 7d 28 54 f5[ ]*vpopcntb %ymm29,%ymm30 +[ ]*[a-f0-9]+:[ ]*62 02 7d 2f 54 f5[ ]*vpopcntb %ymm29,%ymm30\{%k7\} +[ ]*[a-f0-9]+:[ ]*62 02 7d af 54 f5[ ]*vpopcntb %ymm29,%ymm30\{%k7\}\{z\} +[ ]*[a-f0-9]+:[ ]*62 22 7d 28 54 b4 f0 34 12 00 00[ ]*vpopcntb 0x1234\(%rax,%r14,8\),%ymm30 +[ ]*[a-f0-9]+:[ ]*62 62 7d 28 54 72 7f[ ]*vpopcntb 0xfe0\(%rdx\),%ymm30 +[ ]*[a-f0-9]+:[ ]*62 02 fd 08 54 f5[ ]*vpopcntw %xmm29,%xmm30 +[ ]*[a-f0-9]+:[ ]*62 02 fd 0f 54 f5[ ]*vpopcntw %xmm29,%xmm30\{%k7\} +[ ]*[a-f0-9]+:[ ]*62 02 fd 8f 54 f5[ ]*vpopcntw %xmm29,%xmm30\{%k7\}\{z\} +[ ]*[a-f0-9]+:[ ]*62 22 fd 08 54 b4 f0 34 12 00 00[ ]*vpopcntw 0x1234\(%rax,%r14,8\),%xmm30 +[ ]*[a-f0-9]+:[ ]*62 62 fd 08 54 72 7f[ ]*vpopcntw 0x7f0\(%rdx\),%xmm30 +[ ]*[a-f0-9]+:[ ]*62 02 fd 28 54 f5[ ]*vpopcntw %ymm29,%ymm30 +[ ]*[a-f0-9]+:[ ]*62 02 fd 2f 54 f5[ ]*vpopcntw %ymm29,%ymm30\{%k7\} +[ ]*[a-f0-9]+:[ ]*62 02 fd af 54 f5[ ]*vpopcntw %ymm29,%ymm30\{%k7\}\{z\} +[ ]*[a-f0-9]+:[ ]*62 22 fd 28 54 b4 f0 34 12 00 00[ ]*vpopcntw 0x1234\(%rax,%r14,8\),%ymm30 +[ ]*[a-f0-9]+:[ ]*62 62 fd 28 54 72 7f[ ]*vpopcntw 0xfe0\(%rdx\),%ymm30 +[ ]*[a-f0-9]+:[ ]*62 02 7d 08 55 f5[ ]*vpopcntd %xmm29,%xmm30 +[ ]*[a-f0-9]+:[ ]*62 02 7d 0f 55 f5[ ]*vpopcntd %xmm29,%xmm30\{%k7\} +[ ]*[a-f0-9]+:[ ]*62 02 7d 8f 55 f5[ ]*vpopcntd %xmm29,%xmm30\{%k7\}\{z\} +[ ]*[a-f0-9]+:[ ]*62 22 7d 08 55 b4 f0 34 12 00 00[ ]*vpopcntd 0x1234\(%rax,%r14,8\),%xmm30 +[ ]*[a-f0-9]+:[ ]*62 62 7d 08 55 72 7f[ ]*vpopcntd 0x7f0\(%rdx\),%xmm30 +[ ]*[a-f0-9]+:[ ]*62 62 7d 18 55 72 7f[ ]*vpopcntd 0x1fc\(%rdx\)\{1to4\},%xmm30 +[ ]*[a-f0-9]+:[ ]*62 02 7d 28 55 f5[ ]*vpopcntd %ymm29,%ymm30 +[ ]*[a-f0-9]+:[ ]*62 02 7d 2f 55 f5[ ]*vpopcntd %ymm29,%ymm30\{%k7\} +[ ]*[a-f0-9]+:[ ]*62 02 7d af 55 f5[ ]*vpopcntd %ymm29,%ymm30\{%k7\}\{z\} +[ ]*[a-f0-9]+:[ ]*62 22 7d 28 55 b4 f0 34 12 00 00[ ]*vpopcntd 0x1234\(%rax,%r14,8\),%ymm30 +[ ]*[a-f0-9]+:[ ]*62 62 7d 28 55 72 7f[ ]*vpopcntd 0xfe0\(%rdx\),%ymm30 +[ ]*[a-f0-9]+:[ ]*62 62 7d 38 55 72 7f[ ]*vpopcntd 0x1fc\(%rdx\)\{1to8\},%ymm30 +[ ]*[a-f0-9]+:[ ]*62 02 fd 08 55 f5[ ]*vpopcntq %xmm29,%xmm30 +[ ]*[a-f0-9]+:[ ]*62 02 fd 0f 55 f5[ ]*vpopcntq %xmm29,%xmm30\{%k7\} +[ ]*[a-f0-9]+:[ ]*62 02 fd 8f 55 f5[ ]*vpopcntq %xmm29,%xmm30\{%k7\}\{z\} +[ ]*[a-f0-9]+:[ ]*62 22 fd 08 55 b4 f0 34 12 00 00[ ]*vpopcntq 0x1234\(%rax,%r14,8\),%xmm30 +[ ]*[a-f0-9]+:[ ]*62 62 fd 08 55 72 7f[ ]*vpopcntq 0x7f0\(%rdx\),%xmm30 +[ ]*[a-f0-9]+:[ ]*62 62 fd 18 55 72 7f[ ]*vpopcntq 0x3f8\(%rdx\)\{1to2\},%xmm30 +[ ]*[a-f0-9]+:[ ]*62 02 fd 28 55 f5[ ]*vpopcntq %ymm29,%ymm30 +[ ]*[a-f0-9]+:[ ]*62 02 fd 2f 55 f5[ ]*vpopcntq %ymm29,%ymm30\{%k7\} +[ ]*[a-f0-9]+:[ ]*62 02 fd af 55 f5[ ]*vpopcntq %ymm29,%ymm30\{%k7\}\{z\} +[ ]*[a-f0-9]+:[ ]*62 22 fd 28 55 b4 f0 34 12 00 00[ ]*vpopcntq 0x1234\(%rax,%r14,8\),%ymm30 +[ ]*[a-f0-9]+:[ ]*62 62 fd 28 55 72 7f[ ]*vpopcntq 0xfe0\(%rdx\),%ymm30 +[ ]*[a-f0-9]+:[ ]*62 62 fd 38 55 72 7f[ ]*vpopcntq 0x3f8\(%rdx\)\{1to4\},%ymm30 +#pass diff --git a/gas/testsuite/gas/i386/x86-64-avx512bitalg_vl.s b/gas/testsuite/gas/i386/x86-64-avx512bitalg_vl.s new file mode 100644 index 0000000..9425ad5 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-avx512bitalg_vl.s @@ -0,0 +1,119 @@ +# Check 64bit AVX512{BITALG,VL} instructions + + .allow_index_reg + .text +_start: + vpshufbitqmb %xmm28, %xmm29, %k5 # AVX512{BITALG,VL} + vpshufbitqmb %xmm28, %xmm29, %k5{%k7} # AVX512{BITALG,VL} + vpshufbitqmb 0x123(%rax,%r14,8), %xmm29, %k5 # AVX512{BITALG,VL} + vpshufbitqmb 2032(%rdx), %xmm29, %k5 # AVX512{BITALG,VL} Disp8 + vpshufbitqmb %ymm28, %ymm29, %k5 # AVX512{BITALG,VL} + vpshufbitqmb %ymm28, %ymm29, %k5{%k7} # AVX512{BITALG,VL} + vpshufbitqmb 0x123(%rax,%r14,8), %ymm29, %k5 # AVX512{BITALG,VL} + vpshufbitqmb 4064(%rdx), %ymm29, %k5 # AVX512{BITALG,VL} Disp8 + + vpopcntb %xmm29, %xmm30 # AVX512{BITALG,VL} + vpopcntb %xmm29, %xmm30{%k7} # AVX512{BITALG,VL} + vpopcntb %xmm29, %xmm30{%k7}{z} # AVX512{BITALG,VL} + vpopcntb 0x123(%rax,%r14,8), %xmm30 # AVX512{BITALG,VL} + vpopcntb 2032(%rdx), %xmm30 # AVX512{BITALG,VL} Disp8 + vpopcntb %ymm29, %ymm30 # AVX512{BITALG,VL} + vpopcntb %ymm29, %ymm30{%k7} # AVX512{BITALG,VL} + vpopcntb %ymm29, %ymm30{%k7}{z} # AVX512{BITALG,VL} + vpopcntb 0x123(%rax,%r14,8), %ymm30 # AVX512{BITALG,VL} + vpopcntb 4064(%rdx), %ymm30 # AVX512{BITALG,VL} Disp8 + + vpopcntw %xmm29, %xmm30 # AVX512{BITALG,VL} + vpopcntw %xmm29, %xmm30{%k7} # AVX512{BITALG,VL} + vpopcntw %xmm29, %xmm30{%k7}{z} # AVX512{BITALG,VL} + vpopcntw 0x123(%rax,%r14,8), %xmm30 # AVX512{BITALG,VL} + vpopcntw 2032(%rdx), %xmm30 # AVX512{BITALG,VL} Disp8 + vpopcntw %ymm29, %ymm30 # AVX512{BITALG,VL} + vpopcntw %ymm29, %ymm30{%k7} # AVX512{BITALG,VL} + vpopcntw %ymm29, %ymm30{%k7}{z} # AVX512{BITALG,VL} + vpopcntw 0x123(%rax,%r14,8), %ymm30 # AVX512{BITALG,VL} + vpopcntw 4064(%rdx), %ymm30 # AVX512{BITALG,VL} Disp8 + + vpopcntd %xmm29, %xmm30 # AVX512{BITALG,VL} + vpopcntd %xmm29, %xmm30{%k7} # AVX512{BITALG,VL} + vpopcntd %xmm29, %xmm30{%k7}{z} # AVX512{BITALG,VL} + vpopcntd 0x123(%rax,%r14,8), %xmm30 # AVX512{BITALG,VL} + vpopcntd 2032(%rdx), %xmm30 # AVX512{BITALG,VL} Disp8 + vpopcntd 508(%rdx){1to4}, %xmm30 # AVX512{BITALG,VL} Disp8 + vpopcntd %ymm29, %ymm30 # AVX512{BITALG,VL} + vpopcntd %ymm29, %ymm30{%k7} # AVX512{BITALG,VL} + vpopcntd %ymm29, %ymm30{%k7}{z} # AVX512{BITALG,VL} + vpopcntd 0x123(%rax,%r14,8), %ymm30 # AVX512{BITALG,VL} + vpopcntd 4064(%rdx), %ymm30 # AVX512{BITALG,VL} Disp8 + vpopcntd 508(%rdx){1to8}, %ymm30 # AVX512{BITALG,VL} Disp8 + + vpopcntq %xmm29, %xmm30 # AVX512{BITALG,VL} + vpopcntq %xmm29, %xmm30{%k7} # AVX512{BITALG,VL} + vpopcntq %xmm29, %xmm30{%k7}{z} # AVX512{BITALG,VL} + vpopcntq 0x123(%rax,%r14,8), %xmm30 # AVX512{BITALG,VL} + vpopcntq 2032(%rdx), %xmm30 # AVX512{BITALG,VL} Disp8 + vpopcntq 1016(%rdx){1to2}, %xmm30 # AVX512{BITALG,VL} Disp8 + vpopcntq %ymm29, %ymm30 # AVX512{BITALG,VL} + vpopcntq %ymm29, %ymm30{%k7} # AVX512{BITALG,VL} + vpopcntq %ymm29, %ymm30{%k7}{z} # AVX512{BITALG,VL} + vpopcntq 0x123(%rax,%r14,8), %ymm30 # AVX512{BITALG,VL} + vpopcntq 4064(%rdx), %ymm30 # AVX512{BITALG,VL} Disp8 + vpopcntq 1016(%rdx){1to4}, %ymm30 # AVX512{BITALG,VL} Disp8 + + .intel_syntax noprefix + vpshufbitqmb k5, xmm29, xmm28 # AVX512{BITALG,VL} + vpshufbitqmb k5{k7}, xmm29, xmm28 # AVX512{BITALG,VL} + vpshufbitqmb k5, xmm29, XMMWORD PTR [rax+r14*8+0x1234] # AVX512{BITALG,VL} + vpshufbitqmb k5, xmm29, XMMWORD PTR [rdx+2032] # AVX512{BITALG,VL} Disp8 + vpshufbitqmb k5, ymm29, ymm28 # AVX512{BITALG,VL} + vpshufbitqmb k5{k7}, ymm29, ymm28 # AVX512{BITALG,VL} + vpshufbitqmb k5, ymm29, YMMWORD PTR [rax+r14*8+0x1234] # AVX512{BITALG,VL} + vpshufbitqmb k5, ymm29, YMMWORD PTR [rdx+4064] # AVX512{BITALG,VL} Disp8 + + vpopcntb xmm30, xmm29 # AVX512{BITALG,VL} + vpopcntb xmm30{k7}, xmm29 # AVX512{BITALG,VL} + vpopcntb xmm30{k7}{z}, xmm29 # AVX512{BITALG,VL} + vpopcntb xmm30, XMMWORD PTR [rax+r14*8+0x1234] # AVX512{BITALG,VL} + vpopcntb xmm30, XMMWORD PTR [rdx+2032] # AVX512{BITALG,VL} Disp8 + vpopcntb ymm30, ymm29 # AVX512{BITALG,VL} + vpopcntb ymm30{k7}, ymm29 # AVX512{BITALG,VL} + vpopcntb ymm30{k7}{z}, ymm29 # AVX512{BITALG,VL} + vpopcntb ymm30, YMMWORD PTR [rax+r14*8+0x1234] # AVX512{BITALG,VL} + vpopcntb ymm30, YMMWORD PTR [rdx+4064] # AVX512{BITALG,VL} Disp8 + + vpopcntw xmm30, xmm29 # AVX512{BITALG,VL} + vpopcntw xmm30{k7}, xmm29 # AVX512{BITALG,VL} + vpopcntw xmm30{k7}{z}, xmm29 # AVX512{BITALG,VL} + vpopcntw xmm30, XMMWORD PTR [rax+r14*8+0x1234] # AVX512{BITALG,VL} + vpopcntw xmm30, XMMWORD PTR [rdx+2032] # AVX512{BITALG,VL} Disp8 + vpopcntw ymm30, ymm29 # AVX512{BITALG,VL} + vpopcntw ymm30{k7}, ymm29 # AVX512{BITALG,VL} + vpopcntw ymm30{k7}{z}, ymm29 # AVX512{BITALG,VL} + vpopcntw ymm30, YMMWORD PTR [rax+r14*8+0x1234] # AVX512{BITALG,VL} + vpopcntw ymm30, YMMWORD PTR [rdx+4064] # AVX512{BITALG,VL} Disp8 + + vpopcntd xmm30, xmm29 # AVX512{BITALG,VL} + vpopcntd xmm30{k7}, xmm29 # AVX512{BITALG,VL} + vpopcntd xmm30{k7}{z}, xmm29 # AVX512{BITALG,VL} + vpopcntd xmm30, XMMWORD PTR [rax+r14*8+0x1234] # AVX512{BITALG,VL} + vpopcntd xmm30, XMMWORD PTR [rdx+2032] # AVX512{BITALG,VL} Disp8 + vpopcntd xmm30, [rdx+508]{1to4} # AVX512{BITALG,VL} Disp8 + vpopcntd ymm30, ymm29 # AVX512{BITALG,VL} + vpopcntd ymm30{k7}, ymm29 # AVX512{BITALG,VL} + vpopcntd ymm30{k7}{z}, ymm29 # AVX512{BITALG,VL} + vpopcntd ymm30, YMMWORD PTR [rax+r14*8+0x1234] # AVX512{BITALG,VL} + vpopcntd ymm30, YMMWORD PTR [rdx+4064] # AVX512{BITALG,VL} Disp8 + vpopcntd ymm30, [rdx+508]{1to8} # AVX512{BITALG,VL} Disp8 + + vpopcntq xmm30, xmm29 # AVX512{BITALG,VL} + vpopcntq xmm30{k7}, xmm29 # AVX512{BITALG,VL} + vpopcntq xmm30{k7}{z}, xmm29 # AVX512{BITALG,VL} + vpopcntq xmm30, XMMWORD PTR [rax+r14*8+0x1234] # AVX512{BITALG,VL} + vpopcntq xmm30, XMMWORD PTR [rdx+2032] # AVX512{BITALG,VL} Disp8 + vpopcntq xmm30, [rdx+1016]{1to2} # AVX512{BITALG,VL} Disp8 + vpopcntq ymm30, ymm29 # AVX512{BITALG,VL} + vpopcntq ymm30{k7}, ymm29 # AVX512{BITALG,VL} + vpopcntq ymm30{k7}{z}, ymm29 # AVX512{BITALG,VL} + vpopcntq ymm30, YMMWORD PTR [rax+r14*8+0x1234] # AVX512{BITALG,VL} + vpopcntq ymm30, YMMWORD PTR [rdx+4064] # AVX512{BITALG,VL} Disp8 + vpopcntq ymm30, [rdx+1016]{1to4} # AVX512{BITALG,VL} Disp8 diff --git a/opcodes/i386-dis-evex.h b/opcodes/i386-dis-evex.h index 467a2d3..9e062d0 100644 --- a/opcodes/i386-dis-evex.h +++ b/opcodes/i386-dis-evex.h @@ -389,7 +389,7 @@ static const struct dis386 evex_table[][256] = { { PREFIX_TABLE (PREFIX_EVEX_0F3851) }, { PREFIX_TABLE (PREFIX_EVEX_0F3852) }, { PREFIX_TABLE (PREFIX_EVEX_0F3853) }, - { Bad_Opcode }, + { PREFIX_TABLE (PREFIX_EVEX_0F3854) }, { PREFIX_TABLE (PREFIX_EVEX_0F3855) }, { Bad_Opcode }, { Bad_Opcode }, @@ -455,7 +455,7 @@ static const struct dis386 evex_table[][256] = { { Bad_Opcode }, { PREFIX_TABLE (PREFIX_EVEX_0F388D) }, { Bad_Opcode }, - { Bad_Opcode }, + { PREFIX_TABLE (PREFIX_EVEX_0F388F) }, /* 90 */ { PREFIX_TABLE (PREFIX_EVEX_0F3890) }, { PREFIX_TABLE (PREFIX_EVEX_0F3891) }, @@ -2031,6 +2031,12 @@ static const struct dis386 evex_table[][256] = { { "vpdpwssds", { XM, Vex, EXx }, 0 }, { "vp4dpwssds", { XM, Vex, EXxmm }, 0 }, }, + /* PREFIX_EVEX_0F3854 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_W_TABLE (EVEX_W_0F3854_P_2) }, + }, /* PREFIX_EVEX_0F3855 */ { { Bad_Opcode }, @@ -2217,6 +2223,12 @@ static const struct dis386 evex_table[][256] = { { Bad_Opcode }, { VEX_W_TABLE (EVEX_W_0F388D_P_2) }, }, + /* PREFIX_EVEX_0F388F */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { "vpshufbitqmb", { XMask, Vex, EXx }, 0 }, + }, /* PREFIX_EVEX_0F3890 */ { { Bad_Opcode }, @@ -3703,6 +3715,11 @@ static const struct dis386 evex_table[][256] = { { "vpmulld", { XM, Vex, EXx }, 0 }, { "vpmullq", { XM, Vex, EXx }, 0 }, }, + /* EVEX_W_0F3854_P_2 */ + { + { "vpopcntb", { XM, EXx }, 0 }, + { "vpopcntw", { XM, EXx }, 0 }, + }, /* EVEX_W_0F3855_P_2 */ { { "vpopcntd", { XM, EXx }, 0 }, diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c index 637fce3..1734be8 100644 --- a/opcodes/i386-dis.c +++ b/opcodes/i386-dis.c @@ -1576,6 +1576,7 @@ enum PREFIX_EVEX_0F3851, PREFIX_EVEX_0F3852, PREFIX_EVEX_0F3853, + PREFIX_EVEX_0F3854, PREFIX_EVEX_0F3855, PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3859, @@ -1607,6 +1608,7 @@ enum PREFIX_EVEX_0F388A, PREFIX_EVEX_0F388B, PREFIX_EVEX_0F388D, + PREFIX_EVEX_0F388F, PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891, PREFIX_EVEX_0F3892, @@ -2415,6 +2417,7 @@ enum EVEX_W_0F3839_P_1, EVEX_W_0F383A_P_1, EVEX_W_0F3840_P_2, + EVEX_W_0F3854_P_2, EVEX_W_0F3855_P_2, EVEX_W_0F3858_P_2, EVEX_W_0F3859_P_2, diff --git a/opcodes/i386-gen.c b/opcodes/i386-gen.c index 1202376..b3694e7 100644 --- a/opcodes/i386-gen.c +++ b/opcodes/i386-gen.c @@ -227,6 +227,8 @@ static initializer cpu_flag_init[] = "CPU_AVX512F_FLAGS|CpuAVX512_VBMI2" }, { "CPU_AVX512_VNNI_FLAGS", "CPU_AVX512F_FLAGS|CpuAVX512_VNNI" }, + { "CPU_AVX512_BITALG_FLAGS", + "CPU_AVX512F_FLAGS|CpuAVX512_BITALG" }, { "CPU_L1OM_FLAGS", "unknown" }, { "CPU_K1OM_FLAGS", @@ -302,7 +304,7 @@ static initializer cpu_flag_init[] = { "CPU_ANY_AVX2_FLAGS", "CpuAVX2" }, { "CPU_ANY_AVX512F_FLAGS", - "CpuVREX|CpuRegZMM|CpuRegMask|CpuAVX512CD|CpuAVX512ER|CpuAVX512PF|CpuAVX512DQ|CpuAVX512BW|CpuAVX512VL|CpuAVX512IFMA|CpuAVX512VBMI|CpuAVX512_4FMAPS|CpuAVX512_4VNNIW|CpuAVX512_VPOPCNTDQ|CpuAVX512_VBMI2|CpuAVX512_VNNI|CpuAVX512F" }, + "CpuVREX|CpuRegZMM|CpuRegMask|CpuAVX512CD|CpuAVX512ER|CpuAVX512PF|CpuAVX512DQ|CpuAVX512BW|CpuAVX512VL|CpuAVX512IFMA|CpuAVX512VBMI|CpuAVX512_4FMAPS|CpuAVX512_4VNNIW|CpuAVX512_VPOPCNTDQ|CpuAVX512_VBMI2|CpuAVX512_VNNI|CpuAVX512_BITALG|CpuAVX512F" }, { "CPU_ANY_AVX512CD_FLAGS", "CpuAVX512CD" }, { "CPU_ANY_AVX512ER_FLAGS", @@ -329,6 +331,8 @@ static initializer cpu_flag_init[] = "CpuAVX512_VBMI2" }, { "CPU_ANY_AVX512_VNNI_FLAGS", "CpuAVX512_VNNI" }, + { "CPU_ANY_AVX512_BITALG_FLAGS", + "CpuAVX512_BITALG" }, }; static initializer operand_type_init[] = @@ -537,6 +541,7 @@ static bitfield cpu_flags[] = BITFIELD (CpuAVX512_VPOPCNTDQ), BITFIELD (CpuAVX512_VBMI2), BITFIELD (CpuAVX512_VNNI), + BITFIELD (CpuAVX512_BITALG), BITFIELD (CpuMWAITX), BITFIELD (CpuCLZERO), BITFIELD (CpuOSPKE), diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h index 34b57f5..5c29bdb 100644 --- a/opcodes/i386-opc.h +++ b/opcodes/i386-opc.h @@ -202,6 +202,8 @@ enum CpuAVX512_VBMI2, /* Intel AVX-512 VNNI Instructions support required. */ CpuAVX512_VNNI, + /* Intel AVX-512 BITALG Instructions support required. */ + CpuAVX512_BITALG, /* mwaitx instruction required */ CpuMWAITX, /* Clzero instruction required */ @@ -338,6 +340,7 @@ typedef union i386_cpu_flags unsigned int cpuavx512_vpopcntdq:1; unsigned int cpuavx512_vbmi2:1; unsigned int cpuavx512_vnni:1; + unsigned int cpuavx512_bitalg:1; unsigned int cpumwaitx:1; unsigned int cpuclzero:1; unsigned int cpuospke:1; diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl index 6b7dea7..b74dfe5 100644 --- a/opcodes/i386-opc.tbl +++ b/opcodes/i386-opc.tbl @@ -5996,8 +5996,12 @@ vp4dpwssds, 3, 0xf253, None, 1, CpuAVX512_4VNNIW|CpuAVX512VL, Modrm|EVex=3|Maski // AVX512_VPOPCNTDQ instructions vpopcntd, 2, 0x6655, None, 1, CpuAVX512_VPOPCNTDQ, Modrm|EVex=1|Masking=3|VexOpcode=1|VexW=1|Broadcast=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM|ZMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegZMM } +vpopcntd, 2, 0x6655, None, 1, CpuAVX512_VPOPCNTDQ|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=1|VexW=1|Broadcast=3|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM } +vpopcntd, 2, 0x6655, None, 1, CpuAVX512_VPOPCNTDQ|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VexW=1|Broadcast=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM } vpopcntq, 2, 0x6655, None, 1, CpuAVX512_VPOPCNTDQ, Modrm|EVex=1|Masking=3|VexOpcode=1|VexW=2|VecESize=1|Broadcast=2|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM|Qword|ZMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegZMM } +vpopcntq, 2, 0x6655, None, 1, CpuAVX512_VPOPCNTDQ|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=1|VexW=2|VecESize=1|Broadcast=4|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM } +vpopcntq, 2, 0x6655, None, 1, CpuAVX512_VPOPCNTDQ|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VexW=2|VecESize=1|Broadcast=3|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Qword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM } // AVX512_VPOPCNTDQ instructions end @@ -6095,6 +6099,22 @@ vpdpwssds, 3, 0x6653, None, 1, CpuAVX512_VNNI|CpuAVX512VL, Modrm|EVex=3|Masking= // AVX512_VNNI instructions end +// AVX512_BITALG instructions + +vpopcntb, 2, 0x6654, None, 1, CpuAVX512_BITALG, Modrm|EVex=1|Masking=3|VexOpcode=1|VexW=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM|ZMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegZMM } +vpopcntb, 2, 0x6654, None, 1, CpuAVX512_BITALG|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=1|VexW=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM } +vpopcntb, 2, 0x6654, None, 1, CpuAVX512_BITALG|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VexW=1|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM } + +vpopcntw, 2, 0x6654, None, 1, CpuAVX512_BITALG, Modrm|EVex=1|Masking=3|VexOpcode=1|VexW=2|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM|ZMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegZMM } +vpopcntw, 2, 0x6654, None, 1, CpuAVX512_BITALG|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=1|VexW=2|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM } +vpopcntw, 2, 0x6654, None, 1, CpuAVX512_BITALG|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VexW=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM } + +vpshufbitqmb, 3, 0x668f, None, 1, CpuAVX512_BITALG, Modrm|EVex=1|Masking=2|VexOpcode=1|VexVVVV=1|VexW=1|VecESize=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM|ZMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegZMM, RegMask } +vpshufbitqmb, 3, 0x668f, None, 1, CpuAVX512_BITALG|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=1|VexVVVV=1|VexW=1|VecESize=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask } +vpshufbitqmb, 3, 0x668f, None, 1, CpuAVX512_BITALG|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=1|VexVVVV=1|VexW=1|VecESize=1|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask } + +// AVX512_BITALG instructions end + // AVX512 + GFNI instructions vgf2p8affineinvqb, 4, 0x66cf, None, 1, CpuAVX512F|CpuGFNI, Modrm|EVex=1|Masking=3|VexOpcode=2|VexVVVV=1|VexW=2|VecESize=1|Broadcast=2|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegZMM|Qword|ZMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegZMM, RegZMM } -- 2.7.4