From ee3aef93b73646ef98f0241498d807a4fb68b78c Mon Sep 17 00:00:00 2001 From: Hsiangkai Wang Date: Fri, 23 Jul 2021 11:26:58 +0800 Subject: [PATCH] [RISCV][Docs] Add description about inline asm constraint for V. Add inline asm constraint 'vr' for vector registers and 'vm' for vector mask registers. Differential Revision: https://reviews.llvm.org/D106633 --- llvm/docs/LangRef.rst | 2 ++ 1 file changed, 2 insertions(+) diff --git a/llvm/docs/LangRef.rst b/llvm/docs/LangRef.rst index d5e4e59..d91464a 100644 --- a/llvm/docs/LangRef.rst +++ b/llvm/docs/LangRef.rst @@ -4779,6 +4779,8 @@ RISC-V: - ``f``: A 32- or 64-bit floating-point register (requires F or D extension). - ``r``: A 32- or 64-bit general-purpose register (depending on the platform ``XLEN``). +- ``vr``: A vector register. (requires V extension). +- ``vm``: A vector mask register. (requires V extension). Sparc: -- 2.7.4