From ee0ea1d0dda935aa13e6562ee32d37d441b43490 Mon Sep 17 00:00:00 2001 From: bellard Date: Sun, 24 Sep 2006 18:49:13 +0000 Subject: [PATCH] moved PCI init to BIOS - added ISA memory mapping registers and SMM support git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2174 c046a42c-6fe2-441c-8c8c-71466251a162 --- hw/piix_pci.c | 348 +++++++++++++++++++++------------------------------------- 1 file changed, 123 insertions(+), 225 deletions(-) diff --git a/hw/piix_pci.c b/hw/piix_pci.c index d618f00..43f2da2 100644 --- a/hw/piix_pci.c +++ b/hw/piix_pci.c @@ -52,7 +52,123 @@ static int pci_slot_get_pirq(PCIDevice *pci_dev, int irq_num) return (irq_num + slot_addend) & 3; } -PCIBus *i440fx_init(void) +static uint32_t isa_page_descs[384 / 4]; +static uint8_t smm_enabled; + +static const uint32_t mar_addresses[15] = { + 0xa0000, + 0xc0000, + 0xc4000, + 0xc8000, + 0xcc000, + 0xd0000, + 0xd4000, + 0xd8000, + 0xdc000, + 0xe0000, + 0xe4000, + 0xe8000, + 0xec000, + 0xf0000, + 0x100000, +}; + +static void i440fx_update_memory_mappings(PCIDevice *d) +{ + int i, r; + uint32_t start, end, addr; + uint32_t smram, smbase, smsize; + + for(i = 0; i < 14; i++) { + r = (d->config[(i >> 1) + 0x61] >> ((i & 1) * 4)) & 3; + start = mar_addresses[i]; + end = mar_addresses[i + 1]; + // printf("ISA mapping %08x: %d\n", start, r); + switch(r) { + case 3: + /* RAM */ + cpu_register_physical_memory(start, end - start, + start); + break; + case 2: + /* ROM (XXX: not quite correct) */ + cpu_register_physical_memory(start, end - start, + start | IO_MEM_ROM); + break; + case 1: + case 0: + /* XXX: should distinguish read/write cases */ + for(addr = start; addr < end; addr += 4096) { + cpu_register_physical_memory(addr, 4096, + isa_page_descs[(addr - 0xa0000) >> 12]); + } + break; + } + } + smram = le32_to_cpu(*(uint32_t *)(d->config + 0x6c)); + if ((smm_enabled && (smram & 0x80000000)) || (smram & (1 << 26))) { + /* Note: we assume the SMM area is in the 0xa0000-0x100000 range */ + smbase = (smram & 0xffff) << 16; + smsize = (((smram >> 20) & 0xf) + 1) << 16; + if (smbase >= 0xa0000 && (smbase + smsize) <= 0x100000) { + cpu_register_physical_memory(smbase, smsize, smbase); + } + } +} + +void i440fx_set_smm(PCIDevice *d, int val) +{ + val = (val != 0); + if (smm_enabled != val) { + smm_enabled = val; + i440fx_update_memory_mappings(d); + } +} + + +/* XXX: suppress when better memory API. We make the assumption that + no device (in particular the VGA) changes the memory mappings in + the 0xa0000-0x100000 range */ +void i440fx_init_memory_mappings(PCIDevice *d) +{ + int i; + for(i = 0; i < 96; i++) { + isa_page_descs[i] = cpu_get_physical_page_desc(0xa0000 + i * 0x1000); + } +} + +static void i440fx_write_config(PCIDevice *d, + uint32_t address, uint32_t val, int len) +{ + /* XXX: implement SMRAM.D_LOCK */ + pci_default_write_config(d, address, val, len); + if ((address >= 0x61 && address <= 0x67) || address == 0x6c) + i440fx_update_memory_mappings(d); +} + +static void i440fx_save(QEMUFile* f, void *opaque) +{ + PCIDevice *d = opaque; + pci_device_save(d, f); + qemu_put_8s(f, &smm_enabled); +} + +static int i440fx_load(QEMUFile* f, void *opaque, int version_id) +{ + PCIDevice *d = opaque; + int ret; + + if (version_id != 1) + return -EINVAL; + ret = pci_device_load(d, f); + if (ret < 0) + return ret; + i440fx_update_memory_mappings(d); + qemu_get_8s(f, &smm_enabled); + return 0; +} + +PCIBus *i440fx_init(PCIDevice **pi440fx_state) { PCIBus *b; PCIDevice *d; @@ -73,7 +189,7 @@ PCIBus *i440fx_init(void) register_ioport_read(0xcfc, 4, 4, pci_host_data_readl, s); d = pci_register_device(b, "i440FX", sizeof(PCIDevice), 0, - NULL, NULL); + NULL, i440fx_write_config); d->config[0x00] = 0x86; // vendor_id d->config[0x01] = 0x80; @@ -83,6 +199,11 @@ PCIBus *i440fx_init(void) d->config[0x0a] = 0x00; // class_sub = host2pci d->config[0x0b] = 0x06; // class_base = PCI_bridge d->config[0x0e] = 0x00; // header_type + + d->config[0x6c] = 0x0a; /* SMRAM */ + + register_savevm("I440FX", 0, 1, i440fx_save, i440fx_load, d); + *pi440fx_state = d; return b; } @@ -188,226 +309,3 @@ int piix3_init(PCIBus *bus) piix3_reset(d); return d->devfn; } - -/***********************************************************/ -/* XXX: the following should be moved to the PC BIOS */ - -static __attribute__((unused)) uint32_t isa_inb(uint32_t addr) -{ - return cpu_inb(NULL, addr); -} - -static void isa_outb(uint32_t val, uint32_t addr) -{ - cpu_outb(NULL, addr, val); -} - -static __attribute__((unused)) uint32_t isa_inw(uint32_t addr) -{ - return cpu_inw(NULL, addr); -} - -static __attribute__((unused)) void isa_outw(uint32_t val, uint32_t addr) -{ - cpu_outw(NULL, addr, val); -} - -static __attribute__((unused)) uint32_t isa_inl(uint32_t addr) -{ - return cpu_inl(NULL, addr); -} - -static __attribute__((unused)) void isa_outl(uint32_t val, uint32_t addr) -{ - cpu_outl(NULL, addr, val); -} - -static uint32_t pci_bios_io_addr; -static uint32_t pci_bios_mem_addr; -/* host irqs corresponding to PCI irqs A-D */ -static uint8_t pci_irqs[4] = { 11, 9, 11, 9 }; -static int pci_bios_next_bus; - -static void pci_config_writel(PCIDevice *d, uint32_t addr, uint32_t val) -{ - PCIBus *s = d->bus; - addr |= (pci_bus_num(s) << 16) | (d->devfn << 8); - pci_data_write(s, addr, val, 4); -} - -static void pci_config_writew(PCIDevice *d, uint32_t addr, uint32_t val) -{ - PCIBus *s = d->bus; - addr |= (pci_bus_num(s) << 16) | (d->devfn << 8); - pci_data_write(s, addr, val, 2); -} - -static void pci_config_writeb(PCIDevice *d, uint32_t addr, uint32_t val) -{ - PCIBus *s = d->bus; - addr |= (pci_bus_num(s) << 16) | (d->devfn << 8); - pci_data_write(s, addr, val, 1); -} - -static __attribute__((unused)) uint32_t pci_config_readl(PCIDevice *d, uint32_t addr) -{ - PCIBus *s = d->bus; - addr |= (pci_bus_num(s) << 16) | (d->devfn << 8); - return pci_data_read(s, addr, 4); -} - -static uint32_t pci_config_readw(PCIDevice *d, uint32_t addr) -{ - PCIBus *s = d->bus; - addr |= (pci_bus_num(s) << 16) | (d->devfn << 8); - return pci_data_read(s, addr, 2); -} - -static uint32_t pci_config_readb(PCIDevice *d, uint32_t addr) -{ - PCIBus *s = d->bus; - addr |= (pci_bus_num(s) << 16) | (d->devfn << 8); - return pci_data_read(s, addr, 1); -} - -static void pci_set_io_region_addr(PCIDevice *d, int region_num, uint32_t addr) -{ - PCIIORegion *r; - uint16_t cmd; - uint32_t ofs; - - if ( region_num == PCI_ROM_SLOT ) { - ofs = 0x30; - }else{ - ofs = 0x10 + region_num * 4; - } - - pci_config_writel(d, ofs, addr); - r = &d->io_regions[region_num]; - - /* enable memory mappings */ - cmd = pci_config_readw(d, PCI_COMMAND); - if ( region_num == PCI_ROM_SLOT ) - cmd |= 2; - else if (r->type & PCI_ADDRESS_SPACE_IO) - cmd |= 1; - else - cmd |= 2; - pci_config_writew(d, PCI_COMMAND, cmd); -} - -static void pci_bios_init_device(PCIDevice *d) -{ - int class; - PCIIORegion *r; - uint32_t *paddr; - int i, pin, pic_irq, vendor_id, device_id; - - class = pci_config_readw(d, PCI_CLASS_DEVICE); - vendor_id = pci_config_readw(d, PCI_VENDOR_ID); - device_id = pci_config_readw(d, PCI_DEVICE_ID); - switch(class) { - case 0x0101: - if (vendor_id == 0x8086 && device_id == 0x7010) { - /* PIIX3 IDE */ - pci_config_writew(d, 0x40, 0x8000); // enable IDE0 - pci_config_writew(d, 0x42, 0x8000); // enable IDE1 - goto default_map; - } else { - /* IDE: we map it as in ISA mode */ - pci_set_io_region_addr(d, 0, 0x1f0); - pci_set_io_region_addr(d, 1, 0x3f4); - pci_set_io_region_addr(d, 2, 0x170); - pci_set_io_region_addr(d, 3, 0x374); - } - break; - case 0x0604: - /* PCI to PCI bridge. Assign bus ID and recurse to configure - devices on the secondary bus. */ - i = pci_bios_next_bus++; - pci_config_writeb(d, 0x18, pci_bus_num(d->bus)); - pci_config_writeb(d, 0x19, i); - pci_for_each_device(i, pci_bios_init_device); - break; - case 0x0300: - if (vendor_id != 0x1234) - goto default_map; - /* VGA: map frame buffer to default Bochs VBE address */ - pci_set_io_region_addr(d, 0, 0xE0000000); - break; - case 0x0800: - /* PIC */ - vendor_id = pci_config_readw(d, PCI_VENDOR_ID); - device_id = pci_config_readw(d, PCI_DEVICE_ID); - if (vendor_id == 0x1014) { - /* IBM */ - if (device_id == 0x0046 || device_id == 0xFFFF) { - /* MPIC & MPIC2 */ - pci_set_io_region_addr(d, 0, 0x80800000 + 0x00040000); - } - } - break; - case 0xff00: - if (vendor_id == 0x0106b && - (device_id == 0x0017 || device_id == 0x0022)) { - /* macio bridge */ - pci_set_io_region_addr(d, 0, 0x80800000); - } - break; - default: - default_map: - /* default memory mappings */ - for(i = 0; i < PCI_NUM_REGIONS; i++) { - r = &d->io_regions[i]; - if (r->size) { - if (r->type & PCI_ADDRESS_SPACE_IO) - paddr = &pci_bios_io_addr; - else - paddr = &pci_bios_mem_addr; - *paddr = (*paddr + r->size - 1) & ~(r->size - 1); - pci_set_io_region_addr(d, i, *paddr); - *paddr += r->size; - } - } - break; - } - - /* map the interrupt */ - pin = pci_config_readb(d, PCI_INTERRUPT_PIN); - if (pin != 0) { - pin = pci_slot_get_pirq(d, pin - 1); - pic_irq = pci_irqs[pin]; - pci_config_writeb(d, PCI_INTERRUPT_LINE, pic_irq); - } -} - -/* - * This function initializes the PCI devices as a normal PCI BIOS - * would do. It is provided just in case the BIOS has no support for - * PCI. - */ -void pci_bios_init(void) -{ - int i, irq; - uint8_t elcr[2]; - - pci_bios_io_addr = 0xc000; - pci_bios_mem_addr = 0xf0000000; - - /* activate IRQ mappings */ - elcr[0] = 0x00; - elcr[1] = 0x00; - for(i = 0; i < 4; i++) { - irq = pci_irqs[i]; - /* set to trigger level */ - elcr[irq >> 3] |= (1 << (irq & 7)); - /* activate irq remapping in PIIX */ - pci_config_writeb(piix3_dev, 0x60 + i, irq); - } - isa_outb(elcr[0], 0x4d0); - isa_outb(elcr[1], 0x4d1); - - pci_bios_next_bus = 1; - pci_for_each_device(0, pci_bios_init_device); -} - -- 2.7.4