From ee0dee7d38474d7e35e5d24722e3b90068dbf8a0 Mon Sep 17 00:00:00 2001 From: Simon Pilgrim Date: Sat, 20 Feb 2021 12:17:46 +0000 Subject: [PATCH] [X86][SSE] Use llvm min/max intrinsics instead of (deprecated) sse intrinsics. NFCI. These are auto-upgraded to the equivalent llvm variants now. --- llvm/test/CodeGen/X86/2007-06-28-X86-64-isel.ll | 4 ++-- llvm/test/CodeGen/X86/2011-12-06-AVXVectorExtractCombine.ll | 4 ++-- llvm/test/CodeGen/X86/pr14161.ll | 6 +++--- 3 files changed, 7 insertions(+), 7 deletions(-) diff --git a/llvm/test/CodeGen/X86/2007-06-28-X86-64-isel.ll b/llvm/test/CodeGen/X86/2007-06-28-X86-64-isel.ll index 3c0782e..fa62d0f5 100644 --- a/llvm/test/CodeGen/X86/2007-06-28-X86-64-isel.ll +++ b/llvm/test/CodeGen/X86/2007-06-28-X86-64-isel.ll @@ -5,7 +5,7 @@ define void @test() { ; CHECK-LABEL: test: ; CHECK: # %bb.0: # %bb2 ; CHECK-NEXT: retq - %tmp1 = call <8 x i16> @llvm.x86.sse2.pmins.w( <8 x i16> zeroinitializer, <8 x i16> bitcast (<4 x i32> < i32 7, i32 7, i32 7, i32 7 > to <8 x i16>) ) + %tmp1 = call <8 x i16> @llvm.smin.v8i16( <8 x i16> zeroinitializer, <8 x i16> bitcast (<4 x i32> < i32 7, i32 7, i32 7, i32 7 > to <8 x i16>) ) %tmp2 = bitcast <8 x i16> %tmp1 to <4 x i32> br i1 false, label %bb1, label %bb2 @@ -17,4 +17,4 @@ bb1: ret void } -declare <8 x i16> @llvm.x86.sse2.pmins.w(<8 x i16>, <8 x i16>) +declare <8 x i16> @llvm.smin.v8i16(<8 x i16>, <8 x i16>) diff --git a/llvm/test/CodeGen/X86/2011-12-06-AVXVectorExtractCombine.ll b/llvm/test/CodeGen/X86/2011-12-06-AVXVectorExtractCombine.ll index 09f6d42..8e56489 100644 --- a/llvm/test/CodeGen/X86/2011-12-06-AVXVectorExtractCombine.ll +++ b/llvm/test/CodeGen/X86/2011-12-06-AVXVectorExtractCombine.ll @@ -10,11 +10,11 @@ define void @test(<4 x i32>* nocapture %p) nounwind { ; CHECK-NEXT: vmovdqu %xmm0, (%rdi) ; CHECK-NEXT: retq %a = load <4 x i32>, <4 x i32>* %p, align 1 - %b = call <4 x i32> @llvm.x86.sse41.pmaxsd(<4 x i32> %a, <4 x i32> zeroinitializer) nounwind + %b = call <4 x i32> @llvm.smax.v4i32(<4 x i32> %a, <4 x i32> zeroinitializer) nounwind %c = shufflevector <4 x i32> %b, <4 x i32> undef, <8 x i32> %d = shufflevector <8 x i32> %c, <8 x i32> undef, <4 x i32> store <4 x i32> %d, <4 x i32>* %p, align 1 ret void } -declare <4 x i32> @llvm.x86.sse41.pmaxsd(<4 x i32>, <4 x i32>) nounwind readnone +declare <4 x i32> @llvm.smax.v4i32(<4 x i32>, <4 x i32>) nounwind readnone diff --git a/llvm/test/CodeGen/X86/pr14161.ll b/llvm/test/CodeGen/X86/pr14161.ll index b78f064..d0ddcd6 100644 --- a/llvm/test/CodeGen/X86/pr14161.ll +++ b/llvm/test/CodeGen/X86/pr14161.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc < %s -mtriple=x86_64-linux-pc -mcpu=corei7 | FileCheck %s -declare <4 x i32> @llvm.x86.sse41.pminud(<4 x i32>, <4 x i32>) +declare <4 x i32> @llvm.umin.v4i32(<4 x i32>, <4 x i32>) define <2 x i16> @good(<4 x i32>*, <4 x i8>*) { ; CHECK-LABEL: good: @@ -11,7 +11,7 @@ define <2 x i16> @good(<4 x i32>*, <4 x i8>*) { ; CHECK-NEXT: retq entry: %2 = load <4 x i32>, <4 x i32>* %0, align 16 - %3 = call <4 x i32> @llvm.x86.sse41.pminud(<4 x i32> %2, <4 x i32> ) + %3 = call <4 x i32> @llvm.umin.v4i32(<4 x i32> %2, <4 x i32> ) %4 = extractelement <4 x i32> %3, i32 0 %5 = extractelement <4 x i32> %3, i32 1 %6 = extractelement <4 x i32> %3, i32 2 @@ -30,7 +30,7 @@ define <2 x i16> @bad(<4 x i32>*, <4 x i8>*) { ; CHECK-NEXT: retq entry: %2 = load <4 x i32>, <4 x i32>* %0, align 16 - %3 = call <4 x i32> @llvm.x86.sse41.pminud(<4 x i32> %2, <4 x i32> ) + %3 = call <4 x i32> @llvm.umin.v4i32(<4 x i32> %2, <4 x i32> ) %4 = extractelement <4 x i32> %3, i32 0 %5 = extractelement <4 x i32> %3, i32 1 %6 = extractelement <4 x i32> %3, i32 2 -- 2.7.4