From ed6eb4b258e4299b7615df3b6979cb62026ee197 Mon Sep 17 00:00:00 2001 From: Artyom Tarasenko Date: Mon, 25 Jul 2011 19:22:38 +0200 Subject: [PATCH] Fix disabling interrupts in sun4u clear interrupt request if the interrupt priority < CPU pil clear hardware interrupt request if interrupts are disabled Signed-off-by: Artyom Tarasenko [blauwirbel@gmail.com: added a comment about magic 2] Signed-off-by: Blue Swirl --- hw/sun4u.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/hw/sun4u.c b/hw/sun4u.c index 1b60e4e..32e6ab9 100644 --- a/hw/sun4u.c +++ b/hw/sun4u.c @@ -261,7 +261,9 @@ void cpu_check_irqs(CPUState *env) pil |= 1 << 14; } - if (!pil) { + /* The bit corresponding to psrpil is (1<< psrpil), the next bit + is (2 << psrpil). */ + if (pil < (2 << env->psrpil)){ if (env->interrupt_request & CPU_INTERRUPT_HARD) { CPUIRQ_DPRINTF("Reset CPU IRQ (current interrupt %x)\n", env->interrupt_index); @@ -293,10 +295,12 @@ void cpu_check_irqs(CPUState *env) break; } } - } else { + } else if (env->interrupt_request & CPU_INTERRUPT_HARD) { CPUIRQ_DPRINTF("Interrupts disabled, pil=%08x pil_in=%08x softint=%08x " "current interrupt %x\n", pil, env->pil_in, env->softint, env->interrupt_index); + env->interrupt_index = 0; + cpu_reset_interrupt(env, CPU_INTERRUPT_HARD); } } -- 2.7.4