From ed6e39134940e2e888111da0e9210d6a8ae40290 Mon Sep 17 00:00:00 2001 From: Alyssa Rosenzweig Date: Wed, 30 Aug 2023 09:40:54 -0400 Subject: [PATCH] agx: Add pseudo-instructions for icmp/fcmp Easier to optimize with. Signed-off-by: Alyssa Rosenzweig Part-of: --- src/asahi/compiler/agx_lower_pseudo.c | 11 +++++++++++ src/asahi/compiler/agx_opcodes.py | 4 ++++ 2 files changed, 15 insertions(+) diff --git a/src/asahi/compiler/agx_lower_pseudo.c b/src/asahi/compiler/agx_lower_pseudo.c index 6a5908a..093f360 100644 --- a/src/asahi/compiler/agx_lower_pseudo.c +++ b/src/asahi/compiler/agx_lower_pseudo.c @@ -65,6 +65,17 @@ lower(agx_builder *b, agx_instr *I) case AGX_OPCODE_OR: return agx_bitop_to(b, I->dest[0], I->src[0], I->src[1], AGX_BITOP_OR); + /* Unfused comparisons are fused with a 0/1 select */ + case AGX_OPCODE_ICMP: + return agx_icmpsel_to(b, I->dest[0], I->src[0], I->src[1], + agx_immediate(I->invert_cond ? 0 : 1), + agx_immediate(I->invert_cond ? 1 : 0), I->icond); + + case AGX_OPCODE_FCMP: + return agx_fcmpsel_to(b, I->dest[0], I->src[0], I->src[1], + agx_immediate(I->invert_cond ? 0 : 1), + agx_immediate(I->invert_cond ? 1 : 0), I->fcond); + /* Writes to the nesting counter lowered to the real register */ case AGX_OPCODE_BEGIN_CF: return agx_mov_imm_to(b, agx_register(0, AGX_SIZE_16), 0); diff --git a/src/asahi/compiler/agx_opcodes.py b/src/asahi/compiler/agx_opcodes.py index cc11f48..443853e 100644 --- a/src/asahi/compiler/agx_opcodes.py +++ b/src/asahi/compiler/agx_opcodes.py @@ -251,6 +251,10 @@ op("fcmpsel", encoding_32 = (0x02, 0x7F, 8, 10), srcs = 4, imms = [FCOND]) +# Pseudo-instructions for compares returning 1/0 +op("icmp", _, srcs = 2, imms = [ICOND, INVERT_COND]) +op("fcmp", _, srcs = 2, imms = [FCOND, INVERT_COND]) + # sources are coordinates, LOD, texture bindless base (zero for texture state # registers), texture, sampler, shadow/offset # TODO: anything else? -- 2.7.4