From ed595e8627b37131d1f0146c24655a1825c5cf13 Mon Sep 17 00:00:00 2001 From: Serge Pavlov Date: Fri, 24 May 2019 01:20:34 +0000 Subject: [PATCH] [AArch64] Add nvcast patterns for v2f32 -> v1f64 Summary: Constant stores of f32 values can create such NvCast nodes. Reviewers: t.p.northover Subscribers: javed.absar, kristof.beyls, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D62285 llvm-svn: 361584 --- llvm/lib/Target/AArch64/AArch64InstrInfo.td | 1 + llvm/test/CodeGen/AArch64/arm64-nvcast.ll | 12 ++++++++++++ 2 files changed, 13 insertions(+) diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td index f426da4..8b70290 100644 --- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td +++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td @@ -6203,6 +6203,7 @@ def : Pat<(v4i16 (AArch64NvCast (v2f32 FPR64:$src))), (v4i16 FPR64:$src)>; def : Pat<(v2i32 (AArch64NvCast (v2f32 FPR64:$src))), (v2i32 FPR64:$src)>; def : Pat<(v2f32 (AArch64NvCast (v2f32 FPR64:$src))), (v2f32 FPR64:$src)>; def : Pat<(v1i64 (AArch64NvCast (v2f32 FPR64:$src))), (v1i64 FPR64:$src)>; +def : Pat<(v1f64 (AArch64NvCast (v2f32 FPR64:$src))), (v1f64 FPR64:$src)>; // Natural vector casts (128 bit) def : Pat<(v16i8 (AArch64NvCast (v4i32 FPR128:$src))), (v16i8 FPR128:$src)>; diff --git a/llvm/test/CodeGen/AArch64/arm64-nvcast.ll b/llvm/test/CodeGen/AArch64/arm64-nvcast.ll index d948612..59b956c 100644 --- a/llvm/test/CodeGen/AArch64/arm64-nvcast.ll +++ b/llvm/test/CodeGen/AArch64/arm64-nvcast.ll @@ -47,3 +47,15 @@ entry: store <2 x float> , <2 x float>* bitcast (%"st1"* @_gv to <2 x float>*), align 8 ret void } + +%struct.Vector3 = type { float, float, float } + +define void @nvcast_v2f32_v1f64(%struct.Vector3*) { +; CHECK-LABEL: _nvcast_v2f32_v1f64 +; CHECK: fmov.2s v[[REG:[0-9]+]], #1.00000000 +; CHECK: str d[[REG]], [x0] +entry: + %a13 = bitcast %struct.Vector3* %0 to <1 x double>* + store <1 x double> , <1 x double>* %a13, align 8 + ret void +} -- 2.7.4