From ed433ca707269cd22fa1137c33818af6c254eea4 Mon Sep 17 00:00:00 2001 From: Seung-Woo Kim Date: Wed, 13 Jan 2021 14:50:51 +0900 Subject: [PATCH] clk: amlogic: g12a: fix divide by zero for default pll register On reset register value 0x20000000 for some plls of g12, there are divide by zero operations warned by UBSAN. For the case, calculate pll rate as zero. This removes below UBSAN warnings: UBSAN: Undefined behaviour in drivers/amlogic/clk/g12a/g12a_clk-pll.c:155:74 ... UBSAN: Undefined behaviour in drivers/amlogic/clk/g12a/g12a_clk-pll.c:140:74 ... UBSAN: Undefined behaviour in drivers/amlogic/clk/g12a/g12a_clk-pll.c:145:25 division by zero ... [] __ubsan_handle_divrem_overflow+0x8c/0xc8 [] meson_g12a_pll_recalc_rate+0x8d0/0x930 [] clk_register+0x724/0xe10 [] g12a_clkc_init+0x640/0x7fc ... Change-Id: I4f0c771502e2ae0291a9eaffbea7a03e617009af Signed-off-by: Seung-Woo Kim --- drivers/amlogic/clk/g12a/g12a_clk-pll.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/amlogic/clk/g12a/g12a_clk-pll.c b/drivers/amlogic/clk/g12a/g12a_clk-pll.c index e466bfc..b32609c 100644 --- a/drivers/amlogic/clk/g12a/g12a_clk-pll.c +++ b/drivers/amlogic/clk/g12a/g12a_clk-pll.c @@ -123,7 +123,9 @@ static unsigned long meson_g12a_pll_recalc_rate(struct clk_hw *hw, p = &pll->frac; - if (p->width >= 2) { + if (!n) { + rate_mhz = 0; + } else if (p->width >= 2) { reg = readl(pll->base + p->reg_off); frac = PARM_GET(p->width - 1, p->shift, reg); -- 2.7.4