From ed34d0ef1a7a1e76d7f51f81532adc3425e35c76 Mon Sep 17 00:00:00 2001 From: Christian Konig Date: Wed, 20 Mar 2013 15:43:00 +0000 Subject: [PATCH] Revert "pre-RA-sched: fix TargetOpcode usage" MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit This reverts commit 06091513c283c863296f01cc7c2e86b56bb50d02. The code is obviously wrong, but the trivial fix causes inefficient code generation on X86. Somebody with more knowledge of the code needs to take a look here. Signed-off-by: Christian König llvm-svn: 177529 --- .../lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp | 30 +++++++++------------- 1 file changed, 12 insertions(+), 18 deletions(-) diff --git a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp index 8d1b102..c009cfc 100644 --- a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp @@ -1894,15 +1894,12 @@ unsigned RegReductionPQBase::getNodePriority(const SUnit *SU) const { // CopyToReg should be close to its uses to facilitate coalescing and // avoid spilling. return 0; - if (SU->getNode() && SU->getNode()->isMachineOpcode()) { - Opc = SU->getNode()->getMachineOpcode(); - if (Opc == TargetOpcode::EXTRACT_SUBREG || - Opc == TargetOpcode::SUBREG_TO_REG || - Opc == TargetOpcode::INSERT_SUBREG) - // EXTRACT_SUBREG, INSERT_SUBREG, and SUBREG_TO_REG nodes should be - // close to their uses to facilitate coalescing. - return 0; - } + if (Opc == TargetOpcode::EXTRACT_SUBREG || + Opc == TargetOpcode::SUBREG_TO_REG || + Opc == TargetOpcode::INSERT_SUBREG) + // EXTRACT_SUBREG, INSERT_SUBREG, and SUBREG_TO_REG nodes should be + // close to their uses to facilitate coalescing. + return 0; if (SU->NumSuccs == 0 && SU->NumPreds != 0) // If SU does not have a register use, i.e. it doesn't produce a value // that would be consumed (e.g. store), then it terminates a chain of @@ -2588,15 +2585,12 @@ static bool canEnableCoalescing(SUnit *SU) { // avoid spilling. return true; - if (SU->getNode() && SU->getNode()->isMachineOpcode()) { - Opc = SU->getNode()->getMachineOpcode(); - if (Opc == TargetOpcode::EXTRACT_SUBREG || - Opc == TargetOpcode::SUBREG_TO_REG || - Opc == TargetOpcode::INSERT_SUBREG) - // EXTRACT_SUBREG, INSERT_SUBREG, and SUBREG_TO_REG nodes should be - // close to their uses to facilitate coalescing. - return true; - } + if (Opc == TargetOpcode::EXTRACT_SUBREG || + Opc == TargetOpcode::SUBREG_TO_REG || + Opc == TargetOpcode::INSERT_SUBREG) + // EXTRACT_SUBREG, INSERT_SUBREG, and SUBREG_TO_REG nodes should be + // close to their uses to facilitate coalescing. + return true; if (SU->NumPreds == 0 && SU->NumSuccs != 0) // If SU does not have a register def, schedule it close to its uses -- 2.7.4