From ecea07c50ecc85f6e474d8f4831e566f97ac2be2 Mon Sep 17 00:00:00 2001
From: Krzysztof Parzyszek <kparzysz@codeaurora.org>
Date: Thu, 14 Jul 2016 19:30:55 +0000
Subject: [PATCH] [Hexagon] Packetize function call arguments with tail call
 instructions

On Hexagon is it legal to packetize the instructions setting up call
arguments with the call instruction itself. This was already done,
except for tail calls. Make sure tail calls are handled as well.

llvm-svn: 275458
---
 llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp       | 11 +++++++++++
 llvm/lib/Target/Hexagon/HexagonInstrInfo.h         |  1 +
 llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp  |  2 +-
 .../test/CodeGen/Hexagon/packetize-tailcall-arg.ll | 22 ++++++++++++++++++++++
 4 files changed, 35 insertions(+), 1 deletion(-)
 create mode 100644 llvm/test/CodeGen/Hexagon/packetize-tailcall-arg.ll

diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp b/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
index d3fd517..f3230a7 100644
--- a/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
@@ -2437,6 +2437,17 @@ bool HexagonInstrInfo::isSpillPredRegOp(const MachineInstr *MI) const {
 }
 
 
+bool HexagonInstrInfo::isTailCall(const MachineInstr *MI) const {
+  if (!MI->isBranch())
+    return false;
+
+  for (auto &Op : MI->operands())
+    if (Op.isGlobal() || Op.isSymbol())
+      return true;
+  return false;
+}
+
+
 // Returns true when SU has a timing class TC1.
 bool HexagonInstrInfo::isTC1(const MachineInstr *MI) const {
   unsigned SchedClass = MI->getDesc().getSchedClass();
diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfo.h b/llvm/lib/Target/Hexagon/HexagonInstrInfo.h
index 92f8c33..50bd7e9 100644
--- a/llvm/lib/Target/Hexagon/HexagonInstrInfo.h
+++ b/llvm/lib/Target/Hexagon/HexagonInstrInfo.h
@@ -309,6 +309,7 @@ public:
   bool isSignExtendingLoad(const MachineInstr &MI) const;
   bool isSolo(const MachineInstr* MI) const;
   bool isSpillPredRegOp(const MachineInstr *MI) const;
+  bool isTailCall(const MachineInstr *MI) const;
   bool isTC1(const MachineInstr *MI) const;
   bool isTC2(const MachineInstr *MI) const;
   bool isTC2Early(const MachineInstr *MI) const;
diff --git a/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp b/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp
index 033c021..0b3aea1 100644
--- a/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp
@@ -1248,7 +1248,7 @@ bool HexagonPacketizerList::isLegalToPacketizeTogether(SUnit *SUI, SUnit *SUJ) {
       RC = HRI->getMinimalPhysRegClass(DepReg);
     }
 
-    if (I->isCall() || I->isReturn()) {
+    if (I->isCall() || I->isReturn() || HII->isTailCall(I)) {
       if (!isRegDependence(DepType))
         continue;
       if (!isCallDependent(I, DepType, SUJ->Succs[i].getReg()))
diff --git a/llvm/test/CodeGen/Hexagon/packetize-tailcall-arg.ll b/llvm/test/CodeGen/Hexagon/packetize-tailcall-arg.ll
new file mode 100644
index 0000000..17afd7d
--- /dev/null
+++ b/llvm/test/CodeGen/Hexagon/packetize-tailcall-arg.ll
@@ -0,0 +1,22 @@
+; RUN: llc -march=hexagon < %s | FileCheck %s
+; There should only be one packet:
+; {
+;   jump free
+;   r0 = memw(r0 + #-4)
+; }
+;
+; CHECK: {
+; CHECK-NOT: {
+
+define void @fred(i8* %p) nounwind {
+entry:
+  %arrayidx = getelementptr inbounds i8, i8* %p, i32 -4
+  %t0 = bitcast i8* %arrayidx to i8**
+  %t1 = load i8*, i8** %t0, align 4
+  tail call void @free(i8* %t1)
+  ret void
+}
+
+; Function Attrs: nounwind
+declare void @free(i8* nocapture) nounwind
+
-- 
2.7.4