From ece459bb661f4324f478b6a5b9335be497484735 Mon Sep 17 00:00:00 2001 From: Akira Hatanaka Date: Fri, 1 Mar 2013 21:52:08 +0000 Subject: [PATCH] [mips] Fix inefficient code generation. This patch eliminates the need to emit a constant move instruction when this pattern is matched: (select (setgt a, Constant), T, F) The pattern above effectively turns into this: (conditional-move (setlt a, Constant + 1), F, T) llvm-svn: 176384 --- llvm/lib/Target/Mips/MipsCondMov.td | 7 ++ llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp | 2 +- llvm/lib/Target/Mips/MipsInstrInfo.td | 8 ++ llvm/test/CodeGen/Mips/cmov.ll | 137 ++++++++++++++++++++++++++++++ llvm/test/CodeGen/Mips/mips64-f128.ll | 6 +- 5 files changed, 156 insertions(+), 4 deletions(-) diff --git a/llvm/lib/Target/Mips/MipsCondMov.td b/llvm/lib/Target/Mips/MipsCondMov.td index 1c68f24..42e4c99 100644 --- a/llvm/lib/Target/Mips/MipsCondMov.td +++ b/llvm/lib/Target/Mips/MipsCondMov.td @@ -68,6 +68,13 @@ multiclass MovzPats0; def : MipsPat<(select (i32 (setule CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F), (MOVZInst DRC:$T, (SLTuOp CRC:$rhs, CRC:$lhs), DRC:$F)>; + def : MipsPat<(select (i32 (setgt CRC:$lhs, immSExt16Plus1:$rhs)), + DRC:$T, DRC:$F), + (MOVZInst DRC:$T, (SLTiOp CRC:$lhs, (Plus1 imm:$rhs)), DRC:$F)>; + def : MipsPat<(select (i32 (setugt CRC:$lhs, immSExt16Plus1:$rhs)), + DRC:$T, DRC:$F), + (MOVZInst DRC:$T, (SLTiuOp CRC:$lhs, (Plus1 imm:$rhs)), + DRC:$F)>; } multiclass MovzPats1getTargetConstant(Imm, Node->getValueType(0)); } diff --git a/llvm/lib/Target/Mips/MipsInstrInfo.td b/llvm/lib/Target/Mips/MipsInstrInfo.td index de09c9e..b71ced1 100644 --- a/llvm/lib/Target/Mips/MipsInstrInfo.td +++ b/llvm/lib/Target/Mips/MipsInstrInfo.td @@ -299,6 +299,9 @@ def HI16 : SDNodeXFormgetZExtValue() >> 16) & 0xFFFF); }]>; +// Plus 1. +def Plus1 : SDNodeXFormgetSExtValue() + 1); }]>; + // Node immediate fits as 16-bit sign extended on target immediate. // e.g. addi, andi def immSExt8 : PatLeaf<(imm), [{ return isInt<8>(N->getSExtValue()); }]>; @@ -331,6 +334,11 @@ def immLow16Zero : PatLeaf<(imm), [{ // shamt field must fit in 5 bits. def immZExt5 : ImmLeaf; +// True if (N + 1) fits in 16-bit field. +def immSExt16Plus1 : PatLeaf<(imm), [{ + return isInt<17>(N->getSExtValue()) && isInt<16>(N->getSExtValue() + 1); +}]>; + // Mips Address Mode! SDNode frameindex could possibily be a match // since load and store instructions from stack used it. def addr : diff --git a/llvm/test/CodeGen/Mips/cmov.ll b/llvm/test/CodeGen/Mips/cmov.ll index 3af899a..81925a4 100755 --- a/llvm/test/CodeGen/Mips/cmov.ll +++ b/llvm/test/CodeGen/Mips/cmov.ll @@ -59,3 +59,140 @@ entry: ret i64 %cond } +; slti and conditional move. +; +; Check that, pattern +; (select (setgt a, N), t, f) +; turns into +; (movz t, (setlt a, N + 1), f) +; if N + 1 fits in 16-bit. + +; O32: slti0: +; O32: slti $[[R0:[0-9]+]], ${{[0-9]+}}, 32767 +; O32: movz ${{[0-9]+}}, ${{[0-9]+}}, $[[R0]] + +define i32 @slti0(i32 %a) { +entry: + %cmp = icmp sgt i32 %a, 32766 + %cond = select i1 %cmp, i32 3, i32 4 + ret i32 %cond +} + +; O32: slti1: +; O32: slt ${{[0-9]+}} + +define i32 @slti1(i32 %a) { +entry: + %cmp = icmp sgt i32 %a, 32767 + %cond = select i1 %cmp, i32 3, i32 4 + ret i32 %cond +} + +; O32: slti2: +; O32: slti $[[R0:[0-9]+]], ${{[0-9]+}}, -32768 +; O32: movz ${{[0-9]+}}, ${{[0-9]+}}, $[[R0]] + +define i32 @slti2(i32 %a) { +entry: + %cmp = icmp sgt i32 %a, -32769 + %cond = select i1 %cmp, i32 3, i32 4 + ret i32 %cond +} + +; O32: slti3: +; O32: slt ${{[0-9]+}} + +define i32 @slti3(i32 %a) { +entry: + %cmp = icmp sgt i32 %a, -32770 + %cond = select i1 %cmp, i32 3, i32 4 + ret i32 %cond +} + +; 64-bit patterns. + +; N64: slti64_0: +; N64: slti $[[R0:[0-9]+]], ${{[0-9]+}}, 32767 +; N64: movz ${{[0-9]+}}, ${{[0-9]+}}, $[[R0]] + +define i64 @slti64_0(i64 %a) { +entry: + %cmp = icmp sgt i64 %a, 32766 + %conv = select i1 %cmp, i64 3, i64 4 + ret i64 %conv +} + +; N64: slti64_1: +; N64: slt ${{[0-9]+}} + +define i64 @slti64_1(i64 %a) { +entry: + %cmp = icmp sgt i64 %a, 32767 + %conv = select i1 %cmp, i64 3, i64 4 + ret i64 %conv +} + +; N64: slti64_2: +; N64: slti $[[R0:[0-9]+]], ${{[0-9]+}}, -32768 +; N64: movz ${{[0-9]+}}, ${{[0-9]+}}, $[[R0]] + +define i64 @slti64_2(i64 %a) { +entry: + %cmp = icmp sgt i64 %a, -32769 + %conv = select i1 %cmp, i64 3, i64 4 + ret i64 %conv +} + +; N64: slti64_3: +; N64: slt ${{[0-9]+}} + +define i64 @slti64_3(i64 %a) { +entry: + %cmp = icmp sgt i64 %a, -32770 + %conv = select i1 %cmp, i64 3, i64 4 + ret i64 %conv +} + +; sltiu instructions. + +; O32: sltiu0: +; O32: sltiu $[[R0:[0-9]+]], ${{[0-9]+}}, 32767 +; O32: movz ${{[0-9]+}}, ${{[0-9]+}}, $[[R0]] + +define i32 @sltiu0(i32 %a) { +entry: + %cmp = icmp ugt i32 %a, 32766 + %cond = select i1 %cmp, i32 3, i32 4 + ret i32 %cond +} + +; O32: sltiu1: +; O32: sltu ${{[0-9]+}} + +define i32 @sltiu1(i32 %a) { +entry: + %cmp = icmp ugt i32 %a, 32767 + %cond = select i1 %cmp, i32 3, i32 4 + ret i32 %cond +} + +; O32: sltiu2: +; O32: sltiu $[[R0:[0-9]+]], ${{[0-9]+}}, -32768 +; O32: movz ${{[0-9]+}}, ${{[0-9]+}}, $[[R0]] + +define i32 @sltiu2(i32 %a) { +entry: + %cmp = icmp ugt i32 %a, -32769 + %cond = select i1 %cmp, i32 3, i32 4 + ret i32 %cond +} + +; O32: sltiu3: +; O32: sltu ${{[0-9]+}} + +define i32 @sltiu3(i32 %a) { +entry: + %cmp = icmp ugt i32 %a, -32770 + %cond = select i1 %cmp, i32 3, i32 4 + ret i32 %cond +} diff --git a/llvm/test/CodeGen/Mips/mips64-f128.ll b/llvm/test/CodeGen/Mips/mips64-f128.ll index 9aa8b8e..c6dd434 100644 --- a/llvm/test/CodeGen/Mips/mips64-f128.ll +++ b/llvm/test/CodeGen/Mips/mips64-f128.ll @@ -632,9 +632,9 @@ entry: ; CHECK: or $[[R3:[0-9]+]], $8, $zero ; CHECK: ld $25, %call16(__gttf2)($gp) ; CHECK: jalr $25 -; CHECK: slt $1, $zero, $2 -; CHECK: movn $[[R1]], $[[R3]], $1 -; CHECK: movn $[[R0]], $[[R2]], $1 +; CHECK: slti $1, $2, 1 +; CHECK: movz $[[R1]], $[[R3]], $1 +; CHECK: movz $[[R0]], $[[R2]], $1 ; CHECK: or $2, $[[R1]], $zero ; CHECK: or $3, $[[R0]], $zero -- 2.7.4