From ec8631e01143e593c4f28d3d2d8a11073ce38b7f Mon Sep 17 00:00:00 2001 From: Alex Sierra Date: Wed, 3 Feb 2021 19:02:20 -0600 Subject: [PATCH] drm/amdgpu: use pd addr based on gart level page table With a recent gart page table re-construction, the gart page table is now 2-level for some ASICs: PDB0->PTB. In the case of 2-level gart page table, the page_table_base of vmid0 should point to PDB0 instead of PTB. Signed-off-by: Alex Sierra Reviewed-by: Felix Kuehling Reviewed-by: Oak Zeng Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index 4add9ea..0ea1b68 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -2057,7 +2057,8 @@ int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset, return r; if (vm_needs_flush) { - job->vm_pd_addr = amdgpu_gmc_pd_addr(adev->gart.bo); + job->vm_pd_addr = amdgpu_gmc_pd_addr(adev->gmc.pdb0_bo ? + adev->gmc.pdb0_bo : adev->gart.bo); job->vm_needs_flush = true; } if (resv) { -- 2.7.4