From ec02635d104c5f42840c63ed41d0cea774d649fe Mon Sep 17 00:00:00 2001 From: Michael Liao Date: Thu, 4 Jun 2020 02:00:06 -0400 Subject: [PATCH] [amdgpu] Skip OR combining on 64-bit integer before legalizing ops. Reviewers: arsenm, rampitec Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, kerbowa, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D81710 --- llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 2 +- llvm/test/CodeGen/AMDGPU/fshr.ll | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp index f1aba26..ff38503 100644 --- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp @@ -8958,7 +8958,7 @@ SDValue SITargetLowering::performOrCombine(SDNode *N, } } - if (VT != MVT::i64) + if (VT != MVT::i64 || DCI.isBeforeLegalizeOps()) return SDValue(); // TODO: This could be a generic combine with a predicate for extracting the diff --git a/llvm/test/CodeGen/AMDGPU/fshr.ll b/llvm/test/CodeGen/AMDGPU/fshr.ll index a71384e..e27cbe7 100644 --- a/llvm/test/CodeGen/AMDGPU/fshr.ll +++ b/llvm/test/CodeGen/AMDGPU/fshr.ll @@ -763,7 +763,7 @@ define <3 x i16> @v_fshr_v3i16(<3 x i16> %src0, <3 x i16> %src1, <3 x i16> %src2 ; SI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1 ; SI-NEXT: v_cndmask_b32_e32 v1, v2, v5, vcc ; SI-NEXT: v_and_b32_e32 v2, v9, v1 -; SI-NEXT: v_alignbit_b32 v1, v2, v0, 16 +; SI-NEXT: v_alignbit_b32 v1, v1, v0, 16 ; SI-NEXT: s_setpc_b64 s[30:31] ; ; VI-LABEL: v_fshr_v3i16: -- 2.7.4