From eba6deab22b576004a209b3f42ccc5e58f7603bf Mon Sep 17 00:00:00 2001 From: Paul Walker Date: Fri, 18 Dec 2020 17:06:32 +0000 Subject: [PATCH] [SVE] Lower vector CTLZ, CTPOP and CTTZ operations. CTLZ and CTPOP are lowered to CLZ and CNT instructions respectively. CTTZ is not a native SVE operation but is instead lowered to: CTTZ(V) => CTLZ(BITREVERSE(V)) In the case of fixed-length support using SVE we also lower CTTZ operating on NEON sized vectors because of its reliance on BITREVERSE which is also lowered to SVE intructions at these lengths. Differential Revision: https://reviews.llvm.org/D93607 --- llvm/lib/Target/AArch64/AArch64ISelLowering.cpp | 43 + llvm/lib/Target/AArch64/AArch64ISelLowering.h | 3 + llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td | 19 +- llvm/lib/Target/AArch64/SVEInstrFormats.td | 14 +- llvm/test/CodeGen/AArch64/sve-bit-counting.ll | 173 +++ .../AArch64/sve-fixed-length-bit-counting.ll | 1128 ++++++++++++++++++++ 6 files changed, 1364 insertions(+), 16 deletions(-) create mode 100644 llvm/test/CodeGen/AArch64/sve-bit-counting.ll create mode 100644 llvm/test/CodeGen/AArch64/sve-fixed-length-bit-counting.ll diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp index 2012f12..faed7c6 100644 --- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp +++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp @@ -184,6 +184,8 @@ static bool isMergePassthruOpcode(unsigned Opc) { return false; case AArch64ISD::BITREVERSE_MERGE_PASSTHRU: case AArch64ISD::BSWAP_MERGE_PASSTHRU: + case AArch64ISD::CTLZ_MERGE_PASSTHRU: + case AArch64ISD::CTPOP_MERGE_PASSTHRU: case AArch64ISD::DUP_MERGE_PASSTHRU: case AArch64ISD::FNEG_MERGE_PASSTHRU: case AArch64ISD::SIGN_EXTEND_INREG_MERGE_PASSTHRU: @@ -1070,6 +1072,9 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM, for (auto VT : {MVT::nxv16i8, MVT::nxv8i16, MVT::nxv4i32, MVT::nxv2i64}) { setOperationAction(ISD::BITREVERSE, VT, Custom); setOperationAction(ISD::BSWAP, VT, Custom); + setOperationAction(ISD::CTLZ, VT, Custom); + setOperationAction(ISD::CTPOP, VT, Custom); + setOperationAction(ISD::CTTZ, VT, Custom); setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom); setOperationAction(ISD::UINT_TO_FP, VT, Custom); setOperationAction(ISD::SINT_TO_FP, VT, Custom); @@ -1188,6 +1193,9 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM, // These operations are not supported on NEON but SVE can do them. setOperationAction(ISD::BITREVERSE, MVT::v1i64, Custom); + setOperationAction(ISD::CTLZ, MVT::v1i64, Custom); + setOperationAction(ISD::CTLZ, MVT::v2i64, Custom); + setOperationAction(ISD::CTTZ, MVT::v1i64, Custom); setOperationAction(ISD::MUL, MVT::v1i64, Custom); setOperationAction(ISD::MUL, MVT::v2i64, Custom); setOperationAction(ISD::SDIV, MVT::v8i8, Custom); @@ -1223,6 +1231,7 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM, for (auto VT : {MVT::v8i8, MVT::v16i8, MVT::v4i16, MVT::v8i16, MVT::v2i32, MVT::v4i32, MVT::v2i64}) { setOperationAction(ISD::BITREVERSE, VT, Custom); + setOperationAction(ISD::CTTZ, VT, Custom); setOperationAction(ISD::VECREDUCE_AND, VT, Custom); setOperationAction(ISD::VECREDUCE_OR, VT, Custom); setOperationAction(ISD::VECREDUCE_XOR, VT, Custom); @@ -1338,6 +1347,9 @@ void AArch64TargetLowering::addTypeForFixedLengthSVE(MVT VT) { setOperationAction(ISD::ANY_EXTEND, VT, Custom); setOperationAction(ISD::BITREVERSE, VT, Custom); setOperationAction(ISD::BSWAP, VT, Custom); + setOperationAction(ISD::CTLZ, VT, Custom); + setOperationAction(ISD::CTPOP, VT, Custom); + setOperationAction(ISD::CTTZ, VT, Custom); setOperationAction(ISD::FADD, VT, Custom); setOperationAction(ISD::FCEIL, VT, Custom); setOperationAction(ISD::FDIV, VT, Custom); @@ -1944,6 +1956,8 @@ const char *AArch64TargetLowering::getTargetNodeName(unsigned Opcode) const { MAKE_CASE(AArch64ISD::STNP) MAKE_CASE(AArch64ISD::BITREVERSE_MERGE_PASSTHRU) MAKE_CASE(AArch64ISD::BSWAP_MERGE_PASSTHRU) + MAKE_CASE(AArch64ISD::CTLZ_MERGE_PASSTHRU) + MAKE_CASE(AArch64ISD::CTPOP_MERGE_PASSTHRU) MAKE_CASE(AArch64ISD::DUP_MERGE_PASSTHRU) MAKE_CASE(AArch64ISD::INDEX_VECTOR) MAKE_CASE(AArch64ISD::UABD) @@ -3577,6 +3591,17 @@ SDValue AArch64TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, case Intrinsic::aarch64_sve_ptrue: return DAG.getNode(AArch64ISD::PTRUE, dl, Op.getValueType(), Op.getOperand(1)); + case Intrinsic::aarch64_sve_clz: + return DAG.getNode(AArch64ISD::CTLZ_MERGE_PASSTHRU, dl, Op.getValueType(), + Op.getOperand(2), Op.getOperand(3), Op.getOperand(1)); + case Intrinsic::aarch64_sve_cnt: { + SDValue Data = Op.getOperand(3); + // CTPOP only supports integer operands. + if (Data.getValueType().isFloatingPoint()) + Data = DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Data); + return DAG.getNode(AArch64ISD::CTPOP_MERGE_PASSTHRU, dl, Op.getValueType(), + Op.getOperand(2), Data, Op.getOperand(1)); + } case Intrinsic::aarch64_sve_dupq_lane: return LowerDUPQLane(Op, DAG); case Intrinsic::aarch64_sve_convert_from_svbool: @@ -4378,6 +4403,11 @@ SDValue AArch64TargetLowering::LowerOperation(SDValue Op, /*OverrideNEON=*/true); case ISD::BSWAP: return LowerToPredicatedOp(Op, DAG, AArch64ISD::BSWAP_MERGE_PASSTHRU); + case ISD::CTLZ: + return LowerToPredicatedOp(Op, DAG, AArch64ISD::CTLZ_MERGE_PASSTHRU, + /*OverrideNEON=*/true); + case ISD::CTTZ: + return LowerCTTZ(Op, DAG); } } @@ -6484,6 +6514,9 @@ SDValue AArch64TargetLowering::LowerCTPOP(SDValue Op, SelectionDAG &DAG) const { return DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i128, UaddLV); } + if (VT.isScalableVector() || useSVEForFixedLengthVectorVT(VT)) + return LowerToPredicatedOp(Op, DAG, AArch64ISD::CTPOP_MERGE_PASSTHRU); + assert((VT == MVT::v1i64 || VT == MVT::v2i64 || VT == MVT::v2i32 || VT == MVT::v4i32 || VT == MVT::v4i16 || VT == MVT::v8i16) && "Unexpected type for custom ctpop lowering"); @@ -6507,6 +6540,16 @@ SDValue AArch64TargetLowering::LowerCTPOP(SDValue Op, SelectionDAG &DAG) const { return Val; } +SDValue AArch64TargetLowering::LowerCTTZ(SDValue Op, SelectionDAG &DAG) const { + EVT VT = Op.getValueType(); + assert(VT.isScalableVector() || + useSVEForFixedLengthVectorVT(VT, /*OverrideNEON=*/true)); + + SDLoc DL(Op); + SDValue RBIT = DAG.getNode(ISD::BITREVERSE, DL, VT, Op.getOperand(0)); + return DAG.getNode(ISD::CTLZ, DL, VT, RBIT); +} + SDValue AArch64TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const { if (Op.getValueType().isVector()) diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.h b/llvm/lib/Target/AArch64/AArch64ISelLowering.h index 36518a5..96aaf40 100644 --- a/llvm/lib/Target/AArch64/AArch64ISelLowering.h +++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.h @@ -307,6 +307,8 @@ enum NodeType : unsigned { BITREVERSE_MERGE_PASSTHRU, BSWAP_MERGE_PASSTHRU, + CTLZ_MERGE_PASSTHRU, + CTPOP_MERGE_PASSTHRU, DUP_MERGE_PASSTHRU, INDEX_VECTOR, @@ -909,6 +911,7 @@ private: SDValue LowerShiftRightParts(SDValue Op, SelectionDAG &DAG) const; SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) const; SDValue LowerCTPOP(SDValue Op, SelectionDAG &DAG) const; + SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) const; SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const; SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const; SDValue LowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const; diff --git a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td index e9a823c..4478670 100644 --- a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td +++ b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td @@ -201,6 +201,8 @@ def SDT_AArch64IntExtend : SDTypeProfile<1, 4, [ ]>; // Predicated operations with the result of inactive lanes provided by the last operand. +def AArch64clz_mt : SDNode<"AArch64ISD::CTLZ_MERGE_PASSTHRU", SDT_AArch64Arith>; +def AArch64cnt_mt : SDNode<"AArch64ISD::CTPOP_MERGE_PASSTHRU", SDT_AArch64Arith>; def AArch64fneg_mt : SDNode<"AArch64ISD::FNEG_MERGE_PASSTHRU", SDT_AArch64Arith>; def AArch64fabs_mt : SDNode<"AArch64ISD::FABS_MERGE_PASSTHRU", SDT_AArch64Arith>; def AArch64sxt_mt : SDNode<"AArch64ISD::SIGN_EXTEND_INREG_MERGE_PASSTHRU", SDT_AArch64IntExtend>; @@ -217,6 +219,12 @@ def AArch64frecpx_mt : SDNode<"AArch64ISD::FRECPX_MERGE_PASSTHRU", SDT_AArch64Ar def AArch64rbit_mt : SDNode<"AArch64ISD::BITREVERSE_MERGE_PASSTHRU", SDT_AArch64Arith>; def AArch64revb_mt : SDNode<"AArch64ISD::BSWAP_MERGE_PASSTHRU", SDT_AArch64Arith>; +// These are like the above but we don't yet have need for ISD nodes. They allow +// a single pattern to match intrinsic and ISD operand layouts. +def AArch64cls_mt : PatFrags<(ops node:$pg, node:$op, node:$pt), [(int_aarch64_sve_cls node:$pt, node:$pg, node:$op)]>; +def AArch64cnot_mt : PatFrags<(ops node:$pg, node:$op, node:$pt), [(int_aarch64_sve_cnot node:$pt, node:$pg, node:$op)]>; +def AArch64not_mt : PatFrags<(ops node:$pg, node:$op, node:$pt), [(int_aarch64_sve_not node:$pt, node:$pg, node:$op)]>; + def SDT_AArch64FCVT : SDTypeProfile<1, 3, [ SDTCisVec<0>, SDTCisVec<1>, SDTCisVec<2>, SDTCisVec<3>, SDTCVecEltisVT<1,i1> @@ -371,12 +379,11 @@ let Predicates = [HasSVE] in { defm ABS_ZPmZ : sve_int_un_pred_arit_0< 0b110, "abs", int_aarch64_sve_abs>; defm NEG_ZPmZ : sve_int_un_pred_arit_0< 0b111, "neg", int_aarch64_sve_neg>; - defm CLS_ZPmZ : sve_int_un_pred_arit_1< 0b000, "cls", int_aarch64_sve_cls>; - defm CLZ_ZPmZ : sve_int_un_pred_arit_1< 0b001, "clz", int_aarch64_sve_clz>; - defm CNT_ZPmZ : sve_int_un_pred_arit_1< 0b010, "cnt", int_aarch64_sve_cnt>; - - defm CNOT_ZPmZ : sve_int_un_pred_arit_1< 0b011, "cnot", int_aarch64_sve_cnot>; - defm NOT_ZPmZ : sve_int_un_pred_arit_1< 0b110, "not", int_aarch64_sve_not>; + defm CLS_ZPmZ : sve_int_un_pred_arit_1< 0b000, "cls", AArch64cls_mt>; + defm CLZ_ZPmZ : sve_int_un_pred_arit_1< 0b001, "clz", AArch64clz_mt>; + defm CNT_ZPmZ : sve_int_un_pred_arit_1< 0b010, "cnt", AArch64cnt_mt>; + defm CNOT_ZPmZ : sve_int_un_pred_arit_1< 0b011, "cnot", AArch64cnot_mt>; + defm NOT_ZPmZ : sve_int_un_pred_arit_1< 0b110, "not", AArch64not_mt>; defm FABS_ZPmZ : sve_int_un_pred_arit_1_fp<0b100, "fabs", AArch64fabs_mt>; defm FNEG_ZPmZ : sve_int_un_pred_arit_1_fp<0b101, "fneg", AArch64fneg_mt>; diff --git a/llvm/lib/Target/AArch64/SVEInstrFormats.td b/llvm/lib/Target/AArch64/SVEInstrFormats.td index b5077cf..8208eb4 100644 --- a/llvm/lib/Target/AArch64/SVEInstrFormats.td +++ b/llvm/lib/Target/AArch64/SVEInstrFormats.td @@ -3813,16 +3813,10 @@ multiclass sve_int_un_pred_arit_1 opc, string asm, def _S : sve_int_un_pred_arit<0b10, { opc, 0b1 }, asm, ZPR32>; def _D : sve_int_un_pred_arit<0b11, { opc, 0b1 }, asm, ZPR64>; - def : SVE_3_Op_Pat(NAME # _B)>; - def : SVE_3_Op_Pat(NAME # _H)>; - def : SVE_3_Op_Pat(NAME # _S)>; - def : SVE_3_Op_Pat(NAME # _D)>; - - def : SVE_3_Op_Pat(NAME # _H)>; - def : SVE_3_Op_Pat(NAME # _S)>; - def : SVE_3_Op_Pat(NAME # _D)>; - - def : SVE_3_Op_Pat(NAME # _H)>; + def : SVE_1_Op_Passthru_Pat(NAME # _B)>; + def : SVE_1_Op_Passthru_Pat(NAME # _H)>; + def : SVE_1_Op_Passthru_Pat(NAME # _S)>; + def : SVE_1_Op_Passthru_Pat(NAME # _D)>; } multiclass sve_int_un_pred_arit_1_fp opc, string asm, SDPatternOperator op> { diff --git a/llvm/test/CodeGen/AArch64/sve-bit-counting.ll b/llvm/test/CodeGen/AArch64/sve-bit-counting.ll new file mode 100644 index 0000000..a4364e9 --- /dev/null +++ b/llvm/test/CodeGen/AArch64/sve-bit-counting.ll @@ -0,0 +1,173 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc < %s 2>%t | FileCheck %s +; RUN: FileCheck --check-prefix=WARN --allow-empty %s <%t + +; If this check fails please read test/CodeGen/AArch64/README for instructions on how to resolve it. +; WARN-NOT: warning + +target triple = "aarch64-unknown-linux-gnu" + +; +; CLZ +; + +define @ctlz_b( %a) #0 { +; CHECK-LABEL: ctlz_b: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p0.b +; CHECK-NEXT: clz z0.b, p0/m, z0.b +; CHECK-NEXT: ret + + %res = call @llvm.ctlz.nxv16i8( %a) + ret %res +} + +define @ctlz_h( %a) #0 { +; CHECK-LABEL: ctlz_h: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p0.h +; CHECK-NEXT: clz z0.h, p0/m, z0.h +; CHECK-NEXT: ret + + %res = call @llvm.ctlz.nxv8i16( %a) + ret %res +} + +define @ctlz_s( %a) #0 { +; CHECK-LABEL: ctlz_s: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p0.s +; CHECK-NEXT: clz z0.s, p0/m, z0.s +; CHECK-NEXT: ret + + %res = call @llvm.ctlz.nxv4i32( %a) + ret %res +} + +define @ctlz_d( %a) #0 { +; CHECK-LABEL: ctlz_d: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p0.d +; CHECK-NEXT: clz z0.d, p0/m, z0.d +; CHECK-NEXT: ret + + %res = call @llvm.ctlz.nxv2i64( %a) + ret %res +} + +; +; CNT +; + +define @ctpop_b( %a) #0 { +; CHECK-LABEL: ctpop_b: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p0.b +; CHECK-NEXT: cnt z0.b, p0/m, z0.b +; CHECK-NEXT: ret + + %res = call @llvm.ctpop.nxv16i8( %a) + ret %res +} + +define @ctpop_h( %a) #0 { +; CHECK-LABEL: ctpop_h: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p0.h +; CHECK-NEXT: cnt z0.h, p0/m, z0.h +; CHECK-NEXT: ret + + %res = call @llvm.ctpop.nxv8i16( %a) + ret %res +} + +define @ctpop_s( %a) #0 { +; CHECK-LABEL: ctpop_s: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p0.s +; CHECK-NEXT: cnt z0.s, p0/m, z0.s +; CHECK-NEXT: ret + + %res = call @llvm.ctpop.nxv4i32( %a) + ret %res +} + +define @ctpop_d( %a) #0 { +; CHECK-LABEL: ctpop_d: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p0.d +; CHECK-NEXT: cnt z0.d, p0/m, z0.d +; CHECK-NEXT: ret + + %res = call @llvm.ctpop.nxv2i64( %a) + ret %res +} + +; +; Count trailing zeros +; + +define @cttz_b( %a) #0 { +; CHECK-LABEL: cttz_b: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p0.b +; CHECK-NEXT: rbit z0.b, p0/m, z0.b +; CHECK-NEXT: clz z0.b, p0/m, z0.b +; CHECK-NEXT: ret + + %res = call @llvm.cttz.nxv16i8( %a) + ret %res +} + +define @cttz_h( %a) #0 { +; CHECK-LABEL: cttz_h: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p0.h +; CHECK-NEXT: rbit z0.h, p0/m, z0.h +; CHECK-NEXT: clz z0.h, p0/m, z0.h +; CHECK-NEXT: ret + + %res = call @llvm.cttz.nxv8i16( %a) + ret %res +} + +define @cttz_s( %a) #0 { +; CHECK-LABEL: cttz_s: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p0.s +; CHECK-NEXT: rbit z0.s, p0/m, z0.s +; CHECK-NEXT: clz z0.s, p0/m, z0.s +; CHECK-NEXT: ret + + %res = call @llvm.cttz.nxv4i32( %a) + ret %res +} + +define @cttz_d( %a) #0 { +; CHECK-LABEL: cttz_d: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p0.d +; CHECK-NEXT: rbit z0.d, p0/m, z0.d +; CHECK-NEXT: clz z0.d, p0/m, z0.d +; CHECK-NEXT: ret + + %res = call @llvm.cttz.nxv2i64( %a) + ret %res +} + +attributes #0 = { "target-features"="+sve" } + +declare @llvm.ctlz.nxv16i8() +declare @llvm.ctlz.nxv8i16() +declare @llvm.ctlz.nxv4i32() +declare @llvm.ctlz.nxv2i64() + +declare @llvm.ctpop.nxv16i8() +declare @llvm.ctpop.nxv8i16() +declare @llvm.ctpop.nxv4i32() +declare @llvm.ctpop.nxv2i64() + +declare @llvm.cttz.nxv16i8() +declare @llvm.cttz.nxv8i16() +declare @llvm.cttz.nxv4i32() +declare @llvm.cttz.nxv2i64() diff --git a/llvm/test/CodeGen/AArch64/sve-fixed-length-bit-counting.ll b/llvm/test/CodeGen/AArch64/sve-fixed-length-bit-counting.ll new file mode 100644 index 0000000..74344f1 --- /dev/null +++ b/llvm/test/CodeGen/AArch64/sve-fixed-length-bit-counting.ll @@ -0,0 +1,1128 @@ +; RUN: llc -aarch64-sve-vector-bits-min=128 -asm-verbose=0 < %s | FileCheck %s -check-prefix=NO_SVE +; RUN: llc -aarch64-sve-vector-bits-min=256 -asm-verbose=0 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_EQ_256 +; RUN: llc -aarch64-sve-vector-bits-min=384 -asm-verbose=0 < %s | FileCheck %s -check-prefixes=CHECK +; RUN: llc -aarch64-sve-vector-bits-min=512 -asm-verbose=0 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_512 +; RUN: llc -aarch64-sve-vector-bits-min=640 -asm-verbose=0 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_512 +; RUN: llc -aarch64-sve-vector-bits-min=768 -asm-verbose=0 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_512 +; RUN: llc -aarch64-sve-vector-bits-min=896 -asm-verbose=0 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_512 +; RUN: llc -aarch64-sve-vector-bits-min=1024 -asm-verbose=0 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_512,VBITS_GE_1024 +; RUN: llc -aarch64-sve-vector-bits-min=1152 -asm-verbose=0 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_512,VBITS_GE_1024 +; RUN: llc -aarch64-sve-vector-bits-min=1280 -asm-verbose=0 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_512,VBITS_GE_1024 +; RUN: llc -aarch64-sve-vector-bits-min=1408 -asm-verbose=0 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_512,VBITS_GE_1024 +; RUN: llc -aarch64-sve-vector-bits-min=1536 -asm-verbose=0 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_512,VBITS_GE_1024 +; RUN: llc -aarch64-sve-vector-bits-min=1664 -asm-verbose=0 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_512,VBITS_GE_1024 +; RUN: llc -aarch64-sve-vector-bits-min=1792 -asm-verbose=0 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_512,VBITS_GE_1024 +; RUN: llc -aarch64-sve-vector-bits-min=1920 -asm-verbose=0 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_512,VBITS_GE_1024 +; RUN: llc -aarch64-sve-vector-bits-min=2048 -asm-verbose=0 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_512,VBITS_GE_1024,VBITS_GE_2048 + +target triple = "aarch64-unknown-linux-gnu" + +; Don't use SVE when its registers are no bigger than NEON. +; NO_SVE-NOT: ptrue + +; +; CLZ +; + +; Don't use SVE for 64-bit vectors. +define <8 x i8> @ctlz_v8i8(<8 x i8> %op) #0 { +; CHECK-LABEL: ctlz_v8i8: +; CHECK: clz v0.8b, v0.8b +; CHECK-NEXT: ret + %res = call <8 x i8> @llvm.ctlz.v8i8(<8 x i8> %op) + ret <8 x i8> %res +} + +; Don't use SVE for 128-bit vectors. +define <16 x i8> @ctlz_v16i8(<16 x i8> %op) #0 { +; CHECK-LABEL: ctlz_v16i8: +; CHECK: clz v0.16b, v0.16b +; CHECK-NEXT: ret + %res = call <16 x i8> @llvm.ctlz.v16i8(<16 x i8> %op) + ret <16 x i8> %res +} + +define void @ctlz_v32i8(<32 x i8>* %a) #0 { +; CHECK-LABEL: ctlz_v32i8: +; CHECK: ptrue [[PG:p[0-9]+]].b, vl32 +; CHECK-NEXT: ld1b { [[OP:z[0-9]+]].b }, [[PG]]/z, [x0] +; CHECK-NEXT: clz [[RES:z[0-9]+]].b, [[PG]]/m, [[OP]].b +; CHECK-NEXT: st1b { [[RES]].b }, [[PG]], [x0] +; CHECK-NEXT: ret + %op = load <32 x i8>, <32 x i8>* %a + %res = call <32 x i8> @llvm.ctlz.v32i8(<32 x i8> %op) + store <32 x i8> %res, <32 x i8>* %a + ret void +} + +define void @ctlz_v64i8(<64 x i8>* %a) #0 { +; CHECK-LABEL: ctlz_v64i8: +; VBITS_GE_512: ptrue [[PG:p[0-9]+]].b, vl64 +; VBITS_GE_512-NEXT: ld1b { [[OP:z[0-9]+]].b }, [[PG]]/z, [x0] +; VBITS_GE_512-NEXT: clz [[RES:z[0-9]+]].b, [[PG]]/m, [[OP]].b +; VBITS_GE_512-NEXT: st1b { [[RES]].b }, [[PG]], [x0] +; VBITS_GE_512-NEXT: ret +; +; Ensure sensible type legalisation. +; VBITS_EQ_256-DAG: ptrue [[PG:p[0-9]+]].b, vl32 +; VBITS_EQ_256-DAG: mov w[[A:[0-9]+]], #32 +; VBITS_EQ_256-DAG: ld1b { [[OP_LO:z[0-9]+]].b }, [[PG]]/z, [x0] +; VBITS_EQ_256-DAG: ld1b { [[OP_HI:z[0-9]+]].b }, [[PG]]/z, [x0, x[[A]]] +; VBITS_EQ_256-DAG: clz [[RES_LO:z[0-9]+]].b, [[PG]]/m, [[OP_LO]].b +; VBITS_EQ_256-DAG: clz [[RES_HI:z[0-9]+]].b, [[PG]]/m, [[OP_HI]].b +; VBITS_EQ_256-DAG: st1b { [[RES_LO]].b }, [[PG]], [x0] +; VBITS_EQ_256-DAG: st1b { [[RES_HI]].b }, [[PG]], [x0, x[[A]]] +; VBITS_EQ_256-NEXT: ret + %op = load <64 x i8>, <64 x i8>* %a + %res = call <64 x i8> @llvm.ctlz.v64i8(<64 x i8> %op) + store <64 x i8> %res, <64 x i8>* %a + ret void +} + +define void @ctlz_v128i8(<128 x i8>* %a) #0 { +; CHECK-LABEL: ctlz_v128i8: +; VBITS_GE_1024: ptrue [[PG:p[0-9]+]].b, vl128 +; VBITS_GE_1024-NEXT: ld1b { [[OP:z[0-9]+]].b }, [[PG]]/z, [x0] +; VBITS_GE_1024-NEXT: clz [[RES:z[0-9]+]].b, [[PG]]/m, [[OP]].b +; VBITS_GE_1024-NEXT: st1b { [[RES]].b }, [[PG]], [x0] +; VBITS_GE_1024-NEXT: ret + %op = load <128 x i8>, <128 x i8>* %a + %res = call <128 x i8> @llvm.ctlz.v128i8(<128 x i8> %op) + store <128 x i8> %res, <128 x i8>* %a + ret void +} + +define void @ctlz_v256i8(<256 x i8>* %a) #0 { +; CHECK-LABEL: ctlz_v256i8: +; VBITS_GE_2048: ptrue [[PG:p[0-9]+]].b, vl256 +; VBITS_GE_2048-NEXT: ld1b { [[OP:z[0-9]+]].b }, [[PG]]/z, [x0] +; VBITS_GE_2048-NEXT: clz [[RES:z[0-9]+]].b, [[PG]]/m, [[OP]].b +; VBITS_GE_2048-NEXT: st1b { [[RES]].b }, [[PG]], [x0] +; VBITS_GE_2048-NEXT: ret + %op = load <256 x i8>, <256 x i8>* %a + %res = call <256 x i8> @llvm.ctlz.v256i8(<256 x i8> %op) + store <256 x i8> %res, <256 x i8>* %a + ret void +} + +; Don't use SVE for 64-bit vectors. +define <4 x i16> @ctlz_v4i16(<4 x i16> %op) #0 { +; CHECK-LABEL: ctlz_v4i16: +; CHECK: clz v0.4h, v0.4h +; CHECK-NEXT: ret + %res = call <4 x i16> @llvm.ctlz.v4i16(<4 x i16> %op) + ret <4 x i16> %res +} + +; Don't use SVE for 128-bit vectors. +define <8 x i16> @ctlz_v8i16(<8 x i16> %op) #0 { +; CHECK-LABEL: ctlz_v8i16: +; CHECK: clz v0.8h, v0.8h +; CHECK-NEXT: ret + %res = call <8 x i16> @llvm.ctlz.v8i16(<8 x i16> %op) + ret <8 x i16> %res +} + +define void @ctlz_v16i16(<16 x i16>* %a) #0 { +; CHECK-LABEL: ctlz_v16i16: +; CHECK: ptrue [[PG:p[0-9]+]].h, vl16 +; CHECK-NEXT: ld1h { [[OP:z[0-9]+]].h }, [[PG]]/z, [x0] +; CHECK-NEXT: clz [[RES:z[0-9]+]].h, [[PG]]/m, [[OP]].h +; CHECK-NEXT: st1h { [[RES]].h }, [[PG]], [x0] +; CHECK-NEXT: ret + %op = load <16 x i16>, <16 x i16>* %a + %res = call <16 x i16> @llvm.ctlz.v16i16(<16 x i16> %op) + store <16 x i16> %res, <16 x i16>* %a + ret void +} + +define void @ctlz_v32i16(<32 x i16>* %a) #0 { +; CHECK-LABEL: ctlz_v32i16: +; VBITS_GE_512: ptrue [[PG:p[0-9]+]].h, vl32 +; VBITS_GE_512-NEXT: ld1h { [[OP:z[0-9]+]].h }, [[PG]]/z, [x0] +; VBITS_GE_512-NEXT: clz [[RES:z[0-9]+]].h, [[PG]]/m, [[OP]].h +; VBITS_GE_512-NEXT: st1h { [[RES]].h }, [[PG]], [x0] +; VBITS_GE_512-NEXT: ret + +; Ensure sensible type legalisation. +; VBITS_EQ_256-DAG: ptrue [[PG:p[0-9]+]].h, vl16 +; VBITS_EQ_256-DAG: add x[[A_HI:[0-9]+]], x0, #32 +; VBITS_EQ_256-DAG: ld1h { [[OP_LO:z[0-9]+]].h }, [[PG]]/z, [x0] +; VBITS_EQ_256-DAG: ld1h { [[OP_HI:z[0-9]+]].h }, [[PG]]/z, [x[[A_HI]]] +; VBITS_EQ_256-DAG: clz [[RES_LO:z[0-9]+]].h, [[PG]]/m, [[OP_LO]].h +; VBITS_EQ_256-DAG: clz [[RES_HI:z[0-9]+]].h, [[PG]]/m, [[OP_HI]].h +; VBITS_EQ_256-DAG: st1h { [[RES_LO]].h }, [[PG]], [x0] +; VBITS_EQ_256-DAG: st1h { [[RES_HI]].h }, [[PG]], [x[[A_HI]] +; VBITS_EQ_256-NEXT: ret + %op = load <32 x i16>, <32 x i16>* %a + %res = call <32 x i16> @llvm.ctlz.v32i16(<32 x i16> %op) + store <32 x i16> %res, <32 x i16>* %a + ret void +} + +define void @ctlz_v64i16(<64 x i16>* %a) #0 { +; CHECK-LABEL: ctlz_v64i16: +; VBITS_GE_1024: ptrue [[PG:p[0-9]+]].h, vl64 +; VBITS_GE_1024-NEXT: ld1h { [[OP:z[0-9]+]].h }, [[PG]]/z, [x0] +; VBITS_GE_1024-NEXT: clz [[RES:z[0-9]+]].h, [[PG]]/m, [[OP]].h +; VBITS_GE_1024-NEXT: st1h { [[RES]].h }, [[PG]], [x0] +; VBITS_GE_1024-NEXT: ret + %op = load <64 x i16>, <64 x i16>* %a + %res = call <64 x i16> @llvm.ctlz.v64i16(<64 x i16> %op) + store <64 x i16> %res, <64 x i16>* %a + ret void +} + +define void @ctlz_v128i16(<128 x i16>* %a) #0 { +; CHECK-LABEL: ctlz_v128i16: +; VBITS_GE_2048: ptrue [[PG:p[0-9]+]].h, vl128 +; VBITS_GE_2048-NEXT: ld1h { [[OP:z[0-9]+]].h }, [[PG]]/z, [x0] +; VBITS_GE_2048-NEXT: clz [[RES:z[0-9]+]].h, [[PG]]/m, [[OP]].h +; VBITS_GE_2048-NEXT: st1h { [[RES]].h }, [[PG]], [x0] +; VBITS_GE_2048-NEXT: ret + %op = load <128 x i16>, <128 x i16>* %a + %res = call <128 x i16> @llvm.ctlz.v128i16(<128 x i16> %op) + store <128 x i16> %res, <128 x i16>* %a + ret void +} + +; Don't use SVE for 64-bit vectors. +define <2 x i32> @ctlz_v2i32(<2 x i32> %op) #0 { +; CHECK-LABEL: ctlz_v2i32: +; CHECK: clz v0.2s, v0.2s +; CHECK-NEXT: ret + %res = call <2 x i32> @llvm.ctlz.v2i32(<2 x i32> %op) + ret <2 x i32> %res +} + +; Don't use SVE for 128-bit vectors. +define <4 x i32> @ctlz_v4i32(<4 x i32> %op) #0 { +; CHECK-LABEL: ctlz_v4i32: +; CHECK: clz v0.4s, v0.4s +; CHECK-NEXT: ret + %res = call <4 x i32> @llvm.ctlz.v4i32(<4 x i32> %op) + ret <4 x i32> %res +} + +define void @ctlz_v8i32(<8 x i32>* %a) #0 { +; CHECK-LABEL: ctlz_v8i32: +; CHECK: ptrue [[PG:p[0-9]+]].s, vl8 +; CHECK-NEXT: ld1w { [[OP:z[0-9]+]].s }, [[PG]]/z, [x0] +; CHECK-NEXT: clz [[RES:z[0-9]+]].s, [[PG]]/m, [[OP]].s +; CHECK-NEXT: st1w { [[RES]].s }, [[PG]], [x0] +; CHECK-NEXT: ret + %op = load <8 x i32>, <8 x i32>* %a + %res = call <8 x i32> @llvm.ctlz.v8i32(<8 x i32> %op) + store <8 x i32> %res, <8 x i32>* %a + ret void +} + +define void @ctlz_v16i32(<16 x i32>* %a) #0 { +; CHECK-LABEL: ctlz_v16i32: +; VBITS_GE_512: ptrue [[PG:p[0-9]+]].s, vl16 +; VBITS_GE_512-NEXT: ld1w { [[OP:z[0-9]+]].s }, [[PG]]/z, [x0] +; VBITS_GE_512-NEXT: clz [[RES:z[0-9]+]].s, [[PG]]/m, [[OP]].s +; VBITS_GE_512-NEXT: st1w { [[RES]].s }, [[PG]], [x0] +; VBITS_GE_512-NEXT: ret + +; Ensure sensible type legalisation. +; VBITS_EQ_256-DAG: ptrue [[PG:p[0-9]+]].s, vl8 +; VBITS_EQ_256-DAG: add x[[A_HI:[0-9]+]], x0, #32 +; VBITS_EQ_256-DAG: ld1w { [[OP_LO:z[0-9]+]].s }, [[PG]]/z, [x0] +; VBITS_EQ_256-DAG: ld1w { [[OP_HI:z[0-9]+]].s }, [[PG]]/z, [x[[A_HI]]] +; VBITS_EQ_256-DAG: clz [[RES_LO:z[0-9]+]].s, [[PG]]/m, [[OP_LO]].s +; VBITS_EQ_256-DAG: clz [[RES_HI:z[0-9]+]].s, [[PG]]/m, [[OP_HI]].s +; VBITS_EQ_256-DAG: st1w { [[RES_LO]].s }, [[PG]], [x0] +; VBITS_EQ_256-DAG: st1w { [[RES_HI]].s }, [[PG]], [x[[A_HI]] +; VBITS_EQ_256-NEXT: ret + %op = load <16 x i32>, <16 x i32>* %a + %res = call <16 x i32> @llvm.ctlz.v16i32(<16 x i32> %op) + store <16 x i32> %res, <16 x i32>* %a + ret void +} + +define void @ctlz_v32i32(<32 x i32>* %a) #0 { +; CHECK-LABEL: ctlz_v32i32: +; VBITS_GE_1024: ptrue [[PG:p[0-9]+]].s, vl32 +; VBITS_GE_1024-NEXT: ld1w { [[OP:z[0-9]+]].s }, [[PG]]/z, [x0] +; VBITS_GE_1024-NEXT: clz [[RES:z[0-9]+]].s, [[PG]]/m, [[OP]].s +; VBITS_GE_1024-NEXT: st1w { [[RES]].s }, [[PG]], [x0] +; VBITS_GE_1024-NEXT: ret + %op = load <32 x i32>, <32 x i32>* %a + %res = call <32 x i32> @llvm.ctlz.v32i32(<32 x i32> %op) + store <32 x i32> %res, <32 x i32>* %a + ret void +} + +define void @ctlz_v64i32(<64 x i32>* %a) #0 { +; CHECK-LABEL: ctlz_v64i32: +; VBITS_GE_2048: ptrue [[PG:p[0-9]+]].s, vl64 +; VBITS_GE_2048-NEXT: ld1w { [[OP:z[0-9]+]].s }, [[PG]]/z, [x0] +; VBITS_GE_2048-NEXT: clz [[RES:z[0-9]+]].s, [[PG]]/m, [[OP]].s +; VBITS_GE_2048-NEXT: st1w { [[RES]].s }, [[PG]], [x0] +; VBITS_GE_2048-NEXT: ret + %op = load <64 x i32>, <64 x i32>* %a + %res = call <64 x i32> @llvm.ctlz.v64i32(<64 x i32> %op) + store <64 x i32> %res, <64 x i32>* %a + ret void +} + +define <1 x i64> @ctlz_v1i64(<1 x i64> %op) #0 { +; CHECK-LABEL: ctlz_v1i64: +; CHECK: ptrue [[PG:p[0-9]+]].d, vl1 +; CHECK-NEXT: clz z0.d, [[PG]]/m, z0.d +; CHECK-NEXT: ret + %res = call <1 x i64> @llvm.ctlz.v1i64(<1 x i64> %op) + ret <1 x i64> %res +} + +define <2 x i64> @ctlz_v2i64(<2 x i64> %op) #0 { +; CHECK-LABEL: ctlz_v2i64: +; CHECK: ptrue [[PG:p[0-9]+]].d, vl2 +; CHECK-NEXT: clz z0.d, [[PG]]/m, z0.d +; CHECK-NEXT: ret + %res = call <2 x i64> @llvm.ctlz.v2i64(<2 x i64> %op) + ret <2 x i64> %res +} + +define void @ctlz_v4i64(<4 x i64>* %a) #0 { +; CHECK-LABEL: ctlz_v4i64: +; CHECK: ptrue [[PG:p[0-9]+]].d, vl4 +; CHECK-NEXT: ld1d { [[OP:z[0-9]+]].d }, [[PG]]/z, [x0] +; CHECK-NEXT: clz [[RES:z[0-9]+]].d, [[PG]]/m, [[OP]].d +; CHECK-NEXT: st1d { [[RES]].d }, [[PG]], [x0] +; CHECK-NEXT: ret + %op = load <4 x i64>, <4 x i64>* %a + %res = call <4 x i64> @llvm.ctlz.v4i64(<4 x i64> %op) + store <4 x i64> %res, <4 x i64>* %a + ret void +} + +define void @ctlz_v8i64(<8 x i64>* %a) #0 { +; CHECK-LABEL: ctlz_v8i64: +; VBITS_GE_512: ptrue [[PG:p[0-9]+]].d, vl8 +; VBITS_GE_512-NEXT: ld1d { [[OP:z[0-9]+]].d }, [[PG]]/z, [x0] +; VBITS_GE_512-NEXT: clz [[RES:z[0-9]+]].d, [[PG]]/m, [[OP]].d +; VBITS_GE_512-NEXT: st1d { [[RES]].d }, [[PG]], [x0] +; VBITS_GE_512-NEXT: ret + +; Ensure sensible type legalisation. +; VBITS_EQ_256-DAG: ptrue [[PG:p[0-9]+]].d, vl4 +; VBITS_EQ_256-DAG: add x[[A_HI:[0-9]+]], x0, #32 +; VBITS_EQ_256-DAG: ld1d { [[OP_LO:z[0-9]+]].d }, [[PG]]/z, [x0] +; VBITS_EQ_256-DAG: ld1d { [[OP_HI:z[0-9]+]].d }, [[PG]]/z, [x[[A_HI]]] +; VBITS_EQ_256-DAG: clz [[RES_LO:z[0-9]+]].d, [[PG]]/m, [[OP_LO]].d +; VBITS_EQ_256-DAG: clz [[RES_HI:z[0-9]+]].d, [[PG]]/m, [[OP_HI]].d +; VBITS_EQ_256-DAG: st1d { [[RES_LO]].d }, [[PG]], [x0] +; VBITS_EQ_256-DAG: st1d { [[RES_HI]].d }, [[PG]], [x[[A_HI]] +; VBITS_EQ_256-NEXT: ret + %op = load <8 x i64>, <8 x i64>* %a + %res = call <8 x i64> @llvm.ctlz.v8i64(<8 x i64> %op) + store <8 x i64> %res, <8 x i64>* %a + ret void +} + +define void @ctlz_v16i64(<16 x i64>* %a) #0 { +; CHECK-LABEL: ctlz_v16i64: +; VBITS_GE_1024: ptrue [[PG:p[0-9]+]].d, vl16 +; VBITS_GE_1024-NEXT: ld1d { [[OP:z[0-9]+]].d }, [[PG]]/z, [x0] +; VBITS_GE_1024-NEXT: clz [[RES:z[0-9]+]].d, [[PG]]/m, [[OP]].d +; VBITS_GE_1024-NEXT: st1d { [[RES]].d }, [[PG]], [x0] +; VBITS_GE_1024-NEXT: ret + %op = load <16 x i64>, <16 x i64>* %a + %res = call <16 x i64> @llvm.ctlz.v16i64(<16 x i64> %op) + store <16 x i64> %res, <16 x i64>* %a + ret void +} + +define void @ctlz_v32i64(<32 x i64>* %a) #0 { +; CHECK-LABEL: ctlz_v32i64: +; VBITS_GE_2048: ptrue [[PG:p[0-9]+]].d, vl32 +; VBITS_GE_2048-NEXT: ld1d { [[OP:z[0-9]+]].d }, [[PG]]/z, [x0] +; VBITS_GE_2048-NEXT: clz [[RES:z[0-9]+]].d, [[PG]]/m, [[OP]].d +; VBITS_GE_2048-NEXT: st1d { [[RES]].d }, [[PG]], [x0] +; VBITS_GE_2048-NEXT: ret + %op = load <32 x i64>, <32 x i64>* %a + %res = call <32 x i64> @llvm.ctlz.v32i64(<32 x i64> %op) + store <32 x i64> %res, <32 x i64>* %a + ret void +} + +; +; CNT +; + +; Don't use SVE for 64-bit vectors. +define <8 x i8> @ctpop_v8i8(<8 x i8> %op) #0 { +; CHECK-LABEL: ctpop_v8i8: +; CHECK: cnt v0.8b, v0.8b +; CHECK-NEXT: ret + %res = call <8 x i8> @llvm.ctpop.v8i8(<8 x i8> %op) + ret <8 x i8> %res +} + +; Don't use SVE for 128-bit vectors. +define <16 x i8> @ctpop_v16i8(<16 x i8> %op) #0 { +; CHECK-LABEL: ctpop_v16i8: +; CHECK: cnt v0.16b, v0.16b +; CHECK-NEXT: ret + %res = call <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %op) + ret <16 x i8> %res +} + +define void @ctpop_v32i8(<32 x i8>* %a) #0 { +; CHECK-LABEL: ctpop_v32i8: +; CHECK: ptrue [[PG:p[0-9]+]].b, vl32 +; CHECK-NEXT: ld1b { [[OP:z[0-9]+]].b }, [[PG]]/z, [x0] +; CHECK-NEXT: cnt [[RES:z[0-9]+]].b, [[PG]]/m, [[OP]].b +; CHECK-NEXT: st1b { [[RES]].b }, [[PG]], [x0] +; CHECK-NEXT: ret + %op = load <32 x i8>, <32 x i8>* %a + %res = call <32 x i8> @llvm.ctpop.v32i8(<32 x i8> %op) + store <32 x i8> %res, <32 x i8>* %a + ret void +} + +define void @ctpop_v64i8(<64 x i8>* %a) #0 { +; CHECK-LABEL: ctpop_v64i8: +; VBITS_GE_512: ptrue [[PG:p[0-9]+]].b, vl64 +; VBITS_GE_512-NEXT: ld1b { [[OP:z[0-9]+]].b }, [[PG]]/z, [x0] +; VBITS_GE_512-NEXT: cnt [[RES:z[0-9]+]].b, [[PG]]/m, [[OP]].b +; VBITS_GE_512-NEXT: st1b { [[RES]].b }, [[PG]], [x0] +; VBITS_GE_512-NEXT: ret +; +; Ensure sensible type legalisation. +; VBITS_EQ_256-DAG: ptrue [[PG:p[0-9]+]].b, vl32 +; VBITS_EQ_256-DAG: mov w[[A:[0-9]+]], #32 +; VBITS_EQ_256-DAG: ld1b { [[OP_LO:z[0-9]+]].b }, [[PG]]/z, [x0] +; VBITS_EQ_256-DAG: ld1b { [[OP_HI:z[0-9]+]].b }, [[PG]]/z, [x0, x[[A]]] +; VBITS_EQ_256-DAG: cnt [[RES_LO:z[0-9]+]].b, [[PG]]/m, [[OP_LO]].b +; VBITS_EQ_256-DAG: cnt [[RES_HI:z[0-9]+]].b, [[PG]]/m, [[OP_HI]].b +; VBITS_EQ_256-DAG: st1b { [[RES_LO]].b }, [[PG]], [x0] +; VBITS_EQ_256-DAG: st1b { [[RES_HI]].b }, [[PG]], [x0, x[[A]]] +; VBITS_EQ_256-NEXT: ret + %op = load <64 x i8>, <64 x i8>* %a + %res = call <64 x i8> @llvm.ctpop.v64i8(<64 x i8> %op) + store <64 x i8> %res, <64 x i8>* %a + ret void +} + +define void @ctpop_v128i8(<128 x i8>* %a) #0 { +; CHECK-LABEL: ctpop_v128i8: +; VBITS_GE_1024: ptrue [[PG:p[0-9]+]].b, vl128 +; VBITS_GE_1024-NEXT: ld1b { [[OP:z[0-9]+]].b }, [[PG]]/z, [x0] +; VBITS_GE_1024-NEXT: cnt [[RES:z[0-9]+]].b, [[PG]]/m, [[OP]].b +; VBITS_GE_1024-NEXT: st1b { [[RES]].b }, [[PG]], [x0] +; VBITS_GE_1024-NEXT: ret + %op = load <128 x i8>, <128 x i8>* %a + %res = call <128 x i8> @llvm.ctpop.v128i8(<128 x i8> %op) + store <128 x i8> %res, <128 x i8>* %a + ret void +} + +define void @ctpop_v256i8(<256 x i8>* %a) #0 { +; CHECK-LABEL: ctpop_v256i8: +; VBITS_GE_2048: ptrue [[PG:p[0-9]+]].b, vl256 +; VBITS_GE_2048-NEXT: ld1b { [[OP:z[0-9]+]].b }, [[PG]]/z, [x0] +; VBITS_GE_2048-NEXT: cnt [[RES:z[0-9]+]].b, [[PG]]/m, [[OP]].b +; VBITS_GE_2048-NEXT: st1b { [[RES]].b }, [[PG]], [x0] +; VBITS_GE_2048-NEXT: ret + %op = load <256 x i8>, <256 x i8>* %a + %res = call <256 x i8> @llvm.ctpop.v256i8(<256 x i8> %op) + store <256 x i8> %res, <256 x i8>* %a + ret void +} + +; Don't use SVE for 64-bit vectors. +define <4 x i16> @ctpop_v4i16(<4 x i16> %op) #0 { +; CHECK-LABEL: ctpop_v4i16: +; CHECK: cnt v0.8b, v0.8b +; CHECK-NEXT: uaddlp v0.4h, v0.8b +; CHECK-NEXT: ret + %res = call <4 x i16> @llvm.ctpop.v4i16(<4 x i16> %op) + ret <4 x i16> %res +} + +; Don't use SVE for 128-bit vectors. +define <8 x i16> @ctpop_v8i16(<8 x i16> %op) #0 { +; CHECK-LABEL: ctpop_v8i16: +; CHECK: cnt v0.16b, v0.16b +; CHECK-NEXT: uaddlp v0.8h, v0.16b +; CHECK-NEXT: ret + %res = call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %op) + ret <8 x i16> %res +} + +define void @ctpop_v16i16(<16 x i16>* %a) #0 { +; CHECK-LABEL: ctpop_v16i16: +; CHECK: ptrue [[PG:p[0-9]+]].h, vl16 +; CHECK-NEXT: ld1h { [[OP:z[0-9]+]].h }, [[PG]]/z, [x0] +; CHECK-NEXT: cnt [[RES:z[0-9]+]].h, [[PG]]/m, [[OP]].h +; CHECK-NEXT: st1h { [[RES]].h }, [[PG]], [x0] +; CHECK-NEXT: ret + %op = load <16 x i16>, <16 x i16>* %a + %res = call <16 x i16> @llvm.ctpop.v16i16(<16 x i16> %op) + store <16 x i16> %res, <16 x i16>* %a + ret void +} + +define void @ctpop_v32i16(<32 x i16>* %a) #0 { +; CHECK-LABEL: ctpop_v32i16: +; VBITS_GE_512: ptrue [[PG:p[0-9]+]].h, vl32 +; VBITS_GE_512-NEXT: ld1h { [[OP:z[0-9]+]].h }, [[PG]]/z, [x0] +; VBITS_GE_512-NEXT: cnt [[RES:z[0-9]+]].h, [[PG]]/m, [[OP]].h +; VBITS_GE_512-NEXT: st1h { [[RES]].h }, [[PG]], [x0] +; VBITS_GE_512-NEXT: ret + +; Ensure sensible type legalisation. +; VBITS_EQ_256-DAG: ptrue [[PG:p[0-9]+]].h, vl16 +; VBITS_EQ_256-DAG: add x[[A_HI:[0-9]+]], x0, #32 +; VBITS_EQ_256-DAG: ld1h { [[OP_LO:z[0-9]+]].h }, [[PG]]/z, [x0] +; VBITS_EQ_256-DAG: ld1h { [[OP_HI:z[0-9]+]].h }, [[PG]]/z, [x[[A_HI]]] +; VBITS_EQ_256-DAG: cnt [[RES_LO:z[0-9]+]].h, [[PG]]/m, [[OP_LO]].h +; VBITS_EQ_256-DAG: cnt [[RES_HI:z[0-9]+]].h, [[PG]]/m, [[OP_HI]].h +; VBITS_EQ_256-DAG: st1h { [[RES_LO]].h }, [[PG]], [x0] +; VBITS_EQ_256-DAG: st1h { [[RES_HI]].h }, [[PG]], [x[[A_HI]] +; VBITS_EQ_256-NEXT: ret + %op = load <32 x i16>, <32 x i16>* %a + %res = call <32 x i16> @llvm.ctpop.v32i16(<32 x i16> %op) + store <32 x i16> %res, <32 x i16>* %a + ret void +} + +define void @ctpop_v64i16(<64 x i16>* %a) #0 { +; CHECK-LABEL: ctpop_v64i16: +; VBITS_GE_1024: ptrue [[PG:p[0-9]+]].h, vl64 +; VBITS_GE_1024-NEXT: ld1h { [[OP:z[0-9]+]].h }, [[PG]]/z, [x0] +; VBITS_GE_1024-NEXT: cnt [[RES:z[0-9]+]].h, [[PG]]/m, [[OP]].h +; VBITS_GE_1024-NEXT: st1h { [[RES]].h }, [[PG]], [x0] +; VBITS_GE_1024-NEXT: ret + %op = load <64 x i16>, <64 x i16>* %a + %res = call <64 x i16> @llvm.ctpop.v64i16(<64 x i16> %op) + store <64 x i16> %res, <64 x i16>* %a + ret void +} + +define void @ctpop_v128i16(<128 x i16>* %a) #0 { +; CHECK-LABEL: ctpop_v128i16: +; VBITS_GE_2048: ptrue [[PG:p[0-9]+]].h, vl128 +; VBITS_GE_2048-NEXT: ld1h { [[OP:z[0-9]+]].h }, [[PG]]/z, [x0] +; VBITS_GE_2048-NEXT: cnt [[RES:z[0-9]+]].h, [[PG]]/m, [[OP]].h +; VBITS_GE_2048-NEXT: st1h { [[RES]].h }, [[PG]], [x0] +; VBITS_GE_2048-NEXT: ret + %op = load <128 x i16>, <128 x i16>* %a + %res = call <128 x i16> @llvm.ctpop.v128i16(<128 x i16> %op) + store <128 x i16> %res, <128 x i16>* %a + ret void +} + +; Don't use SVE for 64-bit vectors. +define <2 x i32> @ctpop_v2i32(<2 x i32> %op) #0 { +; CHECK-LABEL: ctpop_v2i32: +; CHECK: cnt v0.8b, v0.8b +; CHECK-NEXT: uaddlp v0.4h, v0.8b +; CHECK-NEXT: uaddlp v0.2s, v0.4h +; CHECK-NEXT: ret + %res = call <2 x i32> @llvm.ctpop.v2i32(<2 x i32> %op) + ret <2 x i32> %res +} + +; Don't use SVE for 128-bit vectors. +define <4 x i32> @ctpop_v4i32(<4 x i32> %op) #0 { +; CHECK-LABEL: ctpop_v4i32: +; CHECK: cnt v0.16b, v0.16b +; CHECK-NEXT: uaddlp v0.8h, v0.16b +; CHECK-NEXT: uaddlp v0.4s, v0.8h +; CHECK-NEXT: ret + %res = call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %op) + ret <4 x i32> %res +} + +define void @ctpop_v8i32(<8 x i32>* %a) #0 { +; CHECK-LABEL: ctpop_v8i32: +; CHECK: ptrue [[PG:p[0-9]+]].s, vl8 +; CHECK-NEXT: ld1w { [[OP:z[0-9]+]].s }, [[PG]]/z, [x0] +; CHECK-NEXT: cnt [[RES:z[0-9]+]].s, [[PG]]/m, [[OP]].s +; CHECK-NEXT: st1w { [[RES]].s }, [[PG]], [x0] +; CHECK-NEXT: ret + %op = load <8 x i32>, <8 x i32>* %a + %res = call <8 x i32> @llvm.ctpop.v8i32(<8 x i32> %op) + store <8 x i32> %res, <8 x i32>* %a + ret void +} + +define void @ctpop_v16i32(<16 x i32>* %a) #0 { +; CHECK-LABEL: ctpop_v16i32: +; VBITS_GE_512: ptrue [[PG:p[0-9]+]].s, vl16 +; VBITS_GE_512-NEXT: ld1w { [[OP:z[0-9]+]].s }, [[PG]]/z, [x0] +; VBITS_GE_512-NEXT: cnt [[RES:z[0-9]+]].s, [[PG]]/m, [[OP]].s +; VBITS_GE_512-NEXT: st1w { [[RES]].s }, [[PG]], [x0] +; VBITS_GE_512-NEXT: ret + +; Ensure sensible type legalisation. +; VBITS_EQ_256-DAG: ptrue [[PG:p[0-9]+]].s, vl8 +; VBITS_EQ_256-DAG: add x[[A_HI:[0-9]+]], x0, #32 +; VBITS_EQ_256-DAG: ld1w { [[OP_LO:z[0-9]+]].s }, [[PG]]/z, [x0] +; VBITS_EQ_256-DAG: ld1w { [[OP_HI:z[0-9]+]].s }, [[PG]]/z, [x[[A_HI]]] +; VBITS_EQ_256-DAG: cnt [[RES_LO:z[0-9]+]].s, [[PG]]/m, [[OP_LO]].s +; VBITS_EQ_256-DAG: cnt [[RES_HI:z[0-9]+]].s, [[PG]]/m, [[OP_HI]].s +; VBITS_EQ_256-DAG: st1w { [[RES_LO]].s }, [[PG]], [x0] +; VBITS_EQ_256-DAG: st1w { [[RES_HI]].s }, [[PG]], [x[[A_HI]] +; VBITS_EQ_256-NEXT: ret + %op = load <16 x i32>, <16 x i32>* %a + %res = call <16 x i32> @llvm.ctpop.v16i32(<16 x i32> %op) + store <16 x i32> %res, <16 x i32>* %a + ret void +} + +define void @ctpop_v32i32(<32 x i32>* %a) #0 { +; CHECK-LABEL: ctpop_v32i32: +; VBITS_GE_1024: ptrue [[PG:p[0-9]+]].s, vl32 +; VBITS_GE_1024-NEXT: ld1w { [[OP:z[0-9]+]].s }, [[PG]]/z, [x0] +; VBITS_GE_1024-NEXT: cnt [[RES:z[0-9]+]].s, [[PG]]/m, [[OP]].s +; VBITS_GE_1024-NEXT: st1w { [[RES]].s }, [[PG]], [x0] +; VBITS_GE_1024-NEXT: ret + %op = load <32 x i32>, <32 x i32>* %a + %res = call <32 x i32> @llvm.ctpop.v32i32(<32 x i32> %op) + store <32 x i32> %res, <32 x i32>* %a + ret void +} + +define void @ctpop_v64i32(<64 x i32>* %a) #0 { +; CHECK-LABEL: ctpop_v64i32: +; VBITS_GE_2048: ptrue [[PG:p[0-9]+]].s, vl64 +; VBITS_GE_2048-NEXT: ld1w { [[OP:z[0-9]+]].s }, [[PG]]/z, [x0] +; VBITS_GE_2048-NEXT: cnt [[RES:z[0-9]+]].s, [[PG]]/m, [[OP]].s +; VBITS_GE_2048-NEXT: st1w { [[RES]].s }, [[PG]], [x0] +; VBITS_GE_2048-NEXT: ret + %op = load <64 x i32>, <64 x i32>* %a + %res = call <64 x i32> @llvm.ctpop.v64i32(<64 x i32> %op) + store <64 x i32> %res, <64 x i32>* %a + ret void +} + +; Don't use SVE for 64-bit vectors. +define <1 x i64> @ctpop_v1i64(<1 x i64> %op) #0 { +; CHECK-LABEL: ctpop_v1i64: +; CHECK: cnt v0.8b, v0.8b +; CHECK-NEXT: uaddlp v0.4h, v0.8b +; CHECK-NEXT: uaddlp v0.2s, v0.4h +; CHECK-NEXT: uaddlp v0.1d, v0.2s +; CHECK-NEXT: ret + %res = call <1 x i64> @llvm.ctpop.v1i64(<1 x i64> %op) + ret <1 x i64> %res +} + +; Don't use SVE for 128-bit vectors. +define <2 x i64> @ctpop_v2i64(<2 x i64> %op) #0 { +; CHECK-LABEL: ctpop_v2i64: +; CHECK: cnt v0.16b, v0.16b +; CHECK-NEXT: uaddlp v0.8h, v0.16b +; CHECK-NEXT: uaddlp v0.4s, v0.8h +; CHECK-NEXT: uaddlp v0.2d, v0.4s +; CHECK-NEXT: ret + %res = call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %op) + ret <2 x i64> %res +} + +define void @ctpop_v4i64(<4 x i64>* %a) #0 { +; CHECK-LABEL: ctpop_v4i64: +; CHECK: ptrue [[PG:p[0-9]+]].d, vl4 +; CHECK-NEXT: ld1d { [[OP:z[0-9]+]].d }, [[PG]]/z, [x0] +; CHECK-NEXT: cnt [[RES:z[0-9]+]].d, [[PG]]/m, [[OP]].d +; CHECK-NEXT: st1d { [[RES]].d }, [[PG]], [x0] +; CHECK-NEXT: ret + %op = load <4 x i64>, <4 x i64>* %a + %res = call <4 x i64> @llvm.ctpop.v4i64(<4 x i64> %op) + store <4 x i64> %res, <4 x i64>* %a + ret void +} + +define void @ctpop_v8i64(<8 x i64>* %a) #0 { +; CHECK-LABEL: ctpop_v8i64: +; VBITS_GE_512: ptrue [[PG:p[0-9]+]].d, vl8 +; VBITS_GE_512-NEXT: ld1d { [[OP:z[0-9]+]].d }, [[PG]]/z, [x0] +; VBITS_GE_512-NEXT: cnt [[RES:z[0-9]+]].d, [[PG]]/m, [[OP]].d +; VBITS_GE_512-NEXT: st1d { [[RES]].d }, [[PG]], [x0] +; VBITS_GE_512-NEXT: ret + +; Ensure sensible type legalisation. +; VBITS_EQ_256-DAG: ptrue [[PG:p[0-9]+]].d, vl4 +; VBITS_EQ_256-DAG: add x[[A_HI:[0-9]+]], x0, #32 +; VBITS_EQ_256-DAG: ld1d { [[OP_LO:z[0-9]+]].d }, [[PG]]/z, [x0] +; VBITS_EQ_256-DAG: ld1d { [[OP_HI:z[0-9]+]].d }, [[PG]]/z, [x[[A_HI]]] +; VBITS_EQ_256-DAG: cnt [[RES_LO:z[0-9]+]].d, [[PG]]/m, [[OP_LO]].d +; VBITS_EQ_256-DAG: cnt [[RES_HI:z[0-9]+]].d, [[PG]]/m, [[OP_HI]].d +; VBITS_EQ_256-DAG: st1d { [[RES_LO]].d }, [[PG]], [x0] +; VBITS_EQ_256-DAG: st1d { [[RES_HI]].d }, [[PG]], [x[[A_HI]] +; VBITS_EQ_256-NEXT: ret + %op = load <8 x i64>, <8 x i64>* %a + %res = call <8 x i64> @llvm.ctpop.v8i64(<8 x i64> %op) + store <8 x i64> %res, <8 x i64>* %a + ret void +} + +define void @ctpop_v16i64(<16 x i64>* %a) #0 { +; CHECK-LABEL: ctpop_v16i64: +; VBITS_GE_1024: ptrue [[PG:p[0-9]+]].d, vl16 +; VBITS_GE_1024-NEXT: ld1d { [[OP:z[0-9]+]].d }, [[PG]]/z, [x0] +; VBITS_GE_1024-NEXT: cnt [[RES:z[0-9]+]].d, [[PG]]/m, [[OP]].d +; VBITS_GE_1024-NEXT: st1d { [[RES]].d }, [[PG]], [x0] +; VBITS_GE_1024-NEXT: ret + %op = load <16 x i64>, <16 x i64>* %a + %res = call <16 x i64> @llvm.ctpop.v16i64(<16 x i64> %op) + store <16 x i64> %res, <16 x i64>* %a + ret void +} + +define void @ctpop_v32i64(<32 x i64>* %a) #0 { +; CHECK-LABEL: ctpop_v32i64: +; VBITS_GE_2048: ptrue [[PG:p[0-9]+]].d, vl32 +; VBITS_GE_2048-NEXT: ld1d { [[OP:z[0-9]+]].d }, [[PG]]/z, [x0] +; VBITS_GE_2048-NEXT: cnt [[RES:z[0-9]+]].d, [[PG]]/m, [[OP]].d +; VBITS_GE_2048-NEXT: st1d { [[RES]].d }, [[PG]], [x0] +; VBITS_GE_2048-NEXT: ret + %op = load <32 x i64>, <32 x i64>* %a + %res = call <32 x i64> @llvm.ctpop.v32i64(<32 x i64> %op) + store <32 x i64> %res, <32 x i64>* %a + ret void +} + +; +; Count trailing zeros +; + +define <8 x i8> @cttz_v8i8(<8 x i8> %op) #0 { +; CHECK-LABEL: cttz_v8i8: +; CHECK: ptrue [[PG:p[0-9]+]].b, vl8 +; CHECK-NEXT: rbit z[[RBIT:[0-9]+]].b, p0/m, z0.b +; CHECK-NEXT: clz v0.8b, v[[RBIT]].8b +; CHECK-NEXT: ret + %res = call <8 x i8> @llvm.cttz.v8i8(<8 x i8> %op) + ret <8 x i8> %res +} + +define <16 x i8> @cttz_v16i8(<16 x i8> %op) #0 { +; CHECK-LABEL: cttz_v16i8: +; CHECK: ptrue [[PG:p[0-9]+]].b, vl16 +; CHECK-NEXT: rbit z[[RBIT:[0-9]+]].b, p0/m, z0.b +; CHECK-NEXT: clz v0.16b, v[[RBIT]].16b +; CHECK-NEXT: ret + %res = call <16 x i8> @llvm.cttz.v16i8(<16 x i8> %op) + ret <16 x i8> %res +} + +define void @cttz_v32i8(<32 x i8>* %a) #0 { +; CHECK-LABEL: cttz_v32i8: +; CHECK: ptrue [[PG:p[0-9]+]].b, vl32 +; CHECK-NEXT: ld1b { [[OP:z[0-9]+]].b }, [[PG]]/z, [x0] +; CHECK-NEXT: rbit [[RBIT:z[0-9]+]].b, [[PG]]/m, [[OP]].b +; CHECK-NEXT: clz [[RES:z[0-9]+]].b, [[PG]]/m, [[RBIT]].b +; CHECK-NEXT: st1b { [[RES]].b }, [[PG]], [x0] +; CHECK-NEXT: ret + %op = load <32 x i8>, <32 x i8>* %a + %res = call <32 x i8> @llvm.cttz.v32i8(<32 x i8> %op) + store <32 x i8> %res, <32 x i8>* %a + ret void +} + +define void @cttz_v64i8(<64 x i8>* %a) #0 { +; CHECK-LABEL: cttz_v64i8: +; VBITS_GE_512: ptrue [[PG:p[0-9]+]].b, vl64 +; VBITS_GE_512-NEXT: ld1b { [[OP:z[0-9]+]].b }, [[PG]]/z, [x0] +; VBITS_GE_512-NEXT: rbit [[RBIT:z[0-9]+]].b, [[PG]]/m, [[OP]].b +; VBITS_GE_512-NEXT: clz [[RES:z[0-9]+]].b, [[PG]]/m, [[RBIT]].b +; VBITS_GE_512-NEXT: st1b { [[RES]].b }, [[PG]], [x0] +; VBITS_GE_512-NEXT: ret +; +; Ensure sensible type legalisation. +; VBITS_EQ_256-DAG: ptrue [[PG:p[0-9]+]].b, vl32 +; VBITS_EQ_256-DAG: mov w[[A:[0-9]+]], #32 +; VBITS_EQ_256-DAG: ld1b { [[OP_LO:z[0-9]+]].b }, [[PG]]/z, [x0] +; VBITS_EQ_256-DAG: ld1b { [[OP_HI:z[0-9]+]].b }, [[PG]]/z, [x0, x[[A]]] +; VBITS_EQ_256-DAG: rbit [[RBIT_LO:z[0-9]+]].b, [[PG]]/m, [[OP_LO]].b +; VBITS_EQ_256-DAG: rbit [[RBIT_HI:z[0-9]+]].b, [[PG]]/m, [[OP_HI]].b +; VBITS_EQ_256-DAG: clz [[RES_LO:z[0-9]+]].b, [[PG]]/m, [[RBIT_LO]].b +; VBITS_EQ_256-DAG: clz [[RES_HI:z[0-9]+]].b, [[PG]]/m, [[RBIT_HI]].b +; VBITS_EQ_256-DAG: st1b { [[RES_LO]].b }, [[PG]], [x0] +; VBITS_EQ_256-DAG: st1b { [[RES_HI]].b }, [[PG]], [x0, x[[A]]] +; VBITS_EQ_256-NEXT: ret + %op = load <64 x i8>, <64 x i8>* %a + %res = call <64 x i8> @llvm.cttz.v64i8(<64 x i8> %op) + store <64 x i8> %res, <64 x i8>* %a + ret void +} + +define void @cttz_v128i8(<128 x i8>* %a) #0 { +; CHECK-LABEL: cttz_v128i8: +; VBITS_GE_1024: ptrue [[PG:p[0-9]+]].b, vl128 +; VBITS_GE_1024-NEXT: ld1b { [[OP:z[0-9]+]].b }, [[PG]]/z, [x0] +; VBITS_GE_1024-NEXT: rbit [[RBIT:z[0-9]+]].b, [[PG]]/m, [[OP]].b +; VBITS_GE_1024-NEXT: clz [[RES:z[0-9]+]].b, [[PG]]/m, [[RBIT]].b +; VBITS_GE_1024-NEXT: st1b { [[RES]].b }, [[PG]], [x0] +; VBITS_GE_1024-NEXT: ret + %op = load <128 x i8>, <128 x i8>* %a + %res = call <128 x i8> @llvm.cttz.v128i8(<128 x i8> %op) + store <128 x i8> %res, <128 x i8>* %a + ret void +} + +define void @cttz_v256i8(<256 x i8>* %a) #0 { +; CHECK-LABEL: cttz_v256i8: +; VBITS_GE_2048: ptrue [[PG:p[0-9]+]].b, vl256 +; VBITS_GE_2048-NEXT: ld1b { [[OP:z[0-9]+]].b }, [[PG]]/z, [x0] +; VBITS_GE_2048-NEXT: rbit [[RBIT:z[0-9]+]].b, [[PG]]/m, [[OP]].b +; VBITS_GE_2048-NEXT: clz [[RES:z[0-9]+]].b, [[PG]]/m, [[RBIT]].b +; VBITS_GE_2048-NEXT: st1b { [[RES]].b }, [[PG]], [x0] +; VBITS_GE_2048-NEXT: ret + %op = load <256 x i8>, <256 x i8>* %a + %res = call <256 x i8> @llvm.cttz.v256i8(<256 x i8> %op) + store <256 x i8> %res, <256 x i8>* %a + ret void +} + +define <4 x i16> @cttz_v4i16(<4 x i16> %op) #0 { +; CHECK-LABEL: cttz_v4i16: +; CHECK: ptrue [[PG:p[0-9]+]].h, vl4 +; CHECK-NEXT: rbit z[[RBIT:[0-9]+]].h, p0/m, z0.h +; CHECK-NEXT: clz v0.4h, v[[RBIT]].4h +; CHECK-NEXT: ret + %res = call <4 x i16> @llvm.cttz.v4i16(<4 x i16> %op) + ret <4 x i16> %res +} + +define <8 x i16> @cttz_v8i16(<8 x i16> %op) #0 { +; CHECK-LABEL: cttz_v8i16: +; CHECK: ptrue [[PG:p[0-9]+]].h, vl8 +; CHECK-NEXT: rbit z[[RBIT:[0-9]+]].h, p0/m, z0.h +; CHECK-NEXT: clz v0.8h, v[[RBIT]].8h +; CHECK-NEXT: ret + %res = call <8 x i16> @llvm.cttz.v8i16(<8 x i16> %op) + ret <8 x i16> %res +} + +define void @cttz_v16i16(<16 x i16>* %a) #0 { +; CHECK-LABEL: cttz_v16i16: +; CHECK: ptrue [[PG:p[0-9]+]].h, vl16 +; CHECK-NEXT: ld1h { [[OP:z[0-9]+]].h }, [[PG]]/z, [x0] +; CHECK-NEXT: rbit [[RBIT:z[0-9]+]].h, [[PG]]/m, [[OP]].h +; CHECK-NEXT: clz [[RES:z[0-9]+]].h, [[PG]]/m, [[RBIT]].h +; CHECK-NEXT: st1h { [[RES]].h }, [[PG]], [x0] +; CHECK-NEXT: ret + %op = load <16 x i16>, <16 x i16>* %a + %res = call <16 x i16> @llvm.cttz.v16i16(<16 x i16> %op) + store <16 x i16> %res, <16 x i16>* %a + ret void +} + +define void @cttz_v32i16(<32 x i16>* %a) #0 { +; CHECK-LABEL: cttz_v32i16: +; VBITS_GE_512: ptrue [[PG:p[0-9]+]].h, vl32 +; VBITS_GE_512-NEXT: ld1h { [[OP:z[0-9]+]].h }, [[PG]]/z, [x0] +; VBITS_GE_512-NEXT: rbit [[RBIT:z[0-9]+]].h, [[PG]]/m, [[OP]].h +; VBITS_GE_512-NEXT: clz [[RES:z[0-9]+]].h, [[PG]]/m, [[RBIT]].h +; VBITS_GE_512-NEXT: st1h { [[RES]].h }, [[PG]], [x0] +; VBITS_GE_512-NEXT: ret + +; Ensure sensible type legalisation. +; VBITS_EQ_256-DAG: ptrue [[PG:p[0-9]+]].h, vl16 +; VBITS_EQ_256-DAG: add x[[A_HI:[0-9]+]], x0, #32 +; VBITS_EQ_256-DAG: ld1h { [[OP_LO:z[0-9]+]].h }, [[PG]]/z, [x0] +; VBITS_EQ_256-DAG: ld1h { [[OP_HI:z[0-9]+]].h }, [[PG]]/z, [x[[A_HI]]] +; VBITS_EQ_256-DAG: rbit [[RBIT_LO:z[0-9]+]].h, [[PG]]/m, [[OP_LO]].h +; VBITS_EQ_256-DAG: rbit [[RBIT_HI:z[0-9]+]].h, [[PG]]/m, [[OP_HI]].h +; VBITS_EQ_256-DAG: clz [[RES_LO:z[0-9]+]].h, [[PG]]/m, [[RBIT_LO]].h +; VBITS_EQ_256-DAG: clz [[RES_HI:z[0-9]+]].h, [[PG]]/m, [[RBIT_HI]].h +; VBITS_EQ_256-DAG: st1h { [[RES_LO]].h }, [[PG]], [x0] +; VBITS_EQ_256-DAG: st1h { [[RES_HI]].h }, [[PG]], [x[[A_HI]] +; VBITS_EQ_256-NEXT: ret + %op = load <32 x i16>, <32 x i16>* %a + %res = call <32 x i16> @llvm.cttz.v32i16(<32 x i16> %op) + store <32 x i16> %res, <32 x i16>* %a + ret void +} + +define void @cttz_v64i16(<64 x i16>* %a) #0 { +; CHECK-LABEL: cttz_v64i16: +; VBITS_GE_1024: ptrue [[PG:p[0-9]+]].h, vl64 +; VBITS_GE_1024-NEXT: ld1h { [[OP:z[0-9]+]].h }, [[PG]]/z, [x0] +; VBITS_GE_1024-NEXT: rbit [[RBIT:z[0-9]+]].h, [[PG]]/m, [[OP]].h +; VBITS_GE_1024-NEXT: clz [[RES:z[0-9]+]].h, [[PG]]/m, [[RBIT]].h +; VBITS_GE_1024-NEXT: st1h { [[RES]].h }, [[PG]], [x0] +; VBITS_GE_1024-NEXT: ret + %op = load <64 x i16>, <64 x i16>* %a + %res = call <64 x i16> @llvm.cttz.v64i16(<64 x i16> %op) + store <64 x i16> %res, <64 x i16>* %a + ret void +} + +define void @cttz_v128i16(<128 x i16>* %a) #0 { +; CHECK-LABEL: cttz_v128i16: +; VBITS_GE_2048: ptrue [[PG:p[0-9]+]].h, vl128 +; VBITS_GE_2048-NEXT: ld1h { [[OP:z[0-9]+]].h }, [[PG]]/z, [x0] +; VBITS_GE_2048-NEXT: rbit [[RBIT:z[0-9]+]].h, [[PG]]/m, [[OP]].h +; VBITS_GE_2048-NEXT: clz [[RES:z[0-9]+]].h, [[PG]]/m, [[RBIT]].h +; VBITS_GE_2048-NEXT: st1h { [[RES]].h }, [[PG]], [x0] +; VBITS_GE_2048-NEXT: ret + %op = load <128 x i16>, <128 x i16>* %a + %res = call <128 x i16> @llvm.cttz.v128i16(<128 x i16> %op) + store <128 x i16> %res, <128 x i16>* %a + ret void +} + +; Don't use SVE for 64-bit vectors. +define <2 x i32> @cttz_v2i32(<2 x i32> %op) #0 { +; CHECK-LABEL: cttz_v2i32: +; CHECK: ptrue [[PG:p[0-9]+]].s, vl2 +; CHECK-NEXT: rbit z[[RBIT:[0-9]+]].s, p0/m, z0.s +; CHECK-NEXT: clz v0.2s, v[[RBIT]].2s +; CHECK-NEXT: ret + %res = call <2 x i32> @llvm.cttz.v2i32(<2 x i32> %op) + ret <2 x i32> %res +} + +; Don't use SVE for 128-bit vectors. +define <4 x i32> @cttz_v4i32(<4 x i32> %op) #0 { +; CHECK-LABEL: cttz_v4i32: +; CHECK: ptrue [[PG:p[0-9]+]].s, vl4 +; CHECK-NEXT: rbit z[[RBIT:[0-9]+]].s, p0/m, z0.s +; CHECK-NEXT: clz v0.4s, v[[RBIT]].4s +; CHECK-NEXT: ret + %res = call <4 x i32> @llvm.cttz.v4i32(<4 x i32> %op) + ret <4 x i32> %res +} + +define void @cttz_v8i32(<8 x i32>* %a) #0 { +; CHECK-LABEL: cttz_v8i32: +; CHECK: ptrue [[PG:p[0-9]+]].s, vl8 +; CHECK-NEXT: ld1w { [[OP:z[0-9]+]].s }, [[PG]]/z, [x0] +; CHECK-NEXT: rbit [[RBIT:z[0-9]+]].s, [[PG]]/m, [[OP]].s +; CHECK-NEXT: clz [[RES:z[0-9]+]].s, [[PG]]/m, [[RBIT]].s +; CHECK-NEXT: st1w { [[RES]].s }, [[PG]], [x0] +; CHECK-NEXT: ret + %op = load <8 x i32>, <8 x i32>* %a + %res = call <8 x i32> @llvm.cttz.v8i32(<8 x i32> %op) + store <8 x i32> %res, <8 x i32>* %a + ret void +} + +define void @cttz_v16i32(<16 x i32>* %a) #0 { +; CHECK-LABEL: cttz_v16i32: +; VBITS_GE_512: ptrue [[PG:p[0-9]+]].s, vl16 +; VBITS_GE_512-NEXT: ld1w { [[OP:z[0-9]+]].s }, [[PG]]/z, [x0] +; VBITS_GE_512-NEXT: rbit [[RBIT:z[0-9]+]].s, [[PG]]/m, [[OP]].s +; VBITS_GE_512-NEXT: clz [[RES:z[0-9]+]].s, [[PG]]/m, [[RBIT]].s +; VBITS_GE_512-NEXT: st1w { [[RES]].s }, [[PG]], [x0] +; VBITS_GE_512-NEXT: ret + +; Ensure sensible type legalisation. +; VBITS_EQ_256-DAG: ptrue [[PG:p[0-9]+]].s, vl8 +; VBITS_EQ_256-DAG: add x[[A_HI:[0-9]+]], x0, #32 +; VBITS_EQ_256-DAG: ld1w { [[OP_LO:z[0-9]+]].s }, [[PG]]/z, [x0] +; VBITS_EQ_256-DAG: ld1w { [[OP_HI:z[0-9]+]].s }, [[PG]]/z, [x[[A_HI]]] +; VBITS_EQ_256-DAG: rbit [[RBIT_LO:z[0-9]+]].s, [[PG]]/m, [[OP_LO]].s +; VBITS_EQ_256-DAG: rbit [[RBIT_HI:z[0-9]+]].s, [[PG]]/m, [[OP_HI]].s +; VBITS_EQ_256-DAG: clz [[RES_LO:z[0-9]+]].s, [[PG]]/m, [[RBIT_LO]].s +; VBITS_EQ_256-DAG: clz [[RES_HI:z[0-9]+]].s, [[PG]]/m, [[RBIT_HI]].s +; VBITS_EQ_256-DAG: st1w { [[RES_LO]].s }, [[PG]], [x0] +; VBITS_EQ_256-DAG: st1w { [[RES_HI]].s }, [[PG]], [x[[A_HI]] +; VBITS_EQ_256-NEXT: ret + %op = load <16 x i32>, <16 x i32>* %a + %res = call <16 x i32> @llvm.cttz.v16i32(<16 x i32> %op) + store <16 x i32> %res, <16 x i32>* %a + ret void +} + +define void @cttz_v32i32(<32 x i32>* %a) #0 { +; CHECK-LABEL: cttz_v32i32: +; VBITS_GE_1024: ptrue [[PG:p[0-9]+]].s, vl32 +; VBITS_GE_1024-NEXT: ld1w { [[OP:z[0-9]+]].s }, [[PG]]/z, [x0] +; VBITS_GE_1024-NEXT: rbit [[RBIT:z[0-9]+]].s, [[PG]]/m, [[OP]].s +; VBITS_GE_1024-NEXT: clz [[RES:z[0-9]+]].s, [[PG]]/m, [[RBIT]].s +; VBITS_GE_1024-NEXT: st1w { [[RES]].s }, [[PG]], [x0] +; VBITS_GE_1024-NEXT: ret + %op = load <32 x i32>, <32 x i32>* %a + %res = call <32 x i32> @llvm.cttz.v32i32(<32 x i32> %op) + store <32 x i32> %res, <32 x i32>* %a + ret void +} + +define void @cttz_v64i32(<64 x i32>* %a) #0 { +; CHECK-LABEL: cttz_v64i32: +; VBITS_GE_2048: ptrue [[PG:p[0-9]+]].s, vl64 +; VBITS_GE_2048-NEXT: ld1w { [[OP:z[0-9]+]].s }, [[PG]]/z, [x0] +; VBITS_GE_2048-NEXT: rbit [[RBIT:z[0-9]+]].s, [[PG]]/m, [[OP]].s +; VBITS_GE_2048-NEXT: clz [[RES:z[0-9]+]].s, [[PG]]/m, [[RBIT]].s +; VBITS_GE_2048-NEXT: st1w { [[RES]].s }, [[PG]], [x0] +; VBITS_GE_2048-NEXT: ret + %op = load <64 x i32>, <64 x i32>* %a + %res = call <64 x i32> @llvm.cttz.v64i32(<64 x i32> %op) + store <64 x i32> %res, <64 x i32>* %a + ret void +} + +define <1 x i64> @cttz_v1i64(<1 x i64> %op) #0 { +; CHECK-LABEL: cttz_v1i64: +; CHECK: ptrue [[PG:p[0-9]+]].d, vl1 +; CHECK-NEXT: rbit [[RBIT:z[0-9]+]].d, [[PG]]/m, z0.d +; CHECK-NEXT: clz z0.d, [[PG]]/m, [[RBIT]].d +; CHECK-NEXT: ret + %res = call <1 x i64> @llvm.cttz.v1i64(<1 x i64> %op) + ret <1 x i64> %res +} + +define <2 x i64> @cttz_v2i64(<2 x i64> %op) #0 { +; CHECK-LABEL: cttz_v2i64: +; CHECK: ptrue [[PG:p[0-9]+]].d, vl2 +; CHECK-NEXT: rbit [[RBIT:z[0-9]+]].d, [[PG]]/m, z0.d +; CHECK-NEXT: clz z0.d, [[PG]]/m, [[RBIT]].d +; CHECK-NEXT: ret + %res = call <2 x i64> @llvm.cttz.v2i64(<2 x i64> %op) + ret <2 x i64> %res +} + +define void @cttz_v4i64(<4 x i64>* %a) #0 { +; CHECK-LABEL: cttz_v4i64: +; CHECK: ptrue [[PG:p[0-9]+]].d, vl4 +; CHECK-NEXT: ld1d { [[OP:z[0-9]+]].d }, [[PG]]/z, [x0] +; CHECK-NEXT: rbit [[RBIT:z[0-9]+]].d, [[PG]]/m, [[OP]].d +; CHECK-NEXT: clz [[RES:z[0-9]+]].d, [[PG]]/m, [[RBIT]].d +; CHECK-NEXT: st1d { [[RES]].d }, [[PG]], [x0] +; CHECK-NEXT: ret + %op = load <4 x i64>, <4 x i64>* %a + %res = call <4 x i64> @llvm.cttz.v4i64(<4 x i64> %op) + store <4 x i64> %res, <4 x i64>* %a + ret void +} + +define void @cttz_v8i64(<8 x i64>* %a) #0 { +; CHECK-LABEL: cttz_v8i64: +; VBITS_GE_512: ptrue [[PG:p[0-9]+]].d, vl8 +; VBITS_GE_512-NEXT: ld1d { [[OP:z[0-9]+]].d }, [[PG]]/z, [x0] +; VBITS_GE_512-NEXT: rbit [[RBIT:z[0-9]+]].d, [[PG]]/m, [[OP]].d +; VBITS_GE_512-NEXT: clz [[RES:z[0-9]+]].d, [[PG]]/m, [[RBIT]].d +; VBITS_GE_512-NEXT: st1d { [[RES]].d }, [[PG]], [x0] +; VBITS_GE_512-NEXT: ret + +; Ensure sensible type legalisation. +; VBITS_EQ_256-DAG: ptrue [[PG:p[0-9]+]].d, vl4 +; VBITS_EQ_256-DAG: add x[[A_HI:[0-9]+]], x0, #32 +; VBITS_EQ_256-DAG: ld1d { [[OP_LO:z[0-9]+]].d }, [[PG]]/z, [x0] +; VBITS_EQ_256-DAG: ld1d { [[OP_HI:z[0-9]+]].d }, [[PG]]/z, [x[[A_HI]]] +; VBITS_EQ_256-DAG: rbit [[RBIT_LO:z[0-9]+]].d, [[PG]]/m, [[OP_LO]].d +; VBITS_EQ_256-DAG: rbit [[RBIT_HI:z[0-9]+]].d, [[PG]]/m, [[OP_HI]].d +; VBITS_EQ_256-DAG: clz [[RES_LO:z[0-9]+]].d, [[PG]]/m, [[RBIT_LO]].d +; VBITS_EQ_256-DAG: clz [[RES_HI:z[0-9]+]].d, [[PG]]/m, [[RBIT_HI]].d +; VBITS_EQ_256-DAG: st1d { [[RES_LO]].d }, [[PG]], [x0] +; VBITS_EQ_256-DAG: st1d { [[RES_HI]].d }, [[PG]], [x[[A_HI]] +; VBITS_EQ_256-NEXT: ret + %op = load <8 x i64>, <8 x i64>* %a + %res = call <8 x i64> @llvm.cttz.v8i64(<8 x i64> %op) + store <8 x i64> %res, <8 x i64>* %a + ret void +} + +define void @cttz_v16i64(<16 x i64>* %a) #0 { +; CHECK-LABEL: cttz_v16i64: +; VBITS_GE_1024: ptrue [[PG:p[0-9]+]].d, vl16 +; VBITS_GE_1024-NEXT: ld1d { [[OP:z[0-9]+]].d }, [[PG]]/z, [x0] +; VBITS_GE_1024-NEXT: rbit [[RBIT:z[0-9]+]].d, [[PG]]/m, [[OP]].d +; VBITS_GE_1024-NEXT: clz [[RES:z[0-9]+]].d, [[PG]]/m, [[RBIT]].d +; VBITS_GE_1024-NEXT: st1d { [[RES]].d }, [[PG]], [x0] +; VBITS_GE_1024-NEXT: ret + %op = load <16 x i64>, <16 x i64>* %a + %res = call <16 x i64> @llvm.cttz.v16i64(<16 x i64> %op) + store <16 x i64> %res, <16 x i64>* %a + ret void +} + +define void @cttz_v32i64(<32 x i64>* %a) #0 { +; CHECK-LABEL: cttz_v32i64: +; VBITS_GE_2048: ptrue [[PG:p[0-9]+]].d, vl32 +; VBITS_GE_2048-NEXT: ld1d { [[OP:z[0-9]+]].d }, [[PG]]/z, [x0] +; VBITS_GE_2048-NEXT: rbit [[RBIT:z[0-9]+]].d, [[PG]]/m, [[OP]].d +; VBITS_GE_2048-NEXT: clz [[RES:z[0-9]+]].d, [[PG]]/m, [[RBIT]].d +; VBITS_GE_2048-NEXT: st1d { [[RES]].d }, [[PG]], [x0] +; VBITS_GE_2048-NEXT: ret + %op = load <32 x i64>, <32 x i64>* %a + %res = call <32 x i64> @llvm.cttz.v32i64(<32 x i64> %op) + store <32 x i64> %res, <32 x i64>* %a + ret void +} + +attributes #0 = { "target-features"="+sve" } + +declare <8 x i8> @llvm.ctlz.v8i8(<8 x i8>) +declare <16 x i8> @llvm.ctlz.v16i8(<16 x i8>) +declare <32 x i8> @llvm.ctlz.v32i8(<32 x i8>) +declare <64 x i8> @llvm.ctlz.v64i8(<64 x i8>) +declare <128 x i8> @llvm.ctlz.v128i8(<128 x i8>) +declare <256 x i8> @llvm.ctlz.v256i8(<256 x i8>) +declare <4 x i16> @llvm.ctlz.v4i16(<4 x i16>) +declare <8 x i16> @llvm.ctlz.v8i16(<8 x i16>) +declare <16 x i16> @llvm.ctlz.v16i16(<16 x i16>) +declare <32 x i16> @llvm.ctlz.v32i16(<32 x i16>) +declare <64 x i16> @llvm.ctlz.v64i16(<64 x i16>) +declare <128 x i16> @llvm.ctlz.v128i16(<128 x i16>) +declare <2 x i32> @llvm.ctlz.v2i32(<2 x i32>) +declare <4 x i32> @llvm.ctlz.v4i32(<4 x i32>) +declare <8 x i32> @llvm.ctlz.v8i32(<8 x i32>) +declare <16 x i32> @llvm.ctlz.v16i32(<16 x i32>) +declare <32 x i32> @llvm.ctlz.v32i32(<32 x i32>) +declare <64 x i32> @llvm.ctlz.v64i32(<64 x i32>) +declare <1 x i64> @llvm.ctlz.v1i64(<1 x i64>) +declare <2 x i64> @llvm.ctlz.v2i64(<2 x i64>) +declare <4 x i64> @llvm.ctlz.v4i64(<4 x i64>) +declare <8 x i64> @llvm.ctlz.v8i64(<8 x i64>) +declare <16 x i64> @llvm.ctlz.v16i64(<16 x i64>) +declare <32 x i64> @llvm.ctlz.v32i64(<32 x i64>) + +declare <8 x i8> @llvm.ctpop.v8i8(<8 x i8>) +declare <16 x i8> @llvm.ctpop.v16i8(<16 x i8>) +declare <32 x i8> @llvm.ctpop.v32i8(<32 x i8>) +declare <64 x i8> @llvm.ctpop.v64i8(<64 x i8>) +declare <128 x i8> @llvm.ctpop.v128i8(<128 x i8>) +declare <256 x i8> @llvm.ctpop.v256i8(<256 x i8>) +declare <4 x i16> @llvm.ctpop.v4i16(<4 x i16>) +declare <8 x i16> @llvm.ctpop.v8i16(<8 x i16>) +declare <16 x i16> @llvm.ctpop.v16i16(<16 x i16>) +declare <32 x i16> @llvm.ctpop.v32i16(<32 x i16>) +declare <64 x i16> @llvm.ctpop.v64i16(<64 x i16>) +declare <128 x i16> @llvm.ctpop.v128i16(<128 x i16>) +declare <2 x i32> @llvm.ctpop.v2i32(<2 x i32>) +declare <4 x i32> @llvm.ctpop.v4i32(<4 x i32>) +declare <8 x i32> @llvm.ctpop.v8i32(<8 x i32>) +declare <16 x i32> @llvm.ctpop.v16i32(<16 x i32>) +declare <32 x i32> @llvm.ctpop.v32i32(<32 x i32>) +declare <64 x i32> @llvm.ctpop.v64i32(<64 x i32>) +declare <1 x i64> @llvm.ctpop.v1i64(<1 x i64>) +declare <2 x i64> @llvm.ctpop.v2i64(<2 x i64>) +declare <4 x i64> @llvm.ctpop.v4i64(<4 x i64>) +declare <8 x i64> @llvm.ctpop.v8i64(<8 x i64>) +declare <16 x i64> @llvm.ctpop.v16i64(<16 x i64>) +declare <32 x i64> @llvm.ctpop.v32i64(<32 x i64>) + +declare <8 x i8> @llvm.cttz.v8i8(<8 x i8>) +declare <16 x i8> @llvm.cttz.v16i8(<16 x i8>) +declare <32 x i8> @llvm.cttz.v32i8(<32 x i8>) +declare <64 x i8> @llvm.cttz.v64i8(<64 x i8>) +declare <128 x i8> @llvm.cttz.v128i8(<128 x i8>) +declare <256 x i8> @llvm.cttz.v256i8(<256 x i8>) +declare <4 x i16> @llvm.cttz.v4i16(<4 x i16>) +declare <8 x i16> @llvm.cttz.v8i16(<8 x i16>) +declare <16 x i16> @llvm.cttz.v16i16(<16 x i16>) +declare <32 x i16> @llvm.cttz.v32i16(<32 x i16>) +declare <64 x i16> @llvm.cttz.v64i16(<64 x i16>) +declare <128 x i16> @llvm.cttz.v128i16(<128 x i16>) +declare <2 x i32> @llvm.cttz.v2i32(<2 x i32>) +declare <4 x i32> @llvm.cttz.v4i32(<4 x i32>) +declare <8 x i32> @llvm.cttz.v8i32(<8 x i32>) +declare <16 x i32> @llvm.cttz.v16i32(<16 x i32>) +declare <32 x i32> @llvm.cttz.v32i32(<32 x i32>) +declare <64 x i32> @llvm.cttz.v64i32(<64 x i32>) +declare <1 x i64> @llvm.cttz.v1i64(<1 x i64>) +declare <2 x i64> @llvm.cttz.v2i64(<2 x i64>) +declare <4 x i64> @llvm.cttz.v4i64(<4 x i64>) +declare <8 x i64> @llvm.cttz.v8i64(<8 x i64>) +declare <16 x i64> @llvm.cttz.v16i64(<16 x i64>) +declare <32 x i64> @llvm.cttz.v32i64(<32 x i64>) -- 2.7.4