From eb52f69f59656ab182772f212b76d7fb15621210 Mon Sep 17 00:00:00 2001 From: Colin LeMahieu Date: Thu, 11 Dec 2014 16:43:06 +0000 Subject: [PATCH] [Hexagon] Adding encoding information for sign extend word instruction. llvm-svn: 224026 --- llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp | 4 +- llvm/lib/Target/Hexagon/HexagonInstrInfo.td | 57 +++++++++++++++++-------- llvm/lib/Target/Hexagon/HexagonInstrInfoV4.td | 12 +++--- llvm/lib/Target/Hexagon/HexagonPeephole.cpp | 2 +- llvm/test/MC/Disassembler/Hexagon/xtype_alu.txt | 2 + 5 files changed, 50 insertions(+), 27 deletions(-) diff --git a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp index 1cc3c3a..ec78123 100644 --- a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp +++ b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp @@ -453,7 +453,7 @@ SDNode *HexagonDAGToDAGISel::SelectIndexedLoadSignExtend64(LoadSDNode *LD, SDNode *Result_1 = CurDAG->getMachineNode(Opcode, dl, MVT::i32, MVT::i32, MVT::Other, Base, TargetConst, Chain); - SDNode *Result_2 = CurDAG->getMachineNode(Hexagon::SXTW, dl, MVT::i64, + SDNode *Result_2 = CurDAG->getMachineNode(Hexagon::A2_sxtw, dl, MVT::i64, SDValue(Result_1, 0)); MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1); MemOp[0] = LD->getMemOperand(); @@ -474,7 +474,7 @@ SDNode *HexagonDAGToDAGISel::SelectIndexedLoadSignExtend64(LoadSDNode *LD, SDNode *Result_1 = CurDAG->getMachineNode(Opcode, dl, MVT::i32, MVT::Other, Base, TargetConst0, Chain); - SDNode *Result_2 = CurDAG->getMachineNode(Hexagon::SXTW, dl, + SDNode *Result_2 = CurDAG->getMachineNode(Hexagon::A2_sxtw, dl, MVT::i64, SDValue(Result_1, 0)); SDNode* Result_3 = CurDAG->getMachineNode(Hexagon::ADD_ri, dl, MVT::i32, Base, TargetConstVal, diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfo.td b/llvm/lib/Target/Hexagon/HexagonInstrInfo.td index ec0458b..c936390 100644 --- a/llvm/lib/Target/Hexagon/HexagonInstrInfo.td +++ b/llvm/lib/Target/Hexagon/HexagonInstrInfo.td @@ -2200,11 +2200,32 @@ def NOT_rr64 : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1), "$dst = not($src1)", [(set (i64 DoubleRegs:$dst), (not (i64 DoubleRegs:$src1)))]>; +let hasSideEffects = 0 in +class T_S2op_1 RegTyBits, RegisterClass RCOut, + RegisterClass RCIn, bits<2> MajOp, bits<3> MinOp, bit isSat> + : SInst <(outs RCOut:$dst), (ins RCIn:$src), + "$dst = "#mnemonic#"($src)"#!if(isSat, ":sat", ""), + [], "", S_2op_tc_1_SLOT23 > { + bits<5> dst; + bits<5> src; + + let IClass = 0b1000; + + let Inst{27-24} = RegTyBits; + let Inst{23-22} = MajOp; + let Inst{21} = 0b0; + let Inst{20-16} = src; + let Inst{7-5} = MinOp; + let Inst{4-0} = dst; + } + +class T_S2op_1_di MajOp, bits<3> MinOp> + : T_S2op_1 ; + +// Sign extend word to doubleword +let isCodeGenOnly = 0 in +def A2_sxtw : T_S2op_1_di <"sxtw", 0b01, 0b000>; -// Sign extend word to doubleword. -def SXTW : ALU64_rr<(outs DoubleRegs:$dst), (ins IntRegs:$src1), - "$dst = sxtw($src1)", - [(set (i64 DoubleRegs:$dst), (sext (i32 IntRegs:$src1)))]>; //===----------------------------------------------------------------------===// // STYPE/ALU - //===----------------------------------------------------------------------===// @@ -2803,18 +2824,18 @@ let AddedComplexity = 10 in def : Pat <(i32 (zextloadi1 ADDRriS11_0:$addr)), (i32 (A2_and (i32 (LDrib ADDRriS11_0:$addr)), (A2_tfrsi 0x1)))>; -// Map from Rdd = sign_extend_inreg(Rss, i32) -> Rdd = SXTW(Rss.lo). +// Map from Rdd = sign_extend_inreg(Rss, i32) -> Rdd = A2_sxtw(Rss.lo). def : Pat <(i64 (sext_inreg (i64 DoubleRegs:$src1), i32)), - (i64 (SXTW (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_loreg))))>; + (i64 (A2_sxtw (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_loreg))))>; -// Map from Rdd = sign_extend_inreg(Rss, i16) -> Rdd = SXTW(SXTH(Rss.lo)). +// Map from Rdd = sign_extend_inreg(Rss, i16) -> Rdd = A2_sxtw(SXTH(Rss.lo)). def : Pat <(i64 (sext_inreg (i64 DoubleRegs:$src1), i16)), - (i64 (SXTW (i32 (A2_sxth (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), + (i64 (A2_sxtw (i32 (A2_sxth (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_loreg))))))>; -// Map from Rdd = sign_extend_inreg(Rss, i8) -> Rdd = SXTW(SXTB(Rss.lo)). +// Map from Rdd = sign_extend_inreg(Rss, i8) -> Rdd = A2_sxtw(SXTB(Rss.lo)). def : Pat <(i64 (sext_inreg (i64 DoubleRegs:$src1), i8)), - (i64 (SXTW (i32 (A2_sxtb (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), + (i64 (A2_sxtw (i32 (A2_sxtb (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_loreg))))))>; // We want to prevent emitting pnot's as much as possible. @@ -2927,11 +2948,11 @@ def : Pat<(store (i1 -1), ADDRriS11_2:$addr), def : Pat<(store (i1 PredRegs:$src1), ADDRriS11_2:$addr), (STrib ADDRriS11_2:$addr, (i32 (C2_muxii (i1 PredRegs:$src1), 1, 0)) )>; -// Map Rdd = anyext(Rs) -> Rdd = sxtw(Rs). +// Map Rdd = anyext(Rs) -> Rdd = A2_sxtw(Rs). // Hexagon_TODO: We can probably use combine but that will cost 2 instructions. // Better way to do this? def : Pat<(i64 (anyext (i32 IntRegs:$src1))), - (i64 (SXTW (i32 IntRegs:$src1)))>; + (i64 (A2_sxtw (i32 IntRegs:$src1)))>; // Map cmple -> cmpgt. // rs <= rt -> !(rs > rt). @@ -3054,22 +3075,22 @@ def : Pat <(i64 (sext (i1 PredRegs:$src1))), // Convert sign-extended load back to load and sign extend. // i8 -> i64 def: Pat <(i64 (sextloadi8 ADDRriS11_0:$src1)), - (i64 (SXTW (LDrib ADDRriS11_0:$src1)))>; + (i64 (A2_sxtw (LDrib ADDRriS11_0:$src1)))>; // Convert any-extended load back to load and sign extend. // i8 -> i64 def: Pat <(i64 (extloadi8 ADDRriS11_0:$src1)), - (i64 (SXTW (LDrib ADDRriS11_0:$src1)))>; + (i64 (A2_sxtw (LDrib ADDRriS11_0:$src1)))>; // Convert sign-extended load back to load and sign extend. // i16 -> i64 def: Pat <(i64 (sextloadi16 ADDRriS11_1:$src1)), - (i64 (SXTW (LDrih ADDRriS11_1:$src1)))>; + (i64 (A2_sxtw (LDrih ADDRriS11_1:$src1)))>; // Convert sign-extended load back to load and sign extend. // i32 -> i64 def: Pat <(i64 (sextloadi32 ADDRriS11_2:$src1)), - (i64 (SXTW (LDriw ADDRriS11_2:$src1)))>; + (i64 (A2_sxtw (LDriw ADDRriS11_2:$src1)))>; // Zero extends. @@ -3146,9 +3167,9 @@ def : Pat <(i32 (zext (i1 PredRegs:$src1))), def : Pat <(i32 (anyext (i1 PredRegs:$src1))), (i32 (C2_muxii (i1 PredRegs:$src1), 1, 0))>; -// Map from Rss = Pd to Rdd = sxtw (mux(Pd, #1, #0)) +// Map from Rss = Pd to Rdd = A2_sxtw (mux(Pd, #1, #0)) def : Pat <(i64 (anyext (i1 PredRegs:$src1))), - (i64 (SXTW (i32 (C2_muxii (i1 PredRegs:$src1), 1, 0))))>; + (i64 (A2_sxtw (i32 (C2_muxii (i1 PredRegs:$src1), 1, 0))))>; let AddedComplexity = 100 in diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfoV4.td b/llvm/lib/Target/Hexagon/HexagonInstrInfoV4.td index 2cefca5..5c739f2 100644 --- a/llvm/lib/Target/Hexagon/HexagonInstrInfoV4.td +++ b/llvm/lib/Target/Hexagon/HexagonInstrInfoV4.td @@ -3249,7 +3249,7 @@ def: Pat <(i64 (zextloadi8 (NumUsesBelowThresCONST32 tglobaladdr:$addr))), (i64 (COMBINE_Ir_V4 0, (LDriub_abs_V4 tglobaladdr:$addr)))>; def: Pat <(i64 (sextloadi8 (NumUsesBelowThresCONST32 tglobaladdr:$addr))), - (i64 (SXTW (LDrib_abs_V4 tglobaladdr:$addr)))>; + (i64 (A2_sxtw (LDrib_abs_V4 tglobaladdr:$addr)))>; def: Pat <(i64 (extloadi8 FoldGlobalAddr:$addr)), (i64 (COMBINE_Ir_V4 0, (LDrib_abs_V4 FoldGlobalAddr:$addr)))>; @@ -3258,7 +3258,7 @@ def: Pat <(i64 (zextloadi8 FoldGlobalAddr:$addr)), (i64 (COMBINE_Ir_V4 0, (LDriub_abs_V4 FoldGlobalAddr:$addr)))>; def: Pat <(i64 (sextloadi8 FoldGlobalAddr:$addr)), - (i64 (SXTW (LDrib_abs_V4 FoldGlobalAddr:$addr)))>; + (i64 (A2_sxtw (LDrib_abs_V4 FoldGlobalAddr:$addr)))>; } // i16 -> i64 loads // We need a complexity of 120 here to override preceding handling of @@ -3273,7 +3273,7 @@ def: Pat <(i64 (zextloadi16 (NumUsesBelowThresCONST32 tglobaladdr:$addr))), Requires<[HasV4T]>; def: Pat <(i64 (sextloadi16 (NumUsesBelowThresCONST32 tglobaladdr:$addr))), - (i64 (SXTW (LDrih_abs_V4 tglobaladdr:$addr)))>, + (i64 (A2_sxtw (LDrih_abs_V4 tglobaladdr:$addr)))>, Requires<[HasV4T]>; def: Pat <(i64 (extloadi16 FoldGlobalAddr:$addr)), @@ -3285,7 +3285,7 @@ def: Pat <(i64 (zextloadi16 FoldGlobalAddr:$addr)), Requires<[HasV4T]>; def: Pat <(i64 (sextloadi16 FoldGlobalAddr:$addr)), - (i64 (SXTW (LDrih_abs_V4 FoldGlobalAddr:$addr)))>, + (i64 (A2_sxtw (LDrih_abs_V4 FoldGlobalAddr:$addr)))>, Requires<[HasV4T]>; } // i32->i64 loads @@ -3301,7 +3301,7 @@ def: Pat <(i64 (zextloadi32 (NumUsesBelowThresCONST32 tglobaladdr:$addr))), Requires<[HasV4T]>; def: Pat <(i64 (sextloadi32 (NumUsesBelowThresCONST32 tglobaladdr:$addr))), - (i64 (SXTW (LDriw_abs_V4 tglobaladdr:$addr)))>, + (i64 (A2_sxtw (LDriw_abs_V4 tglobaladdr:$addr)))>, Requires<[HasV4T]>; def: Pat <(i64 (extloadi32 FoldGlobalAddr:$addr)), @@ -3313,7 +3313,7 @@ def: Pat <(i64 (zextloadi32 FoldGlobalAddr:$addr)), Requires<[HasV4T]>; def: Pat <(i64 (sextloadi32 FoldGlobalAddr:$addr)), - (i64 (SXTW (LDriw_abs_V4 FoldGlobalAddr:$addr)))>, + (i64 (A2_sxtw (LDriw_abs_V4 FoldGlobalAddr:$addr)))>, Requires<[HasV4T]>; } diff --git a/llvm/lib/Target/Hexagon/HexagonPeephole.cpp b/llvm/lib/Target/Hexagon/HexagonPeephole.cpp index f266149..6553072 100644 --- a/llvm/lib/Target/Hexagon/HexagonPeephole.cpp +++ b/llvm/lib/Target/Hexagon/HexagonPeephole.cpp @@ -133,7 +133,7 @@ bool HexagonPeephole::runOnMachineFunction(MachineFunction &MF) { MachineInstr *MI = MII; // Look for sign extends: // %vreg170 = SXTW %vreg166 - if (!DisableOptSZExt && MI->getOpcode() == Hexagon::SXTW) { + if (!DisableOptSZExt && MI->getOpcode() == Hexagon::A2_sxtw) { assert (MI->getNumOperands() == 2); MachineOperand &Dst = MI->getOperand(0); MachineOperand &Src = MI->getOperand(1); diff --git a/llvm/test/MC/Disassembler/Hexagon/xtype_alu.txt b/llvm/test/MC/Disassembler/Hexagon/xtype_alu.txt index 7060824..f883538 100644 --- a/llvm/test/MC/Disassembler/Hexagon/xtype_alu.txt +++ b/llvm/test/MC/Disassembler/Hexagon/xtype_alu.txt @@ -64,5 +64,7 @@ # CHECK: r17 = sub(r21.h, r31.l):sat:<<16 0xf1 0xd5 0x7f 0xd5 # CHECK: r17 = sub(r21.h, r31.h):sat:<<16 +0x10 0xc0 0x55 0x84 +# CHECK: r17:16 = sxtw(r21) 0x90 0xde 0xf4 0xd3 # CHECK: r17:16 = xor(r21:20, r31:30) -- 2.7.4