From eb2393659113696adf2bd770917f3109d1455c76 Mon Sep 17 00:00:00 2001
From: Fraser Cormack <fraser@codeplay.com>
Date: Fri, 28 May 2021 12:06:15 +0100
Subject: [PATCH] [RISCV] Support vector conversions between fp and i1

This patch custom lowers FP_TO_[US]INT and [US]INT_TO_FP conversions
between floating-point and boolean vectors. As the default action is
scalarization, this patch both supports scalable-vector conversions and
improves the code generation for fixed-length vectors.

The lowering for these conversions can piggy-back on the existing
lowering, which lowers the operations to a supported narrowing/widening
conversion and then either an extension or truncation.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D103312
---
 llvm/lib/Target/RISCV/RISCVISelLowering.cpp       |   19 +-
 llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i.ll | 1162 ++++----------
 llvm/test/CodeGen/RISCV/rvv/fixed-vectors-i2fp.ll | 1666 +++------------------
 llvm/test/CodeGen/RISCV/rvv/vfptoi-sdnode.ll      |  360 +++++
 llvm/test/CodeGen/RISCV/rvv/vitofp-sdnode.ll      |  360 +++++
 5 files changed, 1182 insertions(+), 2385 deletions(-)

diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index c93a672..ff76626 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -451,6 +451,15 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
       setOperationAction(ISD::VECREDUCE_OR, VT, Custom);
       setOperationAction(ISD::VECREDUCE_XOR, VT, Custom);
 
+      // RVV has native int->float & float->int conversions where the
+      // element type sizes are within one power-of-two of each other. Any
+      // wider distances between type sizes have to be lowered as sequences
+      // which progressively narrow the gap in stages.
+      setOperationAction(ISD::SINT_TO_FP, VT, Custom);
+      setOperationAction(ISD::UINT_TO_FP, VT, Custom);
+      setOperationAction(ISD::FP_TO_SINT, VT, Custom);
+      setOperationAction(ISD::FP_TO_UINT, VT, Custom);
+
       // Expand all extending loads to types larger than this, and truncating
       // stores from types larger than this.
       for (MVT OtherVT : MVT::integer_scalable_vector_valuetypes()) {
@@ -650,6 +659,11 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
         setOperationAction(ISD::VECREDUCE_OR, VT, Custom);
         setOperationAction(ISD::VECREDUCE_XOR, VT, Custom);
 
+        setOperationAction(ISD::SINT_TO_FP, VT, Custom);
+        setOperationAction(ISD::UINT_TO_FP, VT, Custom);
+        setOperationAction(ISD::FP_TO_SINT, VT, Custom);
+        setOperationAction(ISD::FP_TO_UINT, VT, Custom);
+
         // Operations below are different for between masks and other vectors.
         if (VT.getVectorElementType() == MVT::i1) {
           setOperationAction(ISD::AND, VT, Custom);
@@ -697,11 +711,6 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
         setOperationAction(ISD::MULHS, VT, Custom);
         setOperationAction(ISD::MULHU, VT, Custom);
 
-        setOperationAction(ISD::SINT_TO_FP, VT, Custom);
-        setOperationAction(ISD::UINT_TO_FP, VT, Custom);
-        setOperationAction(ISD::FP_TO_SINT, VT, Custom);
-        setOperationAction(ISD::FP_TO_UINT, VT, Custom);
-
         setOperationAction(ISD::VSELECT, VT, Custom);
         setOperationAction(ISD::SELECT, VT, Expand);
         setOperationAction(ISD::SELECT_CC, VT, Expand);
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i.ll
index 1198dab..be8efd4 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i.ll
@@ -1,8 +1,8 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+experimental-v,+experimental-zfh,+f,+d -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=8 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX8,RV32,RV32-LMULMAX8
-; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+experimental-v,+experimental-zfh,+f,+d -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=8 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX8,RV64,RV64-LMULMAX8
-; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+experimental-v,+experimental-zfh,+f,+d -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1,RV32,RV32-LMULMAX1
-; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+experimental-v,+experimental-zfh,+f,+d -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1,RV64,RV64-LMULMAX1
+; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+experimental-v,+experimental-zfh,+f,+d -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=8 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX8
+; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+experimental-v,+experimental-zfh,+f,+d -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=8 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX8
+; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+experimental-v,+experimental-zfh,+f,+d -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1
+; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+experimental-v,+experimental-zfh,+f,+d -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1
 
 define void @fp2si_v2f32_v2i32(<2 x float>* %x, <2 x i32>* %y) {
 ; CHECK-LABEL: fp2si_v2f32_v2i32:
@@ -33,77 +33,25 @@ define void @fp2ui_v2f32_v2i32(<2 x float>* %x, <2 x i32>* %y) {
 }
 
 define <2 x i1> @fp2si_v2f32_v2i1(<2 x float> %x) {
-; RV32-LABEL: fp2si_v2f32_v2i1:
-; RV32:       # %bb.0:
-; RV32-NEXT:    vsetivli zero, 1, e32,mf2,ta,mu
-; RV32-NEXT:    vslidedown.vi v25, v8, 1
-; RV32-NEXT:    vfmv.f.s ft0, v25
-; RV32-NEXT:    fcvt.w.s a0, ft0, rtz
-; RV32-NEXT:    vsetivli zero, 2, e8,mf8,ta,mu
-; RV32-NEXT:    vmv.v.x v25, a0
-; RV32-NEXT:    vsetvli zero, zero, e32,mf2,ta,mu
-; RV32-NEXT:    vfmv.f.s ft0, v8
-; RV32-NEXT:    fcvt.w.s a0, ft0, rtz
-; RV32-NEXT:    vsetivli zero, 2, e8,mf8,ta,mu
-; RV32-NEXT:    vmv.s.x v25, a0
-; RV32-NEXT:    vand.vi v25, v25, 1
-; RV32-NEXT:    vmsne.vi v0, v25, 0
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: fp2si_v2f32_v2i1:
-; RV64:       # %bb.0:
-; RV64-NEXT:    vsetivli zero, 1, e32,mf2,ta,mu
-; RV64-NEXT:    vslidedown.vi v25, v8, 1
-; RV64-NEXT:    vfmv.f.s ft0, v25
-; RV64-NEXT:    fcvt.l.s a0, ft0, rtz
-; RV64-NEXT:    vsetivli zero, 2, e8,mf8,ta,mu
-; RV64-NEXT:    vmv.v.x v25, a0
-; RV64-NEXT:    vsetvli zero, zero, e32,mf2,ta,mu
-; RV64-NEXT:    vfmv.f.s ft0, v8
-; RV64-NEXT:    fcvt.l.s a0, ft0, rtz
-; RV64-NEXT:    vsetivli zero, 2, e8,mf8,ta,mu
-; RV64-NEXT:    vmv.s.x v25, a0
-; RV64-NEXT:    vand.vi v25, v25, 1
-; RV64-NEXT:    vmsne.vi v0, v25, 0
-; RV64-NEXT:    ret
+; CHECK-LABEL: fp2si_v2f32_v2i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 2, e16,mf4,ta,mu
+; CHECK-NEXT:    vfncvt.rtz.x.f.w v25, v8
+; CHECK-NEXT:    vand.vi v25, v25, 1
+; CHECK-NEXT:    vmsne.vi v0, v25, 0
+; CHECK-NEXT:    ret
   %z = fptosi <2 x float> %x to <2 x i1>
   ret <2 x i1> %z
 }
 
 define <2 x i1> @fp2ui_v2f32_v2i1(<2 x float> %x) {
-; RV32-LABEL: fp2ui_v2f32_v2i1:
-; RV32:       # %bb.0:
-; RV32-NEXT:    vsetivli zero, 1, e32,mf2,ta,mu
-; RV32-NEXT:    vslidedown.vi v25, v8, 1
-; RV32-NEXT:    vfmv.f.s ft0, v25
-; RV32-NEXT:    fcvt.wu.s a0, ft0, rtz
-; RV32-NEXT:    vsetivli zero, 2, e8,mf8,ta,mu
-; RV32-NEXT:    vmv.v.x v25, a0
-; RV32-NEXT:    vsetvli zero, zero, e32,mf2,ta,mu
-; RV32-NEXT:    vfmv.f.s ft0, v8
-; RV32-NEXT:    fcvt.wu.s a0, ft0, rtz
-; RV32-NEXT:    vsetivli zero, 2, e8,mf8,ta,mu
-; RV32-NEXT:    vmv.s.x v25, a0
-; RV32-NEXT:    vand.vi v25, v25, 1
-; RV32-NEXT:    vmsne.vi v0, v25, 0
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: fp2ui_v2f32_v2i1:
-; RV64:       # %bb.0:
-; RV64-NEXT:    vsetivli zero, 1, e32,mf2,ta,mu
-; RV64-NEXT:    vslidedown.vi v25, v8, 1
-; RV64-NEXT:    vfmv.f.s ft0, v25
-; RV64-NEXT:    fcvt.lu.s a0, ft0, rtz
-; RV64-NEXT:    vsetivli zero, 2, e8,mf8,ta,mu
-; RV64-NEXT:    vmv.v.x v25, a0
-; RV64-NEXT:    vsetvli zero, zero, e32,mf2,ta,mu
-; RV64-NEXT:    vfmv.f.s ft0, v8
-; RV64-NEXT:    fcvt.lu.s a0, ft0, rtz
-; RV64-NEXT:    vsetivli zero, 2, e8,mf8,ta,mu
-; RV64-NEXT:    vmv.s.x v25, a0
-; RV64-NEXT:    vand.vi v25, v25, 1
-; RV64-NEXT:    vmsne.vi v0, v25, 0
-; RV64-NEXT:    ret
+; CHECK-LABEL: fp2ui_v2f32_v2i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 2, e16,mf4,ta,mu
+; CHECK-NEXT:    vfncvt.rtz.xu.f.w v25, v8
+; CHECK-NEXT:    vand.vi v25, v25, 1
+; CHECK-NEXT:    vmsne.vi v0, v25, 0
+; CHECK-NEXT:    ret
   %z = fptoui <2 x float> %x to <2 x i1>
   ret <2 x i1> %z
 }
@@ -163,365 +111,85 @@ define void @fp2ui_v8f32_v8i32(<8 x float>* %x, <8 x i32>* %y) {
 }
 
 define <8 x i1> @fp2si_v8f32_v8i1(<8 x float> %x) {
-; RV32-LMULMAX8-LABEL: fp2si_v8f32_v8i1:
-; RV32-LMULMAX8:       # %bb.0:
-; RV32-LMULMAX8-NEXT:    addi sp, sp, -16
-; RV32-LMULMAX8-NEXT:    .cfi_def_cfa_offset 16
-; RV32-LMULMAX8-NEXT:    vsetvli zero, zero, e32,m2,ta,mu
-; RV32-LMULMAX8-NEXT:    vfmv.f.s ft0, v8
-; RV32-LMULMAX8-NEXT:    fcvt.w.s a0, ft0, rtz
-; RV32-LMULMAX8-NEXT:    sb a0, 8(sp)
-; RV32-LMULMAX8-NEXT:    vsetivli zero, 1, e32,m2,ta,mu
-; RV32-LMULMAX8-NEXT:    vslidedown.vi v26, v8, 7
-; RV32-LMULMAX8-NEXT:    vfmv.f.s ft0, v26
-; RV32-LMULMAX8-NEXT:    fcvt.w.s a0, ft0, rtz
-; RV32-LMULMAX8-NEXT:    sb a0, 15(sp)
-; RV32-LMULMAX8-NEXT:    vslidedown.vi v26, v8, 6
-; RV32-LMULMAX8-NEXT:    vfmv.f.s ft0, v26
-; RV32-LMULMAX8-NEXT:    fcvt.w.s a0, ft0, rtz
-; RV32-LMULMAX8-NEXT:    sb a0, 14(sp)
-; RV32-LMULMAX8-NEXT:    vslidedown.vi v26, v8, 5
-; RV32-LMULMAX8-NEXT:    vfmv.f.s ft0, v26
-; RV32-LMULMAX8-NEXT:    fcvt.w.s a0, ft0, rtz
-; RV32-LMULMAX8-NEXT:    sb a0, 13(sp)
-; RV32-LMULMAX8-NEXT:    vslidedown.vi v26, v8, 4
-; RV32-LMULMAX8-NEXT:    vfmv.f.s ft0, v26
-; RV32-LMULMAX8-NEXT:    fcvt.w.s a0, ft0, rtz
-; RV32-LMULMAX8-NEXT:    sb a0, 12(sp)
-; RV32-LMULMAX8-NEXT:    vslidedown.vi v26, v8, 3
-; RV32-LMULMAX8-NEXT:    vfmv.f.s ft0, v26
-; RV32-LMULMAX8-NEXT:    fcvt.w.s a0, ft0, rtz
-; RV32-LMULMAX8-NEXT:    sb a0, 11(sp)
-; RV32-LMULMAX8-NEXT:    vslidedown.vi v26, v8, 2
-; RV32-LMULMAX8-NEXT:    vfmv.f.s ft0, v26
-; RV32-LMULMAX8-NEXT:    fcvt.w.s a0, ft0, rtz
-; RV32-LMULMAX8-NEXT:    sb a0, 10(sp)
-; RV32-LMULMAX8-NEXT:    vslidedown.vi v26, v8, 1
-; RV32-LMULMAX8-NEXT:    vfmv.f.s ft0, v26
-; RV32-LMULMAX8-NEXT:    fcvt.w.s a0, ft0, rtz
-; RV32-LMULMAX8-NEXT:    sb a0, 9(sp)
-; RV32-LMULMAX8-NEXT:    vsetivli zero, 8, e8,mf2,ta,mu
-; RV32-LMULMAX8-NEXT:    addi a0, sp, 8
-; RV32-LMULMAX8-NEXT:    vle8.v v25, (a0)
-; RV32-LMULMAX8-NEXT:    vand.vi v25, v25, 1
-; RV32-LMULMAX8-NEXT:    vmsne.vi v0, v25, 0
-; RV32-LMULMAX8-NEXT:    addi sp, sp, 16
-; RV32-LMULMAX8-NEXT:    ret
-;
-; RV64-LMULMAX8-LABEL: fp2si_v8f32_v8i1:
-; RV64-LMULMAX8:       # %bb.0:
-; RV64-LMULMAX8-NEXT:    addi sp, sp, -16
-; RV64-LMULMAX8-NEXT:    .cfi_def_cfa_offset 16
-; RV64-LMULMAX8-NEXT:    vsetvli zero, zero, e32,m2,ta,mu
-; RV64-LMULMAX8-NEXT:    vfmv.f.s ft0, v8
-; RV64-LMULMAX8-NEXT:    fcvt.l.s a0, ft0, rtz
-; RV64-LMULMAX8-NEXT:    sb a0, 8(sp)
-; RV64-LMULMAX8-NEXT:    vsetivli zero, 1, e32,m2,ta,mu
-; RV64-LMULMAX8-NEXT:    vslidedown.vi v26, v8, 7
-; RV64-LMULMAX8-NEXT:    vfmv.f.s ft0, v26
-; RV64-LMULMAX8-NEXT:    fcvt.l.s a0, ft0, rtz
-; RV64-LMULMAX8-NEXT:    sb a0, 15(sp)
-; RV64-LMULMAX8-NEXT:    vslidedown.vi v26, v8, 6
-; RV64-LMULMAX8-NEXT:    vfmv.f.s ft0, v26
-; RV64-LMULMAX8-NEXT:    fcvt.l.s a0, ft0, rtz
-; RV64-LMULMAX8-NEXT:    sb a0, 14(sp)
-; RV64-LMULMAX8-NEXT:    vslidedown.vi v26, v8, 5
-; RV64-LMULMAX8-NEXT:    vfmv.f.s ft0, v26
-; RV64-LMULMAX8-NEXT:    fcvt.l.s a0, ft0, rtz
-; RV64-LMULMAX8-NEXT:    sb a0, 13(sp)
-; RV64-LMULMAX8-NEXT:    vslidedown.vi v26, v8, 4
-; RV64-LMULMAX8-NEXT:    vfmv.f.s ft0, v26
-; RV64-LMULMAX8-NEXT:    fcvt.l.s a0, ft0, rtz
-; RV64-LMULMAX8-NEXT:    sb a0, 12(sp)
-; RV64-LMULMAX8-NEXT:    vslidedown.vi v26, v8, 3
-; RV64-LMULMAX8-NEXT:    vfmv.f.s ft0, v26
-; RV64-LMULMAX8-NEXT:    fcvt.l.s a0, ft0, rtz
-; RV64-LMULMAX8-NEXT:    sb a0, 11(sp)
-; RV64-LMULMAX8-NEXT:    vslidedown.vi v26, v8, 2
-; RV64-LMULMAX8-NEXT:    vfmv.f.s ft0, v26
-; RV64-LMULMAX8-NEXT:    fcvt.l.s a0, ft0, rtz
-; RV64-LMULMAX8-NEXT:    sb a0, 10(sp)
-; RV64-LMULMAX8-NEXT:    vslidedown.vi v26, v8, 1
-; RV64-LMULMAX8-NEXT:    vfmv.f.s ft0, v26
-; RV64-LMULMAX8-NEXT:    fcvt.l.s a0, ft0, rtz
-; RV64-LMULMAX8-NEXT:    sb a0, 9(sp)
-; RV64-LMULMAX8-NEXT:    vsetivli zero, 8, e8,mf2,ta,mu
-; RV64-LMULMAX8-NEXT:    addi a0, sp, 8
-; RV64-LMULMAX8-NEXT:    vle8.v v25, (a0)
-; RV64-LMULMAX8-NEXT:    vand.vi v25, v25, 1
-; RV64-LMULMAX8-NEXT:    vmsne.vi v0, v25, 0
-; RV64-LMULMAX8-NEXT:    addi sp, sp, 16
-; RV64-LMULMAX8-NEXT:    ret
-;
-; RV32-LMULMAX1-LABEL: fp2si_v8f32_v8i1:
-; RV32-LMULMAX1:       # %bb.0:
-; RV32-LMULMAX1-NEXT:    addi sp, sp, -16
-; RV32-LMULMAX1-NEXT:    .cfi_def_cfa_offset 16
-; RV32-LMULMAX1-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
-; RV32-LMULMAX1-NEXT:    vfmv.f.s ft0, v9
-; RV32-LMULMAX1-NEXT:    fcvt.w.s a0, ft0, rtz
-; RV32-LMULMAX1-NEXT:    sb a0, 12(sp)
-; RV32-LMULMAX1-NEXT:    vfmv.f.s ft0, v8
-; RV32-LMULMAX1-NEXT:    fcvt.w.s a0, ft0, rtz
-; RV32-LMULMAX1-NEXT:    sb a0, 8(sp)
-; RV32-LMULMAX1-NEXT:    vsetivli zero, 1, e32,m1,ta,mu
-; RV32-LMULMAX1-NEXT:    vslidedown.vi v25, v9, 3
-; RV32-LMULMAX1-NEXT:    vfmv.f.s ft0, v25
-; RV32-LMULMAX1-NEXT:    fcvt.w.s a0, ft0, rtz
-; RV32-LMULMAX1-NEXT:    sb a0, 15(sp)
-; RV32-LMULMAX1-NEXT:    vslidedown.vi v25, v9, 2
-; RV32-LMULMAX1-NEXT:    vfmv.f.s ft0, v25
-; RV32-LMULMAX1-NEXT:    fcvt.w.s a0, ft0, rtz
-; RV32-LMULMAX1-NEXT:    sb a0, 14(sp)
-; RV32-LMULMAX1-NEXT:    vslidedown.vi v25, v9, 1
-; RV32-LMULMAX1-NEXT:    vfmv.f.s ft0, v25
-; RV32-LMULMAX1-NEXT:    fcvt.w.s a0, ft0, rtz
-; RV32-LMULMAX1-NEXT:    sb a0, 13(sp)
-; RV32-LMULMAX1-NEXT:    vslidedown.vi v25, v8, 3
-; RV32-LMULMAX1-NEXT:    vfmv.f.s ft0, v25
-; RV32-LMULMAX1-NEXT:    fcvt.w.s a0, ft0, rtz
-; RV32-LMULMAX1-NEXT:    sb a0, 11(sp)
-; RV32-LMULMAX1-NEXT:    vslidedown.vi v25, v8, 2
-; RV32-LMULMAX1-NEXT:    vfmv.f.s ft0, v25
-; RV32-LMULMAX1-NEXT:    fcvt.w.s a0, ft0, rtz
-; RV32-LMULMAX1-NEXT:    sb a0, 10(sp)
-; RV32-LMULMAX1-NEXT:    vslidedown.vi v25, v8, 1
-; RV32-LMULMAX1-NEXT:    vfmv.f.s ft0, v25
-; RV32-LMULMAX1-NEXT:    fcvt.w.s a0, ft0, rtz
-; RV32-LMULMAX1-NEXT:    sb a0, 9(sp)
-; RV32-LMULMAX1-NEXT:    vsetivli zero, 8, e8,mf2,ta,mu
-; RV32-LMULMAX1-NEXT:    addi a0, sp, 8
-; RV32-LMULMAX1-NEXT:    vle8.v v25, (a0)
-; RV32-LMULMAX1-NEXT:    vand.vi v25, v25, 1
-; RV32-LMULMAX1-NEXT:    vmsne.vi v0, v25, 0
-; RV32-LMULMAX1-NEXT:    addi sp, sp, 16
-; RV32-LMULMAX1-NEXT:    ret
+; LMULMAX8-LABEL: fp2si_v8f32_v8i1:
+; LMULMAX8:       # %bb.0:
+; LMULMAX8-NEXT:    vsetivli zero, 8, e16,m1,ta,mu
+; LMULMAX8-NEXT:    vfncvt.rtz.x.f.w v25, v8
+; LMULMAX8-NEXT:    vand.vi v25, v25, 1
+; LMULMAX8-NEXT:    vmsne.vi v0, v25, 0
+; LMULMAX8-NEXT:    ret
 ;
-; RV64-LMULMAX1-LABEL: fp2si_v8f32_v8i1:
-; RV64-LMULMAX1:       # %bb.0:
-; RV64-LMULMAX1-NEXT:    addi sp, sp, -16
-; RV64-LMULMAX1-NEXT:    .cfi_def_cfa_offset 16
-; RV64-LMULMAX1-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
-; RV64-LMULMAX1-NEXT:    vfmv.f.s ft0, v9
-; RV64-LMULMAX1-NEXT:    fcvt.l.s a0, ft0, rtz
-; RV64-LMULMAX1-NEXT:    sb a0, 12(sp)
-; RV64-LMULMAX1-NEXT:    vfmv.f.s ft0, v8
-; RV64-LMULMAX1-NEXT:    fcvt.l.s a0, ft0, rtz
-; RV64-LMULMAX1-NEXT:    sb a0, 8(sp)
-; RV64-LMULMAX1-NEXT:    vsetivli zero, 1, e32,m1,ta,mu
-; RV64-LMULMAX1-NEXT:    vslidedown.vi v25, v9, 3
-; RV64-LMULMAX1-NEXT:    vfmv.f.s ft0, v25
-; RV64-LMULMAX1-NEXT:    fcvt.l.s a0, ft0, rtz
-; RV64-LMULMAX1-NEXT:    sb a0, 15(sp)
-; RV64-LMULMAX1-NEXT:    vslidedown.vi v25, v9, 2
-; RV64-LMULMAX1-NEXT:    vfmv.f.s ft0, v25
-; RV64-LMULMAX1-NEXT:    fcvt.l.s a0, ft0, rtz
-; RV64-LMULMAX1-NEXT:    sb a0, 14(sp)
-; RV64-LMULMAX1-NEXT:    vslidedown.vi v25, v9, 1
-; RV64-LMULMAX1-NEXT:    vfmv.f.s ft0, v25
-; RV64-LMULMAX1-NEXT:    fcvt.l.s a0, ft0, rtz
-; RV64-LMULMAX1-NEXT:    sb a0, 13(sp)
-; RV64-LMULMAX1-NEXT:    vslidedown.vi v25, v8, 3
-; RV64-LMULMAX1-NEXT:    vfmv.f.s ft0, v25
-; RV64-LMULMAX1-NEXT:    fcvt.l.s a0, ft0, rtz
-; RV64-LMULMAX1-NEXT:    sb a0, 11(sp)
-; RV64-LMULMAX1-NEXT:    vslidedown.vi v25, v8, 2
-; RV64-LMULMAX1-NEXT:    vfmv.f.s ft0, v25
-; RV64-LMULMAX1-NEXT:    fcvt.l.s a0, ft0, rtz
-; RV64-LMULMAX1-NEXT:    sb a0, 10(sp)
-; RV64-LMULMAX1-NEXT:    vslidedown.vi v25, v8, 1
-; RV64-LMULMAX1-NEXT:    vfmv.f.s ft0, v25
-; RV64-LMULMAX1-NEXT:    fcvt.l.s a0, ft0, rtz
-; RV64-LMULMAX1-NEXT:    sb a0, 9(sp)
-; RV64-LMULMAX1-NEXT:    vsetivli zero, 8, e8,mf2,ta,mu
-; RV64-LMULMAX1-NEXT:    addi a0, sp, 8
-; RV64-LMULMAX1-NEXT:    vle8.v v25, (a0)
-; RV64-LMULMAX1-NEXT:    vand.vi v25, v25, 1
-; RV64-LMULMAX1-NEXT:    vmsne.vi v0, v25, 0
-; RV64-LMULMAX1-NEXT:    addi sp, sp, 16
-; RV64-LMULMAX1-NEXT:    ret
+; LMULMAX1-LABEL: fp2si_v8f32_v8i1:
+; LMULMAX1:       # %bb.0:
+; LMULMAX1-NEXT:    vsetivli zero, 8, e8,mf2,ta,mu
+; LMULMAX1-NEXT:    vmv.v.i v25, 0
+; LMULMAX1-NEXT:    vmclr.m v0
+; LMULMAX1-NEXT:    vmerge.vim v26, v25, 1, v0
+; LMULMAX1-NEXT:    vsetivli zero, 4, e16,mf2,ta,mu
+; LMULMAX1-NEXT:    vfncvt.rtz.x.f.w v27, v8
+; LMULMAX1-NEXT:    vand.vi v27, v27, 1
+; LMULMAX1-NEXT:    vmsne.vi v0, v27, 0
+; LMULMAX1-NEXT:    vsetvli zero, zero, e8,mf4,ta,mu
+; LMULMAX1-NEXT:    vmv.v.i v27, 0
+; LMULMAX1-NEXT:    vmerge.vim v28, v27, 1, v0
+; LMULMAX1-NEXT:    vsetivli zero, 4, e8,mf2,tu,mu
+; LMULMAX1-NEXT:    vslideup.vi v26, v28, 0
+; LMULMAX1-NEXT:    vsetivli zero, 8, e8,mf2,ta,mu
+; LMULMAX1-NEXT:    vmsne.vi v0, v26, 0
+; LMULMAX1-NEXT:    vmerge.vim v25, v25, 1, v0
+; LMULMAX1-NEXT:    vsetivli zero, 4, e16,mf2,ta,mu
+; LMULMAX1-NEXT:    vfncvt.rtz.x.f.w v26, v9
+; LMULMAX1-NEXT:    vand.vi v26, v26, 1
+; LMULMAX1-NEXT:    vmsne.vi v0, v26, 0
+; LMULMAX1-NEXT:    vsetvli zero, zero, e8,mf4,ta,mu
+; LMULMAX1-NEXT:    vmerge.vim v26, v27, 1, v0
+; LMULMAX1-NEXT:    vsetivli zero, 8, e8,mf2,tu,mu
+; LMULMAX1-NEXT:    vslideup.vi v25, v26, 4
+; LMULMAX1-NEXT:    vsetvli zero, zero, e8,mf2,ta,mu
+; LMULMAX1-NEXT:    vmsne.vi v0, v25, 0
+; LMULMAX1-NEXT:    ret
   %z = fptosi <8 x float> %x to <8 x i1>
   ret <8 x i1> %z
 }
 
 define <8 x i1> @fp2ui_v8f32_v8i1(<8 x float> %x) {
-; RV32-LMULMAX8-LABEL: fp2ui_v8f32_v8i1:
-; RV32-LMULMAX8:       # %bb.0:
-; RV32-LMULMAX8-NEXT:    addi sp, sp, -16
-; RV32-LMULMAX8-NEXT:    .cfi_def_cfa_offset 16
-; RV32-LMULMAX8-NEXT:    vsetvli zero, zero, e32,m2,ta,mu
-; RV32-LMULMAX8-NEXT:    vfmv.f.s ft0, v8
-; RV32-LMULMAX8-NEXT:    fcvt.wu.s a0, ft0, rtz
-; RV32-LMULMAX8-NEXT:    sb a0, 8(sp)
-; RV32-LMULMAX8-NEXT:    vsetivli zero, 1, e32,m2,ta,mu
-; RV32-LMULMAX8-NEXT:    vslidedown.vi v26, v8, 7
-; RV32-LMULMAX8-NEXT:    vfmv.f.s ft0, v26
-; RV32-LMULMAX8-NEXT:    fcvt.wu.s a0, ft0, rtz
-; RV32-LMULMAX8-NEXT:    sb a0, 15(sp)
-; RV32-LMULMAX8-NEXT:    vslidedown.vi v26, v8, 6
-; RV32-LMULMAX8-NEXT:    vfmv.f.s ft0, v26
-; RV32-LMULMAX8-NEXT:    fcvt.wu.s a0, ft0, rtz
-; RV32-LMULMAX8-NEXT:    sb a0, 14(sp)
-; RV32-LMULMAX8-NEXT:    vslidedown.vi v26, v8, 5
-; RV32-LMULMAX8-NEXT:    vfmv.f.s ft0, v26
-; RV32-LMULMAX8-NEXT:    fcvt.wu.s a0, ft0, rtz
-; RV32-LMULMAX8-NEXT:    sb a0, 13(sp)
-; RV32-LMULMAX8-NEXT:    vslidedown.vi v26, v8, 4
-; RV32-LMULMAX8-NEXT:    vfmv.f.s ft0, v26
-; RV32-LMULMAX8-NEXT:    fcvt.wu.s a0, ft0, rtz
-; RV32-LMULMAX8-NEXT:    sb a0, 12(sp)
-; RV32-LMULMAX8-NEXT:    vslidedown.vi v26, v8, 3
-; RV32-LMULMAX8-NEXT:    vfmv.f.s ft0, v26
-; RV32-LMULMAX8-NEXT:    fcvt.wu.s a0, ft0, rtz
-; RV32-LMULMAX8-NEXT:    sb a0, 11(sp)
-; RV32-LMULMAX8-NEXT:    vslidedown.vi v26, v8, 2
-; RV32-LMULMAX8-NEXT:    vfmv.f.s ft0, v26
-; RV32-LMULMAX8-NEXT:    fcvt.wu.s a0, ft0, rtz
-; RV32-LMULMAX8-NEXT:    sb a0, 10(sp)
-; RV32-LMULMAX8-NEXT:    vslidedown.vi v26, v8, 1
-; RV32-LMULMAX8-NEXT:    vfmv.f.s ft0, v26
-; RV32-LMULMAX8-NEXT:    fcvt.wu.s a0, ft0, rtz
-; RV32-LMULMAX8-NEXT:    sb a0, 9(sp)
-; RV32-LMULMAX8-NEXT:    vsetivli zero, 8, e8,mf2,ta,mu
-; RV32-LMULMAX8-NEXT:    addi a0, sp, 8
-; RV32-LMULMAX8-NEXT:    vle8.v v25, (a0)
-; RV32-LMULMAX8-NEXT:    vand.vi v25, v25, 1
-; RV32-LMULMAX8-NEXT:    vmsne.vi v0, v25, 0
-; RV32-LMULMAX8-NEXT:    addi sp, sp, 16
-; RV32-LMULMAX8-NEXT:    ret
-;
-; RV64-LMULMAX8-LABEL: fp2ui_v8f32_v8i1:
-; RV64-LMULMAX8:       # %bb.0:
-; RV64-LMULMAX8-NEXT:    addi sp, sp, -16
-; RV64-LMULMAX8-NEXT:    .cfi_def_cfa_offset 16
-; RV64-LMULMAX8-NEXT:    vsetvli zero, zero, e32,m2,ta,mu
-; RV64-LMULMAX8-NEXT:    vfmv.f.s ft0, v8
-; RV64-LMULMAX8-NEXT:    fcvt.lu.s a0, ft0, rtz
-; RV64-LMULMAX8-NEXT:    sb a0, 8(sp)
-; RV64-LMULMAX8-NEXT:    vsetivli zero, 1, e32,m2,ta,mu
-; RV64-LMULMAX8-NEXT:    vslidedown.vi v26, v8, 7
-; RV64-LMULMAX8-NEXT:    vfmv.f.s ft0, v26
-; RV64-LMULMAX8-NEXT:    fcvt.lu.s a0, ft0, rtz
-; RV64-LMULMAX8-NEXT:    sb a0, 15(sp)
-; RV64-LMULMAX8-NEXT:    vslidedown.vi v26, v8, 6
-; RV64-LMULMAX8-NEXT:    vfmv.f.s ft0, v26
-; RV64-LMULMAX8-NEXT:    fcvt.lu.s a0, ft0, rtz
-; RV64-LMULMAX8-NEXT:    sb a0, 14(sp)
-; RV64-LMULMAX8-NEXT:    vslidedown.vi v26, v8, 5
-; RV64-LMULMAX8-NEXT:    vfmv.f.s ft0, v26
-; RV64-LMULMAX8-NEXT:    fcvt.lu.s a0, ft0, rtz
-; RV64-LMULMAX8-NEXT:    sb a0, 13(sp)
-; RV64-LMULMAX8-NEXT:    vslidedown.vi v26, v8, 4
-; RV64-LMULMAX8-NEXT:    vfmv.f.s ft0, v26
-; RV64-LMULMAX8-NEXT:    fcvt.lu.s a0, ft0, rtz
-; RV64-LMULMAX8-NEXT:    sb a0, 12(sp)
-; RV64-LMULMAX8-NEXT:    vslidedown.vi v26, v8, 3
-; RV64-LMULMAX8-NEXT:    vfmv.f.s ft0, v26
-; RV64-LMULMAX8-NEXT:    fcvt.lu.s a0, ft0, rtz
-; RV64-LMULMAX8-NEXT:    sb a0, 11(sp)
-; RV64-LMULMAX8-NEXT:    vslidedown.vi v26, v8, 2
-; RV64-LMULMAX8-NEXT:    vfmv.f.s ft0, v26
-; RV64-LMULMAX8-NEXT:    fcvt.lu.s a0, ft0, rtz
-; RV64-LMULMAX8-NEXT:    sb a0, 10(sp)
-; RV64-LMULMAX8-NEXT:    vslidedown.vi v26, v8, 1
-; RV64-LMULMAX8-NEXT:    vfmv.f.s ft0, v26
-; RV64-LMULMAX8-NEXT:    fcvt.lu.s a0, ft0, rtz
-; RV64-LMULMAX8-NEXT:    sb a0, 9(sp)
-; RV64-LMULMAX8-NEXT:    vsetivli zero, 8, e8,mf2,ta,mu
-; RV64-LMULMAX8-NEXT:    addi a0, sp, 8
-; RV64-LMULMAX8-NEXT:    vle8.v v25, (a0)
-; RV64-LMULMAX8-NEXT:    vand.vi v25, v25, 1
-; RV64-LMULMAX8-NEXT:    vmsne.vi v0, v25, 0
-; RV64-LMULMAX8-NEXT:    addi sp, sp, 16
-; RV64-LMULMAX8-NEXT:    ret
-;
-; RV32-LMULMAX1-LABEL: fp2ui_v8f32_v8i1:
-; RV32-LMULMAX1:       # %bb.0:
-; RV32-LMULMAX1-NEXT:    addi sp, sp, -16
-; RV32-LMULMAX1-NEXT:    .cfi_def_cfa_offset 16
-; RV32-LMULMAX1-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
-; RV32-LMULMAX1-NEXT:    vfmv.f.s ft0, v9
-; RV32-LMULMAX1-NEXT:    fcvt.wu.s a0, ft0, rtz
-; RV32-LMULMAX1-NEXT:    sb a0, 12(sp)
-; RV32-LMULMAX1-NEXT:    vfmv.f.s ft0, v8
-; RV32-LMULMAX1-NEXT:    fcvt.wu.s a0, ft0, rtz
-; RV32-LMULMAX1-NEXT:    sb a0, 8(sp)
-; RV32-LMULMAX1-NEXT:    vsetivli zero, 1, e32,m1,ta,mu
-; RV32-LMULMAX1-NEXT:    vslidedown.vi v25, v9, 3
-; RV32-LMULMAX1-NEXT:    vfmv.f.s ft0, v25
-; RV32-LMULMAX1-NEXT:    fcvt.wu.s a0, ft0, rtz
-; RV32-LMULMAX1-NEXT:    sb a0, 15(sp)
-; RV32-LMULMAX1-NEXT:    vslidedown.vi v25, v9, 2
-; RV32-LMULMAX1-NEXT:    vfmv.f.s ft0, v25
-; RV32-LMULMAX1-NEXT:    fcvt.wu.s a0, ft0, rtz
-; RV32-LMULMAX1-NEXT:    sb a0, 14(sp)
-; RV32-LMULMAX1-NEXT:    vslidedown.vi v25, v9, 1
-; RV32-LMULMAX1-NEXT:    vfmv.f.s ft0, v25
-; RV32-LMULMAX1-NEXT:    fcvt.wu.s a0, ft0, rtz
-; RV32-LMULMAX1-NEXT:    sb a0, 13(sp)
-; RV32-LMULMAX1-NEXT:    vslidedown.vi v25, v8, 3
-; RV32-LMULMAX1-NEXT:    vfmv.f.s ft0, v25
-; RV32-LMULMAX1-NEXT:    fcvt.wu.s a0, ft0, rtz
-; RV32-LMULMAX1-NEXT:    sb a0, 11(sp)
-; RV32-LMULMAX1-NEXT:    vslidedown.vi v25, v8, 2
-; RV32-LMULMAX1-NEXT:    vfmv.f.s ft0, v25
-; RV32-LMULMAX1-NEXT:    fcvt.wu.s a0, ft0, rtz
-; RV32-LMULMAX1-NEXT:    sb a0, 10(sp)
-; RV32-LMULMAX1-NEXT:    vslidedown.vi v25, v8, 1
-; RV32-LMULMAX1-NEXT:    vfmv.f.s ft0, v25
-; RV32-LMULMAX1-NEXT:    fcvt.wu.s a0, ft0, rtz
-; RV32-LMULMAX1-NEXT:    sb a0, 9(sp)
-; RV32-LMULMAX1-NEXT:    vsetivli zero, 8, e8,mf2,ta,mu
-; RV32-LMULMAX1-NEXT:    addi a0, sp, 8
-; RV32-LMULMAX1-NEXT:    vle8.v v25, (a0)
-; RV32-LMULMAX1-NEXT:    vand.vi v25, v25, 1
-; RV32-LMULMAX1-NEXT:    vmsne.vi v0, v25, 0
-; RV32-LMULMAX1-NEXT:    addi sp, sp, 16
-; RV32-LMULMAX1-NEXT:    ret
+; LMULMAX8-LABEL: fp2ui_v8f32_v8i1:
+; LMULMAX8:       # %bb.0:
+; LMULMAX8-NEXT:    vsetivli zero, 8, e16,m1,ta,mu
+; LMULMAX8-NEXT:    vfncvt.rtz.xu.f.w v25, v8
+; LMULMAX8-NEXT:    vand.vi v25, v25, 1
+; LMULMAX8-NEXT:    vmsne.vi v0, v25, 0
+; LMULMAX8-NEXT:    ret
 ;
-; RV64-LMULMAX1-LABEL: fp2ui_v8f32_v8i1:
-; RV64-LMULMAX1:       # %bb.0:
-; RV64-LMULMAX1-NEXT:    addi sp, sp, -16
-; RV64-LMULMAX1-NEXT:    .cfi_def_cfa_offset 16
-; RV64-LMULMAX1-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
-; RV64-LMULMAX1-NEXT:    vfmv.f.s ft0, v9
-; RV64-LMULMAX1-NEXT:    fcvt.lu.s a0, ft0, rtz
-; RV64-LMULMAX1-NEXT:    sb a0, 12(sp)
-; RV64-LMULMAX1-NEXT:    vfmv.f.s ft0, v8
-; RV64-LMULMAX1-NEXT:    fcvt.lu.s a0, ft0, rtz
-; RV64-LMULMAX1-NEXT:    sb a0, 8(sp)
-; RV64-LMULMAX1-NEXT:    vsetivli zero, 1, e32,m1,ta,mu
-; RV64-LMULMAX1-NEXT:    vslidedown.vi v25, v9, 3
-; RV64-LMULMAX1-NEXT:    vfmv.f.s ft0, v25
-; RV64-LMULMAX1-NEXT:    fcvt.lu.s a0, ft0, rtz
-; RV64-LMULMAX1-NEXT:    sb a0, 15(sp)
-; RV64-LMULMAX1-NEXT:    vslidedown.vi v25, v9, 2
-; RV64-LMULMAX1-NEXT:    vfmv.f.s ft0, v25
-; RV64-LMULMAX1-NEXT:    fcvt.lu.s a0, ft0, rtz
-; RV64-LMULMAX1-NEXT:    sb a0, 14(sp)
-; RV64-LMULMAX1-NEXT:    vslidedown.vi v25, v9, 1
-; RV64-LMULMAX1-NEXT:    vfmv.f.s ft0, v25
-; RV64-LMULMAX1-NEXT:    fcvt.lu.s a0, ft0, rtz
-; RV64-LMULMAX1-NEXT:    sb a0, 13(sp)
-; RV64-LMULMAX1-NEXT:    vslidedown.vi v25, v8, 3
-; RV64-LMULMAX1-NEXT:    vfmv.f.s ft0, v25
-; RV64-LMULMAX1-NEXT:    fcvt.lu.s a0, ft0, rtz
-; RV64-LMULMAX1-NEXT:    sb a0, 11(sp)
-; RV64-LMULMAX1-NEXT:    vslidedown.vi v25, v8, 2
-; RV64-LMULMAX1-NEXT:    vfmv.f.s ft0, v25
-; RV64-LMULMAX1-NEXT:    fcvt.lu.s a0, ft0, rtz
-; RV64-LMULMAX1-NEXT:    sb a0, 10(sp)
-; RV64-LMULMAX1-NEXT:    vslidedown.vi v25, v8, 1
-; RV64-LMULMAX1-NEXT:    vfmv.f.s ft0, v25
-; RV64-LMULMAX1-NEXT:    fcvt.lu.s a0, ft0, rtz
-; RV64-LMULMAX1-NEXT:    sb a0, 9(sp)
-; RV64-LMULMAX1-NEXT:    vsetivli zero, 8, e8,mf2,ta,mu
-; RV64-LMULMAX1-NEXT:    addi a0, sp, 8
-; RV64-LMULMAX1-NEXT:    vle8.v v25, (a0)
-; RV64-LMULMAX1-NEXT:    vand.vi v25, v25, 1
-; RV64-LMULMAX1-NEXT:    vmsne.vi v0, v25, 0
-; RV64-LMULMAX1-NEXT:    addi sp, sp, 16
-; RV64-LMULMAX1-NEXT:    ret
+; LMULMAX1-LABEL: fp2ui_v8f32_v8i1:
+; LMULMAX1:       # %bb.0:
+; LMULMAX1-NEXT:    vsetivli zero, 8, e8,mf2,ta,mu
+; LMULMAX1-NEXT:    vmv.v.i v25, 0
+; LMULMAX1-NEXT:    vmclr.m v0
+; LMULMAX1-NEXT:    vmerge.vim v26, v25, 1, v0
+; LMULMAX1-NEXT:    vsetivli zero, 4, e16,mf2,ta,mu
+; LMULMAX1-NEXT:    vfncvt.rtz.xu.f.w v27, v8
+; LMULMAX1-NEXT:    vand.vi v27, v27, 1
+; LMULMAX1-NEXT:    vmsne.vi v0, v27, 0
+; LMULMAX1-NEXT:    vsetvli zero, zero, e8,mf4,ta,mu
+; LMULMAX1-NEXT:    vmv.v.i v27, 0
+; LMULMAX1-NEXT:    vmerge.vim v28, v27, 1, v0
+; LMULMAX1-NEXT:    vsetivli zero, 4, e8,mf2,tu,mu
+; LMULMAX1-NEXT:    vslideup.vi v26, v28, 0
+; LMULMAX1-NEXT:    vsetivli zero, 8, e8,mf2,ta,mu
+; LMULMAX1-NEXT:    vmsne.vi v0, v26, 0
+; LMULMAX1-NEXT:    vmerge.vim v25, v25, 1, v0
+; LMULMAX1-NEXT:    vsetivli zero, 4, e16,mf2,ta,mu
+; LMULMAX1-NEXT:    vfncvt.rtz.xu.f.w v26, v9
+; LMULMAX1-NEXT:    vand.vi v26, v26, 1
+; LMULMAX1-NEXT:    vmsne.vi v0, v26, 0
+; LMULMAX1-NEXT:    vsetvli zero, zero, e8,mf4,ta,mu
+; LMULMAX1-NEXT:    vmerge.vim v26, v27, 1, v0
+; LMULMAX1-NEXT:    vsetivli zero, 8, e8,mf2,tu,mu
+; LMULMAX1-NEXT:    vslideup.vi v25, v26, 4
+; LMULMAX1-NEXT:    vsetvli zero, zero, e8,mf2,ta,mu
+; LMULMAX1-NEXT:    vmsne.vi v0, v25, 0
+; LMULMAX1-NEXT:    ret
   %z = fptoui <8 x float> %x to <8 x i1>
   ret <8 x i1> %z
 }
@@ -673,77 +341,25 @@ define void @fp2ui_v2f16_v2i64(<2 x half>* %x, <2 x i64>* %y) {
 }
 
 define <2 x i1> @fp2si_v2f16_v2i1(<2 x half> %x) {
-; RV32-LABEL: fp2si_v2f16_v2i1:
-; RV32:       # %bb.0:
-; RV32-NEXT:    vsetivli zero, 1, e16,mf4,ta,mu
-; RV32-NEXT:    vslidedown.vi v25, v8, 1
-; RV32-NEXT:    vfmv.f.s ft0, v25
-; RV32-NEXT:    fcvt.w.h a0, ft0, rtz
-; RV32-NEXT:    vsetivli zero, 2, e8,mf8,ta,mu
-; RV32-NEXT:    vmv.v.x v25, a0
-; RV32-NEXT:    vsetvli zero, zero, e16,mf4,ta,mu
-; RV32-NEXT:    vfmv.f.s ft0, v8
-; RV32-NEXT:    fcvt.w.h a0, ft0, rtz
-; RV32-NEXT:    vsetivli zero, 2, e8,mf8,ta,mu
-; RV32-NEXT:    vmv.s.x v25, a0
-; RV32-NEXT:    vand.vi v25, v25, 1
-; RV32-NEXT:    vmsne.vi v0, v25, 0
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: fp2si_v2f16_v2i1:
-; RV64:       # %bb.0:
-; RV64-NEXT:    vsetivli zero, 1, e16,mf4,ta,mu
-; RV64-NEXT:    vslidedown.vi v25, v8, 1
-; RV64-NEXT:    vfmv.f.s ft0, v25
-; RV64-NEXT:    fcvt.l.h a0, ft0, rtz
-; RV64-NEXT:    vsetivli zero, 2, e8,mf8,ta,mu
-; RV64-NEXT:    vmv.v.x v25, a0
-; RV64-NEXT:    vsetvli zero, zero, e16,mf4,ta,mu
-; RV64-NEXT:    vfmv.f.s ft0, v8
-; RV64-NEXT:    fcvt.l.h a0, ft0, rtz
-; RV64-NEXT:    vsetivli zero, 2, e8,mf8,ta,mu
-; RV64-NEXT:    vmv.s.x v25, a0
-; RV64-NEXT:    vand.vi v25, v25, 1
-; RV64-NEXT:    vmsne.vi v0, v25, 0
-; RV64-NEXT:    ret
+; CHECK-LABEL: fp2si_v2f16_v2i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 2, e8,mf8,ta,mu
+; CHECK-NEXT:    vfncvt.rtz.x.f.w v25, v8
+; CHECK-NEXT:    vand.vi v25, v25, 1
+; CHECK-NEXT:    vmsne.vi v0, v25, 0
+; CHECK-NEXT:    ret
   %z = fptosi <2 x half> %x to <2 x i1>
   ret <2 x i1> %z
 }
 
 define <2 x i1> @fp2ui_v2f16_v2i1(<2 x half> %x) {
-; RV32-LABEL: fp2ui_v2f16_v2i1:
-; RV32:       # %bb.0:
-; RV32-NEXT:    vsetivli zero, 1, e16,mf4,ta,mu
-; RV32-NEXT:    vslidedown.vi v25, v8, 1
-; RV32-NEXT:    vfmv.f.s ft0, v25
-; RV32-NEXT:    fcvt.wu.h a0, ft0, rtz
-; RV32-NEXT:    vsetivli zero, 2, e8,mf8,ta,mu
-; RV32-NEXT:    vmv.v.x v25, a0
-; RV32-NEXT:    vsetvli zero, zero, e16,mf4,ta,mu
-; RV32-NEXT:    vfmv.f.s ft0, v8
-; RV32-NEXT:    fcvt.wu.h a0, ft0, rtz
-; RV32-NEXT:    vsetivli zero, 2, e8,mf8,ta,mu
-; RV32-NEXT:    vmv.s.x v25, a0
-; RV32-NEXT:    vand.vi v25, v25, 1
-; RV32-NEXT:    vmsne.vi v0, v25, 0
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: fp2ui_v2f16_v2i1:
-; RV64:       # %bb.0:
-; RV64-NEXT:    vsetivli zero, 1, e16,mf4,ta,mu
-; RV64-NEXT:    vslidedown.vi v25, v8, 1
-; RV64-NEXT:    vfmv.f.s ft0, v25
-; RV64-NEXT:    fcvt.lu.h a0, ft0, rtz
-; RV64-NEXT:    vsetivli zero, 2, e8,mf8,ta,mu
-; RV64-NEXT:    vmv.v.x v25, a0
-; RV64-NEXT:    vsetvli zero, zero, e16,mf4,ta,mu
-; RV64-NEXT:    vfmv.f.s ft0, v8
-; RV64-NEXT:    fcvt.lu.h a0, ft0, rtz
-; RV64-NEXT:    vsetivli zero, 2, e8,mf8,ta,mu
-; RV64-NEXT:    vmv.s.x v25, a0
-; RV64-NEXT:    vand.vi v25, v25, 1
-; RV64-NEXT:    vmsne.vi v0, v25, 0
-; RV64-NEXT:    ret
+; CHECK-LABEL: fp2ui_v2f16_v2i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 2, e8,mf8,ta,mu
+; CHECK-NEXT:    vfncvt.rtz.xu.f.w v25, v8
+; CHECK-NEXT:    vand.vi v25, v25, 1
+; CHECK-NEXT:    vmsne.vi v0, v25, 0
+; CHECK-NEXT:    ret
   %z = fptoui <2 x half> %x to <2 x i1>
   ret <2 x i1> %z
 }
@@ -787,77 +403,25 @@ define void @fp2ui_v2f64_v2i8(<2 x double>* %x, <2 x i8>* %y) {
 }
 
 define <2 x i1> @fp2si_v2f64_v2i1(<2 x double> %x) {
-; RV32-LABEL: fp2si_v2f64_v2i1:
-; RV32:       # %bb.0:
-; RV32-NEXT:    vsetivli zero, 1, e64,m1,ta,mu
-; RV32-NEXT:    vslidedown.vi v25, v8, 1
-; RV32-NEXT:    vfmv.f.s ft0, v25
-; RV32-NEXT:    fcvt.w.d a0, ft0, rtz
-; RV32-NEXT:    vsetivli zero, 2, e8,mf8,ta,mu
-; RV32-NEXT:    vmv.v.x v25, a0
-; RV32-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
-; RV32-NEXT:    vfmv.f.s ft0, v8
-; RV32-NEXT:    fcvt.w.d a0, ft0, rtz
-; RV32-NEXT:    vsetivli zero, 2, e8,mf8,ta,mu
-; RV32-NEXT:    vmv.s.x v25, a0
-; RV32-NEXT:    vand.vi v25, v25, 1
-; RV32-NEXT:    vmsne.vi v0, v25, 0
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: fp2si_v2f64_v2i1:
-; RV64:       # %bb.0:
-; RV64-NEXT:    vsetivli zero, 1, e64,m1,ta,mu
-; RV64-NEXT:    vslidedown.vi v25, v8, 1
-; RV64-NEXT:    vfmv.f.s ft0, v25
-; RV64-NEXT:    fcvt.l.d a0, ft0, rtz
-; RV64-NEXT:    vsetivli zero, 2, e8,mf8,ta,mu
-; RV64-NEXT:    vmv.v.x v25, a0
-; RV64-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
-; RV64-NEXT:    vfmv.f.s ft0, v8
-; RV64-NEXT:    fcvt.l.d a0, ft0, rtz
-; RV64-NEXT:    vsetivli zero, 2, e8,mf8,ta,mu
-; RV64-NEXT:    vmv.s.x v25, a0
-; RV64-NEXT:    vand.vi v25, v25, 1
-; RV64-NEXT:    vmsne.vi v0, v25, 0
-; RV64-NEXT:    ret
+; CHECK-LABEL: fp2si_v2f64_v2i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 2, e32,mf2,ta,mu
+; CHECK-NEXT:    vfncvt.rtz.x.f.w v25, v8
+; CHECK-NEXT:    vand.vi v25, v25, 1
+; CHECK-NEXT:    vmsne.vi v0, v25, 0
+; CHECK-NEXT:    ret
   %z = fptosi <2 x double> %x to <2 x i1>
   ret <2 x i1> %z
 }
 
 define <2 x i1> @fp2ui_v2f64_v2i1(<2 x double> %x) {
-; RV32-LABEL: fp2ui_v2f64_v2i1:
-; RV32:       # %bb.0:
-; RV32-NEXT:    vsetivli zero, 1, e64,m1,ta,mu
-; RV32-NEXT:    vslidedown.vi v25, v8, 1
-; RV32-NEXT:    vfmv.f.s ft0, v25
-; RV32-NEXT:    fcvt.wu.d a0, ft0, rtz
-; RV32-NEXT:    vsetivli zero, 2, e8,mf8,ta,mu
-; RV32-NEXT:    vmv.v.x v25, a0
-; RV32-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
-; RV32-NEXT:    vfmv.f.s ft0, v8
-; RV32-NEXT:    fcvt.wu.d a0, ft0, rtz
-; RV32-NEXT:    vsetivli zero, 2, e8,mf8,ta,mu
-; RV32-NEXT:    vmv.s.x v25, a0
-; RV32-NEXT:    vand.vi v25, v25, 1
-; RV32-NEXT:    vmsne.vi v0, v25, 0
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: fp2ui_v2f64_v2i1:
-; RV64:       # %bb.0:
-; RV64-NEXT:    vsetivli zero, 1, e64,m1,ta,mu
-; RV64-NEXT:    vslidedown.vi v25, v8, 1
-; RV64-NEXT:    vfmv.f.s ft0, v25
-; RV64-NEXT:    fcvt.lu.d a0, ft0, rtz
-; RV64-NEXT:    vsetivli zero, 2, e8,mf8,ta,mu
-; RV64-NEXT:    vmv.v.x v25, a0
-; RV64-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
-; RV64-NEXT:    vfmv.f.s ft0, v8
-; RV64-NEXT:    fcvt.lu.d a0, ft0, rtz
-; RV64-NEXT:    vsetivli zero, 2, e8,mf8,ta,mu
-; RV64-NEXT:    vmv.s.x v25, a0
-; RV64-NEXT:    vand.vi v25, v25, 1
-; RV64-NEXT:    vmsne.vi v0, v25, 0
-; RV64-NEXT:    ret
+; CHECK-LABEL: fp2ui_v2f64_v2i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 2, e32,mf2,ta,mu
+; CHECK-NEXT:    vfncvt.rtz.xu.f.w v25, v8
+; CHECK-NEXT:    vand.vi v25, v25, 1
+; CHECK-NEXT:    vmsne.vi v0, v25, 0
+; CHECK-NEXT:    ret
   %z = fptoui <2 x double> %x to <2 x i1>
   ret <2 x i1> %z
 }
@@ -1011,357 +575,159 @@ define void @fp2ui_v8f64_v8i8(<8 x double>* %x, <8 x i8>* %y) {
 }
 
 define <8 x i1> @fp2si_v8f64_v8i1(<8 x double> %x) {
-; RV32-LMULMAX8-LABEL: fp2si_v8f64_v8i1:
-; RV32-LMULMAX8:       # %bb.0:
-; RV32-LMULMAX8-NEXT:    addi sp, sp, -16
-; RV32-LMULMAX8-NEXT:    .cfi_def_cfa_offset 16
-; RV32-LMULMAX8-NEXT:    vsetvli zero, zero, e64,m4,ta,mu
-; RV32-LMULMAX8-NEXT:    vfmv.f.s ft0, v8
-; RV32-LMULMAX8-NEXT:    fcvt.w.d a0, ft0, rtz
-; RV32-LMULMAX8-NEXT:    sb a0, 8(sp)
-; RV32-LMULMAX8-NEXT:    vsetivli zero, 1, e64,m4,ta,mu
-; RV32-LMULMAX8-NEXT:    vslidedown.vi v28, v8, 7
-; RV32-LMULMAX8-NEXT:    vfmv.f.s ft0, v28
-; RV32-LMULMAX8-NEXT:    fcvt.w.d a0, ft0, rtz
-; RV32-LMULMAX8-NEXT:    sb a0, 15(sp)
-; RV32-LMULMAX8-NEXT:    vslidedown.vi v28, v8, 6
-; RV32-LMULMAX8-NEXT:    vfmv.f.s ft0, v28
-; RV32-LMULMAX8-NEXT:    fcvt.w.d a0, ft0, rtz
-; RV32-LMULMAX8-NEXT:    sb a0, 14(sp)
-; RV32-LMULMAX8-NEXT:    vslidedown.vi v28, v8, 5
-; RV32-LMULMAX8-NEXT:    vfmv.f.s ft0, v28
-; RV32-LMULMAX8-NEXT:    fcvt.w.d a0, ft0, rtz
-; RV32-LMULMAX8-NEXT:    sb a0, 13(sp)
-; RV32-LMULMAX8-NEXT:    vslidedown.vi v28, v8, 4
-; RV32-LMULMAX8-NEXT:    vfmv.f.s ft0, v28
-; RV32-LMULMAX8-NEXT:    fcvt.w.d a0, ft0, rtz
-; RV32-LMULMAX8-NEXT:    sb a0, 12(sp)
-; RV32-LMULMAX8-NEXT:    vslidedown.vi v28, v8, 3
-; RV32-LMULMAX8-NEXT:    vfmv.f.s ft0, v28
-; RV32-LMULMAX8-NEXT:    fcvt.w.d a0, ft0, rtz
-; RV32-LMULMAX8-NEXT:    sb a0, 11(sp)
-; RV32-LMULMAX8-NEXT:    vslidedown.vi v28, v8, 2
-; RV32-LMULMAX8-NEXT:    vfmv.f.s ft0, v28
-; RV32-LMULMAX8-NEXT:    fcvt.w.d a0, ft0, rtz
-; RV32-LMULMAX8-NEXT:    sb a0, 10(sp)
-; RV32-LMULMAX8-NEXT:    vslidedown.vi v28, v8, 1
-; RV32-LMULMAX8-NEXT:    vfmv.f.s ft0, v28
-; RV32-LMULMAX8-NEXT:    fcvt.w.d a0, ft0, rtz
-; RV32-LMULMAX8-NEXT:    sb a0, 9(sp)
-; RV32-LMULMAX8-NEXT:    vsetivli zero, 8, e8,mf2,ta,mu
-; RV32-LMULMAX8-NEXT:    addi a0, sp, 8
-; RV32-LMULMAX8-NEXT:    vle8.v v25, (a0)
-; RV32-LMULMAX8-NEXT:    vand.vi v25, v25, 1
-; RV32-LMULMAX8-NEXT:    vmsne.vi v0, v25, 0
-; RV32-LMULMAX8-NEXT:    addi sp, sp, 16
-; RV32-LMULMAX8-NEXT:    ret
-;
-; RV64-LMULMAX8-LABEL: fp2si_v8f64_v8i1:
-; RV64-LMULMAX8:       # %bb.0:
-; RV64-LMULMAX8-NEXT:    addi sp, sp, -16
-; RV64-LMULMAX8-NEXT:    .cfi_def_cfa_offset 16
-; RV64-LMULMAX8-NEXT:    vsetvli zero, zero, e64,m4,ta,mu
-; RV64-LMULMAX8-NEXT:    vfmv.f.s ft0, v8
-; RV64-LMULMAX8-NEXT:    fcvt.l.d a0, ft0, rtz
-; RV64-LMULMAX8-NEXT:    sb a0, 8(sp)
-; RV64-LMULMAX8-NEXT:    vsetivli zero, 1, e64,m4,ta,mu
-; RV64-LMULMAX8-NEXT:    vslidedown.vi v28, v8, 7
-; RV64-LMULMAX8-NEXT:    vfmv.f.s ft0, v28
-; RV64-LMULMAX8-NEXT:    fcvt.l.d a0, ft0, rtz
-; RV64-LMULMAX8-NEXT:    sb a0, 15(sp)
-; RV64-LMULMAX8-NEXT:    vslidedown.vi v28, v8, 6
-; RV64-LMULMAX8-NEXT:    vfmv.f.s ft0, v28
-; RV64-LMULMAX8-NEXT:    fcvt.l.d a0, ft0, rtz
-; RV64-LMULMAX8-NEXT:    sb a0, 14(sp)
-; RV64-LMULMAX8-NEXT:    vslidedown.vi v28, v8, 5
-; RV64-LMULMAX8-NEXT:    vfmv.f.s ft0, v28
-; RV64-LMULMAX8-NEXT:    fcvt.l.d a0, ft0, rtz
-; RV64-LMULMAX8-NEXT:    sb a0, 13(sp)
-; RV64-LMULMAX8-NEXT:    vslidedown.vi v28, v8, 4
-; RV64-LMULMAX8-NEXT:    vfmv.f.s ft0, v28
-; RV64-LMULMAX8-NEXT:    fcvt.l.d a0, ft0, rtz
-; RV64-LMULMAX8-NEXT:    sb a0, 12(sp)
-; RV64-LMULMAX8-NEXT:    vslidedown.vi v28, v8, 3
-; RV64-LMULMAX8-NEXT:    vfmv.f.s ft0, v28
-; RV64-LMULMAX8-NEXT:    fcvt.l.d a0, ft0, rtz
-; RV64-LMULMAX8-NEXT:    sb a0, 11(sp)
-; RV64-LMULMAX8-NEXT:    vslidedown.vi v28, v8, 2
-; RV64-LMULMAX8-NEXT:    vfmv.f.s ft0, v28
-; RV64-LMULMAX8-NEXT:    fcvt.l.d a0, ft0, rtz
-; RV64-LMULMAX8-NEXT:    sb a0, 10(sp)
-; RV64-LMULMAX8-NEXT:    vslidedown.vi v28, v8, 1
-; RV64-LMULMAX8-NEXT:    vfmv.f.s ft0, v28
-; RV64-LMULMAX8-NEXT:    fcvt.l.d a0, ft0, rtz
-; RV64-LMULMAX8-NEXT:    sb a0, 9(sp)
-; RV64-LMULMAX8-NEXT:    vsetivli zero, 8, e8,mf2,ta,mu
-; RV64-LMULMAX8-NEXT:    addi a0, sp, 8
-; RV64-LMULMAX8-NEXT:    vle8.v v25, (a0)
-; RV64-LMULMAX8-NEXT:    vand.vi v25, v25, 1
-; RV64-LMULMAX8-NEXT:    vmsne.vi v0, v25, 0
-; RV64-LMULMAX8-NEXT:    addi sp, sp, 16
-; RV64-LMULMAX8-NEXT:    ret
-;
-; RV32-LMULMAX1-LABEL: fp2si_v8f64_v8i1:
-; RV32-LMULMAX1:       # %bb.0:
-; RV32-LMULMAX1-NEXT:    addi sp, sp, -16
-; RV32-LMULMAX1-NEXT:    .cfi_def_cfa_offset 16
-; RV32-LMULMAX1-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
-; RV32-LMULMAX1-NEXT:    vfmv.f.s ft0, v11
-; RV32-LMULMAX1-NEXT:    fcvt.w.d a0, ft0, rtz
-; RV32-LMULMAX1-NEXT:    sb a0, 14(sp)
-; RV32-LMULMAX1-NEXT:    vfmv.f.s ft0, v10
-; RV32-LMULMAX1-NEXT:    fcvt.w.d a0, ft0, rtz
-; RV32-LMULMAX1-NEXT:    sb a0, 12(sp)
-; RV32-LMULMAX1-NEXT:    vfmv.f.s ft0, v9
-; RV32-LMULMAX1-NEXT:    fcvt.w.d a0, ft0, rtz
-; RV32-LMULMAX1-NEXT:    sb a0, 10(sp)
-; RV32-LMULMAX1-NEXT:    vfmv.f.s ft0, v8
-; RV32-LMULMAX1-NEXT:    fcvt.w.d a0, ft0, rtz
-; RV32-LMULMAX1-NEXT:    sb a0, 8(sp)
-; RV32-LMULMAX1-NEXT:    vsetivli zero, 1, e64,m1,ta,mu
-; RV32-LMULMAX1-NEXT:    vslidedown.vi v25, v11, 1
-; RV32-LMULMAX1-NEXT:    vfmv.f.s ft0, v25
-; RV32-LMULMAX1-NEXT:    fcvt.w.d a0, ft0, rtz
-; RV32-LMULMAX1-NEXT:    sb a0, 15(sp)
-; RV32-LMULMAX1-NEXT:    vslidedown.vi v25, v10, 1
-; RV32-LMULMAX1-NEXT:    vfmv.f.s ft0, v25
-; RV32-LMULMAX1-NEXT:    fcvt.w.d a0, ft0, rtz
-; RV32-LMULMAX1-NEXT:    sb a0, 13(sp)
-; RV32-LMULMAX1-NEXT:    vslidedown.vi v25, v9, 1
-; RV32-LMULMAX1-NEXT:    vfmv.f.s ft0, v25
-; RV32-LMULMAX1-NEXT:    fcvt.w.d a0, ft0, rtz
-; RV32-LMULMAX1-NEXT:    sb a0, 11(sp)
-; RV32-LMULMAX1-NEXT:    vslidedown.vi v25, v8, 1
-; RV32-LMULMAX1-NEXT:    vfmv.f.s ft0, v25
-; RV32-LMULMAX1-NEXT:    fcvt.w.d a0, ft0, rtz
-; RV32-LMULMAX1-NEXT:    sb a0, 9(sp)
-; RV32-LMULMAX1-NEXT:    vsetivli zero, 8, e8,mf2,ta,mu
-; RV32-LMULMAX1-NEXT:    addi a0, sp, 8
-; RV32-LMULMAX1-NEXT:    vle8.v v25, (a0)
-; RV32-LMULMAX1-NEXT:    vand.vi v25, v25, 1
-; RV32-LMULMAX1-NEXT:    vmsne.vi v0, v25, 0
-; RV32-LMULMAX1-NEXT:    addi sp, sp, 16
-; RV32-LMULMAX1-NEXT:    ret
+; LMULMAX8-LABEL: fp2si_v8f64_v8i1:
+; LMULMAX8:       # %bb.0:
+; LMULMAX8-NEXT:    vsetivli zero, 8, e32,m2,ta,mu
+; LMULMAX8-NEXT:    vfncvt.rtz.x.f.w v26, v8
+; LMULMAX8-NEXT:    vand.vi v26, v26, 1
+; LMULMAX8-NEXT:    vmsne.vi v0, v26, 0
+; LMULMAX8-NEXT:    ret
 ;
-; RV64-LMULMAX1-LABEL: fp2si_v8f64_v8i1:
-; RV64-LMULMAX1:       # %bb.0:
-; RV64-LMULMAX1-NEXT:    addi sp, sp, -16
-; RV64-LMULMAX1-NEXT:    .cfi_def_cfa_offset 16
-; RV64-LMULMAX1-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
-; RV64-LMULMAX1-NEXT:    vfmv.f.s ft0, v11
-; RV64-LMULMAX1-NEXT:    fcvt.l.d a0, ft0, rtz
-; RV64-LMULMAX1-NEXT:    sb a0, 14(sp)
-; RV64-LMULMAX1-NEXT:    vfmv.f.s ft0, v10
-; RV64-LMULMAX1-NEXT:    fcvt.l.d a0, ft0, rtz
-; RV64-LMULMAX1-NEXT:    sb a0, 12(sp)
-; RV64-LMULMAX1-NEXT:    vfmv.f.s ft0, v9
-; RV64-LMULMAX1-NEXT:    fcvt.l.d a0, ft0, rtz
-; RV64-LMULMAX1-NEXT:    sb a0, 10(sp)
-; RV64-LMULMAX1-NEXT:    vfmv.f.s ft0, v8
-; RV64-LMULMAX1-NEXT:    fcvt.l.d a0, ft0, rtz
-; RV64-LMULMAX1-NEXT:    sb a0, 8(sp)
-; RV64-LMULMAX1-NEXT:    vsetivli zero, 1, e64,m1,ta,mu
-; RV64-LMULMAX1-NEXT:    vslidedown.vi v25, v11, 1
-; RV64-LMULMAX1-NEXT:    vfmv.f.s ft0, v25
-; RV64-LMULMAX1-NEXT:    fcvt.l.d a0, ft0, rtz
-; RV64-LMULMAX1-NEXT:    sb a0, 15(sp)
-; RV64-LMULMAX1-NEXT:    vslidedown.vi v25, v10, 1
-; RV64-LMULMAX1-NEXT:    vfmv.f.s ft0, v25
-; RV64-LMULMAX1-NEXT:    fcvt.l.d a0, ft0, rtz
-; RV64-LMULMAX1-NEXT:    sb a0, 13(sp)
-; RV64-LMULMAX1-NEXT:    vslidedown.vi v25, v9, 1
-; RV64-LMULMAX1-NEXT:    vfmv.f.s ft0, v25
-; RV64-LMULMAX1-NEXT:    fcvt.l.d a0, ft0, rtz
-; RV64-LMULMAX1-NEXT:    sb a0, 11(sp)
-; RV64-LMULMAX1-NEXT:    vslidedown.vi v25, v8, 1
-; RV64-LMULMAX1-NEXT:    vfmv.f.s ft0, v25
-; RV64-LMULMAX1-NEXT:    fcvt.l.d a0, ft0, rtz
-; RV64-LMULMAX1-NEXT:    sb a0, 9(sp)
-; RV64-LMULMAX1-NEXT:    vsetivli zero, 8, e8,mf2,ta,mu
-; RV64-LMULMAX1-NEXT:    addi a0, sp, 8
-; RV64-LMULMAX1-NEXT:    vle8.v v25, (a0)
-; RV64-LMULMAX1-NEXT:    vand.vi v25, v25, 1
-; RV64-LMULMAX1-NEXT:    vmsne.vi v0, v25, 0
-; RV64-LMULMAX1-NEXT:    addi sp, sp, 16
-; RV64-LMULMAX1-NEXT:    ret
+; LMULMAX1-LABEL: fp2si_v8f64_v8i1:
+; LMULMAX1:       # %bb.0:
+; LMULMAX1-NEXT:    vsetivli zero, 4, e8,mf4,ta,mu
+; LMULMAX1-NEXT:    vmv.v.i v25, 0
+; LMULMAX1-NEXT:    vmclr.m v0
+; LMULMAX1-NEXT:    vmerge.vim v26, v25, 1, v0
+; LMULMAX1-NEXT:    vsetivli zero, 2, e32,mf2,ta,mu
+; LMULMAX1-NEXT:    vfncvt.rtz.x.f.w v27, v8
+; LMULMAX1-NEXT:    vand.vi v27, v27, 1
+; LMULMAX1-NEXT:    vmsne.vi v0, v27, 0
+; LMULMAX1-NEXT:    vsetvli zero, zero, e8,mf8,ta,mu
+; LMULMAX1-NEXT:    vmv.v.i v27, 0
+; LMULMAX1-NEXT:    vmerge.vim v28, v27, 1, v0
+; LMULMAX1-NEXT:    vsetivli zero, 2, e8,mf4,tu,mu
+; LMULMAX1-NEXT:    vmv1r.v v29, v26
+; LMULMAX1-NEXT:    vslideup.vi v29, v28, 0
+; LMULMAX1-NEXT:    vsetivli zero, 4, e8,mf4,ta,mu
+; LMULMAX1-NEXT:    vmsne.vi v0, v29, 0
+; LMULMAX1-NEXT:    vmerge.vim v28, v25, 1, v0
+; LMULMAX1-NEXT:    vsetivli zero, 2, e32,mf2,ta,mu
+; LMULMAX1-NEXT:    vfncvt.rtz.x.f.w v29, v9
+; LMULMAX1-NEXT:    vand.vi v29, v29, 1
+; LMULMAX1-NEXT:    vmsne.vi v0, v29, 0
+; LMULMAX1-NEXT:    vsetvli zero, zero, e8,mf8,ta,mu
+; LMULMAX1-NEXT:    vmerge.vim v29, v27, 1, v0
+; LMULMAX1-NEXT:    vsetivli zero, 4, e8,mf4,tu,mu
+; LMULMAX1-NEXT:    vslideup.vi v28, v29, 2
+; LMULMAX1-NEXT:    vsetvli zero, zero, e8,mf4,ta,mu
+; LMULMAX1-NEXT:    vmsne.vi v0, v28, 0
+; LMULMAX1-NEXT:    vmerge.vim v28, v25, 1, v0
+; LMULMAX1-NEXT:    vsetivli zero, 8, e8,mf2,ta,mu
+; LMULMAX1-NEXT:    vmv.v.i v29, 0
+; LMULMAX1-NEXT:    vmclr.m v0
+; LMULMAX1-NEXT:    vmerge.vim v30, v29, 1, v0
+; LMULMAX1-NEXT:    vsetivli zero, 4, e8,mf2,tu,mu
+; LMULMAX1-NEXT:    vslideup.vi v30, v28, 0
+; LMULMAX1-NEXT:    vsetivli zero, 8, e8,mf2,ta,mu
+; LMULMAX1-NEXT:    vmsne.vi v0, v30, 0
+; LMULMAX1-NEXT:    vmerge.vim v28, v29, 1, v0
+; LMULMAX1-NEXT:    vsetivli zero, 2, e32,mf2,ta,mu
+; LMULMAX1-NEXT:    vfncvt.rtz.x.f.w v29, v10
+; LMULMAX1-NEXT:    vand.vi v29, v29, 1
+; LMULMAX1-NEXT:    vmsne.vi v0, v29, 0
+; LMULMAX1-NEXT:    vsetvli zero, zero, e8,mf8,ta,mu
+; LMULMAX1-NEXT:    vmerge.vim v29, v27, 1, v0
+; LMULMAX1-NEXT:    vsetivli zero, 2, e8,mf4,tu,mu
+; LMULMAX1-NEXT:    vslideup.vi v26, v29, 0
+; LMULMAX1-NEXT:    vsetivli zero, 4, e8,mf4,ta,mu
+; LMULMAX1-NEXT:    vmsne.vi v0, v26, 0
+; LMULMAX1-NEXT:    vmerge.vim v26, v25, 1, v0
+; LMULMAX1-NEXT:    vsetivli zero, 2, e32,mf2,ta,mu
+; LMULMAX1-NEXT:    vfncvt.rtz.x.f.w v29, v11
+; LMULMAX1-NEXT:    vand.vi v29, v29, 1
+; LMULMAX1-NEXT:    vmsne.vi v0, v29, 0
+; LMULMAX1-NEXT:    vsetvli zero, zero, e8,mf8,ta,mu
+; LMULMAX1-NEXT:    vmerge.vim v27, v27, 1, v0
+; LMULMAX1-NEXT:    vsetivli zero, 4, e8,mf4,tu,mu
+; LMULMAX1-NEXT:    vslideup.vi v26, v27, 2
+; LMULMAX1-NEXT:    vsetvli zero, zero, e8,mf4,ta,mu
+; LMULMAX1-NEXT:    vmsne.vi v0, v26, 0
+; LMULMAX1-NEXT:    vmerge.vim v25, v25, 1, v0
+; LMULMAX1-NEXT:    vsetivli zero, 8, e8,mf2,tu,mu
+; LMULMAX1-NEXT:    vslideup.vi v28, v25, 4
+; LMULMAX1-NEXT:    vsetvli zero, zero, e8,mf2,ta,mu
+; LMULMAX1-NEXT:    vmsne.vi v0, v28, 0
+; LMULMAX1-NEXT:    ret
   %z = fptosi <8 x double> %x to <8 x i1>
   ret <8 x i1> %z
 }
 
 define <8 x i1> @fp2ui_v8f64_v8i1(<8 x double> %x) {
-; RV32-LMULMAX8-LABEL: fp2ui_v8f64_v8i1:
-; RV32-LMULMAX8:       # %bb.0:
-; RV32-LMULMAX8-NEXT:    addi sp, sp, -16
-; RV32-LMULMAX8-NEXT:    .cfi_def_cfa_offset 16
-; RV32-LMULMAX8-NEXT:    vsetvli zero, zero, e64,m4,ta,mu
-; RV32-LMULMAX8-NEXT:    vfmv.f.s ft0, v8
-; RV32-LMULMAX8-NEXT:    fcvt.wu.d a0, ft0, rtz
-; RV32-LMULMAX8-NEXT:    sb a0, 8(sp)
-; RV32-LMULMAX8-NEXT:    vsetivli zero, 1, e64,m4,ta,mu
-; RV32-LMULMAX8-NEXT:    vslidedown.vi v28, v8, 7
-; RV32-LMULMAX8-NEXT:    vfmv.f.s ft0, v28
-; RV32-LMULMAX8-NEXT:    fcvt.wu.d a0, ft0, rtz
-; RV32-LMULMAX8-NEXT:    sb a0, 15(sp)
-; RV32-LMULMAX8-NEXT:    vslidedown.vi v28, v8, 6
-; RV32-LMULMAX8-NEXT:    vfmv.f.s ft0, v28
-; RV32-LMULMAX8-NEXT:    fcvt.wu.d a0, ft0, rtz
-; RV32-LMULMAX8-NEXT:    sb a0, 14(sp)
-; RV32-LMULMAX8-NEXT:    vslidedown.vi v28, v8, 5
-; RV32-LMULMAX8-NEXT:    vfmv.f.s ft0, v28
-; RV32-LMULMAX8-NEXT:    fcvt.wu.d a0, ft0, rtz
-; RV32-LMULMAX8-NEXT:    sb a0, 13(sp)
-; RV32-LMULMAX8-NEXT:    vslidedown.vi v28, v8, 4
-; RV32-LMULMAX8-NEXT:    vfmv.f.s ft0, v28
-; RV32-LMULMAX8-NEXT:    fcvt.wu.d a0, ft0, rtz
-; RV32-LMULMAX8-NEXT:    sb a0, 12(sp)
-; RV32-LMULMAX8-NEXT:    vslidedown.vi v28, v8, 3
-; RV32-LMULMAX8-NEXT:    vfmv.f.s ft0, v28
-; RV32-LMULMAX8-NEXT:    fcvt.wu.d a0, ft0, rtz
-; RV32-LMULMAX8-NEXT:    sb a0, 11(sp)
-; RV32-LMULMAX8-NEXT:    vslidedown.vi v28, v8, 2
-; RV32-LMULMAX8-NEXT:    vfmv.f.s ft0, v28
-; RV32-LMULMAX8-NEXT:    fcvt.wu.d a0, ft0, rtz
-; RV32-LMULMAX8-NEXT:    sb a0, 10(sp)
-; RV32-LMULMAX8-NEXT:    vslidedown.vi v28, v8, 1
-; RV32-LMULMAX8-NEXT:    vfmv.f.s ft0, v28
-; RV32-LMULMAX8-NEXT:    fcvt.wu.d a0, ft0, rtz
-; RV32-LMULMAX8-NEXT:    sb a0, 9(sp)
-; RV32-LMULMAX8-NEXT:    vsetivli zero, 8, e8,mf2,ta,mu
-; RV32-LMULMAX8-NEXT:    addi a0, sp, 8
-; RV32-LMULMAX8-NEXT:    vle8.v v25, (a0)
-; RV32-LMULMAX8-NEXT:    vand.vi v25, v25, 1
-; RV32-LMULMAX8-NEXT:    vmsne.vi v0, v25, 0
-; RV32-LMULMAX8-NEXT:    addi sp, sp, 16
-; RV32-LMULMAX8-NEXT:    ret
-;
-; RV64-LMULMAX8-LABEL: fp2ui_v8f64_v8i1:
-; RV64-LMULMAX8:       # %bb.0:
-; RV64-LMULMAX8-NEXT:    addi sp, sp, -16
-; RV64-LMULMAX8-NEXT:    .cfi_def_cfa_offset 16
-; RV64-LMULMAX8-NEXT:    vsetvli zero, zero, e64,m4,ta,mu
-; RV64-LMULMAX8-NEXT:    vfmv.f.s ft0, v8
-; RV64-LMULMAX8-NEXT:    fcvt.lu.d a0, ft0, rtz
-; RV64-LMULMAX8-NEXT:    sb a0, 8(sp)
-; RV64-LMULMAX8-NEXT:    vsetivli zero, 1, e64,m4,ta,mu
-; RV64-LMULMAX8-NEXT:    vslidedown.vi v28, v8, 7
-; RV64-LMULMAX8-NEXT:    vfmv.f.s ft0, v28
-; RV64-LMULMAX8-NEXT:    fcvt.lu.d a0, ft0, rtz
-; RV64-LMULMAX8-NEXT:    sb a0, 15(sp)
-; RV64-LMULMAX8-NEXT:    vslidedown.vi v28, v8, 6
-; RV64-LMULMAX8-NEXT:    vfmv.f.s ft0, v28
-; RV64-LMULMAX8-NEXT:    fcvt.lu.d a0, ft0, rtz
-; RV64-LMULMAX8-NEXT:    sb a0, 14(sp)
-; RV64-LMULMAX8-NEXT:    vslidedown.vi v28, v8, 5
-; RV64-LMULMAX8-NEXT:    vfmv.f.s ft0, v28
-; RV64-LMULMAX8-NEXT:    fcvt.lu.d a0, ft0, rtz
-; RV64-LMULMAX8-NEXT:    sb a0, 13(sp)
-; RV64-LMULMAX8-NEXT:    vslidedown.vi v28, v8, 4
-; RV64-LMULMAX8-NEXT:    vfmv.f.s ft0, v28
-; RV64-LMULMAX8-NEXT:    fcvt.lu.d a0, ft0, rtz
-; RV64-LMULMAX8-NEXT:    sb a0, 12(sp)
-; RV64-LMULMAX8-NEXT:    vslidedown.vi v28, v8, 3
-; RV64-LMULMAX8-NEXT:    vfmv.f.s ft0, v28
-; RV64-LMULMAX8-NEXT:    fcvt.lu.d a0, ft0, rtz
-; RV64-LMULMAX8-NEXT:    sb a0, 11(sp)
-; RV64-LMULMAX8-NEXT:    vslidedown.vi v28, v8, 2
-; RV64-LMULMAX8-NEXT:    vfmv.f.s ft0, v28
-; RV64-LMULMAX8-NEXT:    fcvt.lu.d a0, ft0, rtz
-; RV64-LMULMAX8-NEXT:    sb a0, 10(sp)
-; RV64-LMULMAX8-NEXT:    vslidedown.vi v28, v8, 1
-; RV64-LMULMAX8-NEXT:    vfmv.f.s ft0, v28
-; RV64-LMULMAX8-NEXT:    fcvt.lu.d a0, ft0, rtz
-; RV64-LMULMAX8-NEXT:    sb a0, 9(sp)
-; RV64-LMULMAX8-NEXT:    vsetivli zero, 8, e8,mf2,ta,mu
-; RV64-LMULMAX8-NEXT:    addi a0, sp, 8
-; RV64-LMULMAX8-NEXT:    vle8.v v25, (a0)
-; RV64-LMULMAX8-NEXT:    vand.vi v25, v25, 1
-; RV64-LMULMAX8-NEXT:    vmsne.vi v0, v25, 0
-; RV64-LMULMAX8-NEXT:    addi sp, sp, 16
-; RV64-LMULMAX8-NEXT:    ret
-;
-; RV32-LMULMAX1-LABEL: fp2ui_v8f64_v8i1:
-; RV32-LMULMAX1:       # %bb.0:
-; RV32-LMULMAX1-NEXT:    addi sp, sp, -16
-; RV32-LMULMAX1-NEXT:    .cfi_def_cfa_offset 16
-; RV32-LMULMAX1-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
-; RV32-LMULMAX1-NEXT:    vfmv.f.s ft0, v11
-; RV32-LMULMAX1-NEXT:    fcvt.wu.d a0, ft0, rtz
-; RV32-LMULMAX1-NEXT:    sb a0, 14(sp)
-; RV32-LMULMAX1-NEXT:    vfmv.f.s ft0, v10
-; RV32-LMULMAX1-NEXT:    fcvt.wu.d a0, ft0, rtz
-; RV32-LMULMAX1-NEXT:    sb a0, 12(sp)
-; RV32-LMULMAX1-NEXT:    vfmv.f.s ft0, v9
-; RV32-LMULMAX1-NEXT:    fcvt.wu.d a0, ft0, rtz
-; RV32-LMULMAX1-NEXT:    sb a0, 10(sp)
-; RV32-LMULMAX1-NEXT:    vfmv.f.s ft0, v8
-; RV32-LMULMAX1-NEXT:    fcvt.wu.d a0, ft0, rtz
-; RV32-LMULMAX1-NEXT:    sb a0, 8(sp)
-; RV32-LMULMAX1-NEXT:    vsetivli zero, 1, e64,m1,ta,mu
-; RV32-LMULMAX1-NEXT:    vslidedown.vi v25, v11, 1
-; RV32-LMULMAX1-NEXT:    vfmv.f.s ft0, v25
-; RV32-LMULMAX1-NEXT:    fcvt.wu.d a0, ft0, rtz
-; RV32-LMULMAX1-NEXT:    sb a0, 15(sp)
-; RV32-LMULMAX1-NEXT:    vslidedown.vi v25, v10, 1
-; RV32-LMULMAX1-NEXT:    vfmv.f.s ft0, v25
-; RV32-LMULMAX1-NEXT:    fcvt.wu.d a0, ft0, rtz
-; RV32-LMULMAX1-NEXT:    sb a0, 13(sp)
-; RV32-LMULMAX1-NEXT:    vslidedown.vi v25, v9, 1
-; RV32-LMULMAX1-NEXT:    vfmv.f.s ft0, v25
-; RV32-LMULMAX1-NEXT:    fcvt.wu.d a0, ft0, rtz
-; RV32-LMULMAX1-NEXT:    sb a0, 11(sp)
-; RV32-LMULMAX1-NEXT:    vslidedown.vi v25, v8, 1
-; RV32-LMULMAX1-NEXT:    vfmv.f.s ft0, v25
-; RV32-LMULMAX1-NEXT:    fcvt.wu.d a0, ft0, rtz
-; RV32-LMULMAX1-NEXT:    sb a0, 9(sp)
-; RV32-LMULMAX1-NEXT:    vsetivli zero, 8, e8,mf2,ta,mu
-; RV32-LMULMAX1-NEXT:    addi a0, sp, 8
-; RV32-LMULMAX1-NEXT:    vle8.v v25, (a0)
-; RV32-LMULMAX1-NEXT:    vand.vi v25, v25, 1
-; RV32-LMULMAX1-NEXT:    vmsne.vi v0, v25, 0
-; RV32-LMULMAX1-NEXT:    addi sp, sp, 16
-; RV32-LMULMAX1-NEXT:    ret
+; LMULMAX8-LABEL: fp2ui_v8f64_v8i1:
+; LMULMAX8:       # %bb.0:
+; LMULMAX8-NEXT:    vsetivli zero, 8, e32,m2,ta,mu
+; LMULMAX8-NEXT:    vfncvt.rtz.xu.f.w v26, v8
+; LMULMAX8-NEXT:    vand.vi v26, v26, 1
+; LMULMAX8-NEXT:    vmsne.vi v0, v26, 0
+; LMULMAX8-NEXT:    ret
 ;
-; RV64-LMULMAX1-LABEL: fp2ui_v8f64_v8i1:
-; RV64-LMULMAX1:       # %bb.0:
-; RV64-LMULMAX1-NEXT:    addi sp, sp, -16
-; RV64-LMULMAX1-NEXT:    .cfi_def_cfa_offset 16
-; RV64-LMULMAX1-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
-; RV64-LMULMAX1-NEXT:    vfmv.f.s ft0, v11
-; RV64-LMULMAX1-NEXT:    fcvt.lu.d a0, ft0, rtz
-; RV64-LMULMAX1-NEXT:    sb a0, 14(sp)
-; RV64-LMULMAX1-NEXT:    vfmv.f.s ft0, v10
-; RV64-LMULMAX1-NEXT:    fcvt.lu.d a0, ft0, rtz
-; RV64-LMULMAX1-NEXT:    sb a0, 12(sp)
-; RV64-LMULMAX1-NEXT:    vfmv.f.s ft0, v9
-; RV64-LMULMAX1-NEXT:    fcvt.lu.d a0, ft0, rtz
-; RV64-LMULMAX1-NEXT:    sb a0, 10(sp)
-; RV64-LMULMAX1-NEXT:    vfmv.f.s ft0, v8
-; RV64-LMULMAX1-NEXT:    fcvt.lu.d a0, ft0, rtz
-; RV64-LMULMAX1-NEXT:    sb a0, 8(sp)
-; RV64-LMULMAX1-NEXT:    vsetivli zero, 1, e64,m1,ta,mu
-; RV64-LMULMAX1-NEXT:    vslidedown.vi v25, v11, 1
-; RV64-LMULMAX1-NEXT:    vfmv.f.s ft0, v25
-; RV64-LMULMAX1-NEXT:    fcvt.lu.d a0, ft0, rtz
-; RV64-LMULMAX1-NEXT:    sb a0, 15(sp)
-; RV64-LMULMAX1-NEXT:    vslidedown.vi v25, v10, 1
-; RV64-LMULMAX1-NEXT:    vfmv.f.s ft0, v25
-; RV64-LMULMAX1-NEXT:    fcvt.lu.d a0, ft0, rtz
-; RV64-LMULMAX1-NEXT:    sb a0, 13(sp)
-; RV64-LMULMAX1-NEXT:    vslidedown.vi v25, v9, 1
-; RV64-LMULMAX1-NEXT:    vfmv.f.s ft0, v25
-; RV64-LMULMAX1-NEXT:    fcvt.lu.d a0, ft0, rtz
-; RV64-LMULMAX1-NEXT:    sb a0, 11(sp)
-; RV64-LMULMAX1-NEXT:    vslidedown.vi v25, v8, 1
-; RV64-LMULMAX1-NEXT:    vfmv.f.s ft0, v25
-; RV64-LMULMAX1-NEXT:    fcvt.lu.d a0, ft0, rtz
-; RV64-LMULMAX1-NEXT:    sb a0, 9(sp)
-; RV64-LMULMAX1-NEXT:    vsetivli zero, 8, e8,mf2,ta,mu
-; RV64-LMULMAX1-NEXT:    addi a0, sp, 8
-; RV64-LMULMAX1-NEXT:    vle8.v v25, (a0)
-; RV64-LMULMAX1-NEXT:    vand.vi v25, v25, 1
-; RV64-LMULMAX1-NEXT:    vmsne.vi v0, v25, 0
-; RV64-LMULMAX1-NEXT:    addi sp, sp, 16
-; RV64-LMULMAX1-NEXT:    ret
+; LMULMAX1-LABEL: fp2ui_v8f64_v8i1:
+; LMULMAX1:       # %bb.0:
+; LMULMAX1-NEXT:    vsetivli zero, 4, e8,mf4,ta,mu
+; LMULMAX1-NEXT:    vmv.v.i v25, 0
+; LMULMAX1-NEXT:    vmclr.m v0
+; LMULMAX1-NEXT:    vmerge.vim v26, v25, 1, v0
+; LMULMAX1-NEXT:    vsetivli zero, 2, e32,mf2,ta,mu
+; LMULMAX1-NEXT:    vfncvt.rtz.xu.f.w v27, v8
+; LMULMAX1-NEXT:    vand.vi v27, v27, 1
+; LMULMAX1-NEXT:    vmsne.vi v0, v27, 0
+; LMULMAX1-NEXT:    vsetvli zero, zero, e8,mf8,ta,mu
+; LMULMAX1-NEXT:    vmv.v.i v27, 0
+; LMULMAX1-NEXT:    vmerge.vim v28, v27, 1, v0
+; LMULMAX1-NEXT:    vsetivli zero, 2, e8,mf4,tu,mu
+; LMULMAX1-NEXT:    vmv1r.v v29, v26
+; LMULMAX1-NEXT:    vslideup.vi v29, v28, 0
+; LMULMAX1-NEXT:    vsetivli zero, 4, e8,mf4,ta,mu
+; LMULMAX1-NEXT:    vmsne.vi v0, v29, 0
+; LMULMAX1-NEXT:    vmerge.vim v28, v25, 1, v0
+; LMULMAX1-NEXT:    vsetivli zero, 2, e32,mf2,ta,mu
+; LMULMAX1-NEXT:    vfncvt.rtz.xu.f.w v29, v9
+; LMULMAX1-NEXT:    vand.vi v29, v29, 1
+; LMULMAX1-NEXT:    vmsne.vi v0, v29, 0
+; LMULMAX1-NEXT:    vsetvli zero, zero, e8,mf8,ta,mu
+; LMULMAX1-NEXT:    vmerge.vim v29, v27, 1, v0
+; LMULMAX1-NEXT:    vsetivli zero, 4, e8,mf4,tu,mu
+; LMULMAX1-NEXT:    vslideup.vi v28, v29, 2
+; LMULMAX1-NEXT:    vsetvli zero, zero, e8,mf4,ta,mu
+; LMULMAX1-NEXT:    vmsne.vi v0, v28, 0
+; LMULMAX1-NEXT:    vmerge.vim v28, v25, 1, v0
+; LMULMAX1-NEXT:    vsetivli zero, 8, e8,mf2,ta,mu
+; LMULMAX1-NEXT:    vmv.v.i v29, 0
+; LMULMAX1-NEXT:    vmclr.m v0
+; LMULMAX1-NEXT:    vmerge.vim v30, v29, 1, v0
+; LMULMAX1-NEXT:    vsetivli zero, 4, e8,mf2,tu,mu
+; LMULMAX1-NEXT:    vslideup.vi v30, v28, 0
+; LMULMAX1-NEXT:    vsetivli zero, 8, e8,mf2,ta,mu
+; LMULMAX1-NEXT:    vmsne.vi v0, v30, 0
+; LMULMAX1-NEXT:    vmerge.vim v28, v29, 1, v0
+; LMULMAX1-NEXT:    vsetivli zero, 2, e32,mf2,ta,mu
+; LMULMAX1-NEXT:    vfncvt.rtz.xu.f.w v29, v10
+; LMULMAX1-NEXT:    vand.vi v29, v29, 1
+; LMULMAX1-NEXT:    vmsne.vi v0, v29, 0
+; LMULMAX1-NEXT:    vsetvli zero, zero, e8,mf8,ta,mu
+; LMULMAX1-NEXT:    vmerge.vim v29, v27, 1, v0
+; LMULMAX1-NEXT:    vsetivli zero, 2, e8,mf4,tu,mu
+; LMULMAX1-NEXT:    vslideup.vi v26, v29, 0
+; LMULMAX1-NEXT:    vsetivli zero, 4, e8,mf4,ta,mu
+; LMULMAX1-NEXT:    vmsne.vi v0, v26, 0
+; LMULMAX1-NEXT:    vmerge.vim v26, v25, 1, v0
+; LMULMAX1-NEXT:    vsetivli zero, 2, e32,mf2,ta,mu
+; LMULMAX1-NEXT:    vfncvt.rtz.xu.f.w v29, v11
+; LMULMAX1-NEXT:    vand.vi v29, v29, 1
+; LMULMAX1-NEXT:    vmsne.vi v0, v29, 0
+; LMULMAX1-NEXT:    vsetvli zero, zero, e8,mf8,ta,mu
+; LMULMAX1-NEXT:    vmerge.vim v27, v27, 1, v0
+; LMULMAX1-NEXT:    vsetivli zero, 4, e8,mf4,tu,mu
+; LMULMAX1-NEXT:    vslideup.vi v26, v27, 2
+; LMULMAX1-NEXT:    vsetvli zero, zero, e8,mf4,ta,mu
+; LMULMAX1-NEXT:    vmsne.vi v0, v26, 0
+; LMULMAX1-NEXT:    vmerge.vim v25, v25, 1, v0
+; LMULMAX1-NEXT:    vsetivli zero, 8, e8,mf2,tu,mu
+; LMULMAX1-NEXT:    vslideup.vi v28, v25, 4
+; LMULMAX1-NEXT:    vsetvli zero, zero, e8,mf2,ta,mu
+; LMULMAX1-NEXT:    vmsne.vi v0, v28, 0
+; LMULMAX1-NEXT:    ret
   %z = fptoui <8 x double> %x to <8 x i1>
   ret <8 x i1> %z
 }
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-i2fp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-i2fp.ll
index eabdb3d..af6e727 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-i2fp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-i2fp.ll
@@ -1,8 +1,8 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+experimental-v,+experimental-zfh,+f,+d -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=8 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX8,RV32,RV32-LMULMAX8
-; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+experimental-v,+experimental-zfh,+f,+d -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=8 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX8,RV64,RV64-LMULMAX8
-; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+experimental-v,+experimental-zfh,+f,+d -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1,RV32,RV32-LMULMAX1
-; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+experimental-v,+experimental-zfh,+f,+d -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1,RV64,RV64-LMULMAX1
+; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+experimental-v,+experimental-zfh,+f,+d -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=8 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX8
+; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+experimental-v,+experimental-zfh,+f,+d -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=8 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX8
+; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+experimental-v,+experimental-zfh,+f,+d -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1
+; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+experimental-v,+experimental-zfh,+f,+d -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1
 
 define void @si2fp_v2i32_v2f32(<2 x i32>* %x, <2 x float>* %y) {
 ; CHECK-LABEL: si2fp_v2i32_v2f32:
@@ -33,85 +33,25 @@ define void @ui2fp_v2i32_v2f32(<2 x i32>* %x, <2 x float>* %y) {
 }
 
 define <2 x float> @si2fp_v2i1_v2f32(<2 x i1> %x) {
-; RV32-LABEL: si2fp_v2i1_v2f32:
-; RV32:       # %bb.0:
-; RV32-NEXT:    vsetivli zero, 2, e8,mf8,ta,mu
-; RV32-NEXT:    vmv.v.i v25, 0
-; RV32-NEXT:    vmerge.vim v25, v25, 1, v0
-; RV32-NEXT:    vmv.x.s a0, v25
-; RV32-NEXT:    andi a0, a0, 1
-; RV32-NEXT:    neg a0, a0
-; RV32-NEXT:    fcvt.s.w ft0, a0
-; RV32-NEXT:    vsetivli zero, 1, e8,mf8,ta,mu
-; RV32-NEXT:    vslidedown.vi v25, v25, 1
-; RV32-NEXT:    vmv.x.s a0, v25
-; RV32-NEXT:    andi a0, a0, 1
-; RV32-NEXT:    neg a0, a0
-; RV32-NEXT:    fcvt.s.w ft1, a0
-; RV32-NEXT:    vsetivli zero, 2, e32,mf2,ta,mu
-; RV32-NEXT:    vfmv.v.f v8, ft1
-; RV32-NEXT:    vfmv.s.f v8, ft0
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: si2fp_v2i1_v2f32:
-; RV64:       # %bb.0:
-; RV64-NEXT:    vsetivli zero, 2, e8,mf8,ta,mu
-; RV64-NEXT:    vmv.v.i v25, 0
-; RV64-NEXT:    vmerge.vim v25, v25, 1, v0
-; RV64-NEXT:    vmv.x.s a0, v25
-; RV64-NEXT:    andi a0, a0, 1
-; RV64-NEXT:    neg a0, a0
-; RV64-NEXT:    fcvt.s.l ft0, a0
-; RV64-NEXT:    vsetivli zero, 1, e8,mf8,ta,mu
-; RV64-NEXT:    vslidedown.vi v25, v25, 1
-; RV64-NEXT:    vmv.x.s a0, v25
-; RV64-NEXT:    andi a0, a0, 1
-; RV64-NEXT:    neg a0, a0
-; RV64-NEXT:    fcvt.s.l ft1, a0
-; RV64-NEXT:    vsetivli zero, 2, e32,mf2,ta,mu
-; RV64-NEXT:    vfmv.v.f v8, ft1
-; RV64-NEXT:    vfmv.s.f v8, ft0
-; RV64-NEXT:    ret
+; CHECK-LABEL: si2fp_v2i1_v2f32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 2, e32,mf2,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, 0
+; CHECK-NEXT:    vmerge.vim v25, v25, -1, v0
+; CHECK-NEXT:    vfcvt.f.x.v v8, v25
+; CHECK-NEXT:    ret
   %z = sitofp <2 x i1> %x to <2 x float>
   ret <2 x float> %z
 }
 
 define <2 x float> @ui2fp_v2i1_v2f32(<2 x i1> %x) {
-; RV32-LABEL: ui2fp_v2i1_v2f32:
-; RV32:       # %bb.0:
-; RV32-NEXT:    vsetivli zero, 2, e8,mf8,ta,mu
-; RV32-NEXT:    vmv.v.i v25, 0
-; RV32-NEXT:    vmerge.vim v25, v25, 1, v0
-; RV32-NEXT:    vmv.x.s a0, v25
-; RV32-NEXT:    andi a0, a0, 1
-; RV32-NEXT:    fcvt.s.wu ft0, a0
-; RV32-NEXT:    vsetivli zero, 1, e8,mf8,ta,mu
-; RV32-NEXT:    vslidedown.vi v25, v25, 1
-; RV32-NEXT:    vmv.x.s a0, v25
-; RV32-NEXT:    andi a0, a0, 1
-; RV32-NEXT:    fcvt.s.wu ft1, a0
-; RV32-NEXT:    vsetivli zero, 2, e32,mf2,ta,mu
-; RV32-NEXT:    vfmv.v.f v8, ft1
-; RV32-NEXT:    vfmv.s.f v8, ft0
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: ui2fp_v2i1_v2f32:
-; RV64:       # %bb.0:
-; RV64-NEXT:    vsetivli zero, 2, e8,mf8,ta,mu
-; RV64-NEXT:    vmv.v.i v25, 0
-; RV64-NEXT:    vmerge.vim v25, v25, 1, v0
-; RV64-NEXT:    vmv.x.s a0, v25
-; RV64-NEXT:    andi a0, a0, 1
-; RV64-NEXT:    fcvt.s.lu ft0, a0
-; RV64-NEXT:    vsetivli zero, 1, e8,mf8,ta,mu
-; RV64-NEXT:    vslidedown.vi v25, v25, 1
-; RV64-NEXT:    vmv.x.s a0, v25
-; RV64-NEXT:    andi a0, a0, 1
-; RV64-NEXT:    fcvt.s.lu ft1, a0
-; RV64-NEXT:    vsetivli zero, 2, e32,mf2,ta,mu
-; RV64-NEXT:    vfmv.v.f v8, ft1
-; RV64-NEXT:    vfmv.s.f v8, ft0
-; RV64-NEXT:    ret
+; CHECK-LABEL: ui2fp_v2i1_v2f32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 2, e32,mf2,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, 0
+; CHECK-NEXT:    vmerge.vim v25, v25, 1, v0
+; CHECK-NEXT:    vfcvt.f.xu.v v8, v25
+; CHECK-NEXT:    ret
   %z = uitofp <2 x i1> %x to <2 x float>
   ret <2 x float> %z
 }
@@ -171,537 +111,61 @@ define void @ui2fp_v8i32_v8f32(<8 x i32>* %x, <8 x float>* %y) {
 }
 
 define <8 x float> @si2fp_v8i1_v8f32(<8 x i1> %x) {
-; RV32-LMULMAX8-LABEL: si2fp_v8i1_v8f32:
-; RV32-LMULMAX8:       # %bb.0:
-; RV32-LMULMAX8-NEXT:    addi sp, sp, -64
-; RV32-LMULMAX8-NEXT:    .cfi_def_cfa_offset 64
-; RV32-LMULMAX8-NEXT:    sw ra, 60(sp) # 4-byte Folded Spill
-; RV32-LMULMAX8-NEXT:    sw s0, 56(sp) # 4-byte Folded Spill
-; RV32-LMULMAX8-NEXT:    .cfi_offset ra, -4
-; RV32-LMULMAX8-NEXT:    .cfi_offset s0, -8
-; RV32-LMULMAX8-NEXT:    addi s0, sp, 64
-; RV32-LMULMAX8-NEXT:    .cfi_def_cfa s0, 0
-; RV32-LMULMAX8-NEXT:    andi sp, sp, -32
-; RV32-LMULMAX8-NEXT:    vsetivli zero, 8, e8,mf2,ta,mu
-; RV32-LMULMAX8-NEXT:    vmv.v.i v25, 0
-; RV32-LMULMAX8-NEXT:    vmerge.vim v25, v25, 1, v0
-; RV32-LMULMAX8-NEXT:    vmv.x.s a0, v25
-; RV32-LMULMAX8-NEXT:    andi a0, a0, 1
-; RV32-LMULMAX8-NEXT:    neg a0, a0
-; RV32-LMULMAX8-NEXT:    fcvt.s.w ft0, a0
-; RV32-LMULMAX8-NEXT:    fsw ft0, 0(sp)
-; RV32-LMULMAX8-NEXT:    vsetivli zero, 1, e8,mf2,ta,mu
-; RV32-LMULMAX8-NEXT:    vslidedown.vi v26, v25, 7
-; RV32-LMULMAX8-NEXT:    vmv.x.s a0, v26
-; RV32-LMULMAX8-NEXT:    andi a0, a0, 1
-; RV32-LMULMAX8-NEXT:    neg a0, a0
-; RV32-LMULMAX8-NEXT:    fcvt.s.w ft0, a0
-; RV32-LMULMAX8-NEXT:    fsw ft0, 28(sp)
-; RV32-LMULMAX8-NEXT:    vslidedown.vi v26, v25, 6
-; RV32-LMULMAX8-NEXT:    vmv.x.s a0, v26
-; RV32-LMULMAX8-NEXT:    andi a0, a0, 1
-; RV32-LMULMAX8-NEXT:    neg a0, a0
-; RV32-LMULMAX8-NEXT:    fcvt.s.w ft0, a0
-; RV32-LMULMAX8-NEXT:    fsw ft0, 24(sp)
-; RV32-LMULMAX8-NEXT:    vslidedown.vi v26, v25, 5
-; RV32-LMULMAX8-NEXT:    vmv.x.s a0, v26
-; RV32-LMULMAX8-NEXT:    andi a0, a0, 1
-; RV32-LMULMAX8-NEXT:    neg a0, a0
-; RV32-LMULMAX8-NEXT:    fcvt.s.w ft0, a0
-; RV32-LMULMAX8-NEXT:    fsw ft0, 20(sp)
-; RV32-LMULMAX8-NEXT:    vslidedown.vi v26, v25, 4
-; RV32-LMULMAX8-NEXT:    vmv.x.s a0, v26
-; RV32-LMULMAX8-NEXT:    andi a0, a0, 1
-; RV32-LMULMAX8-NEXT:    neg a0, a0
-; RV32-LMULMAX8-NEXT:    fcvt.s.w ft0, a0
-; RV32-LMULMAX8-NEXT:    fsw ft0, 16(sp)
-; RV32-LMULMAX8-NEXT:    vslidedown.vi v26, v25, 3
-; RV32-LMULMAX8-NEXT:    vmv.x.s a0, v26
-; RV32-LMULMAX8-NEXT:    andi a0, a0, 1
-; RV32-LMULMAX8-NEXT:    neg a0, a0
-; RV32-LMULMAX8-NEXT:    fcvt.s.w ft0, a0
-; RV32-LMULMAX8-NEXT:    fsw ft0, 12(sp)
-; RV32-LMULMAX8-NEXT:    vslidedown.vi v26, v25, 2
-; RV32-LMULMAX8-NEXT:    vmv.x.s a0, v26
-; RV32-LMULMAX8-NEXT:    andi a0, a0, 1
-; RV32-LMULMAX8-NEXT:    neg a0, a0
-; RV32-LMULMAX8-NEXT:    fcvt.s.w ft0, a0
-; RV32-LMULMAX8-NEXT:    fsw ft0, 8(sp)
-; RV32-LMULMAX8-NEXT:    vslidedown.vi v25, v25, 1
-; RV32-LMULMAX8-NEXT:    vmv.x.s a0, v25
-; RV32-LMULMAX8-NEXT:    andi a0, a0, 1
-; RV32-LMULMAX8-NEXT:    neg a0, a0
-; RV32-LMULMAX8-NEXT:    fcvt.s.w ft0, a0
-; RV32-LMULMAX8-NEXT:    fsw ft0, 4(sp)
-; RV32-LMULMAX8-NEXT:    vsetivli zero, 8, e32,m2,ta,mu
-; RV32-LMULMAX8-NEXT:    vle32.v v8, (sp)
-; RV32-LMULMAX8-NEXT:    addi sp, s0, -64
-; RV32-LMULMAX8-NEXT:    lw s0, 56(sp) # 4-byte Folded Reload
-; RV32-LMULMAX8-NEXT:    lw ra, 60(sp) # 4-byte Folded Reload
-; RV32-LMULMAX8-NEXT:    addi sp, sp, 64
-; RV32-LMULMAX8-NEXT:    ret
-;
-; RV64-LMULMAX8-LABEL: si2fp_v8i1_v8f32:
-; RV64-LMULMAX8:       # %bb.0:
-; RV64-LMULMAX8-NEXT:    addi sp, sp, -64
-; RV64-LMULMAX8-NEXT:    .cfi_def_cfa_offset 64
-; RV64-LMULMAX8-NEXT:    sd ra, 56(sp) # 8-byte Folded Spill
-; RV64-LMULMAX8-NEXT:    sd s0, 48(sp) # 8-byte Folded Spill
-; RV64-LMULMAX8-NEXT:    .cfi_offset ra, -8
-; RV64-LMULMAX8-NEXT:    .cfi_offset s0, -16
-; RV64-LMULMAX8-NEXT:    addi s0, sp, 64
-; RV64-LMULMAX8-NEXT:    .cfi_def_cfa s0, 0
-; RV64-LMULMAX8-NEXT:    andi sp, sp, -32
-; RV64-LMULMAX8-NEXT:    vsetivli zero, 8, e8,mf2,ta,mu
-; RV64-LMULMAX8-NEXT:    vmv.v.i v25, 0
-; RV64-LMULMAX8-NEXT:    vmerge.vim v25, v25, 1, v0
-; RV64-LMULMAX8-NEXT:    vmv.x.s a0, v25
-; RV64-LMULMAX8-NEXT:    andi a0, a0, 1
-; RV64-LMULMAX8-NEXT:    neg a0, a0
-; RV64-LMULMAX8-NEXT:    fcvt.s.l ft0, a0
-; RV64-LMULMAX8-NEXT:    fsw ft0, 0(sp)
-; RV64-LMULMAX8-NEXT:    vsetivli zero, 1, e8,mf2,ta,mu
-; RV64-LMULMAX8-NEXT:    vslidedown.vi v26, v25, 7
-; RV64-LMULMAX8-NEXT:    vmv.x.s a0, v26
-; RV64-LMULMAX8-NEXT:    andi a0, a0, 1
-; RV64-LMULMAX8-NEXT:    neg a0, a0
-; RV64-LMULMAX8-NEXT:    fcvt.s.l ft0, a0
-; RV64-LMULMAX8-NEXT:    fsw ft0, 28(sp)
-; RV64-LMULMAX8-NEXT:    vslidedown.vi v26, v25, 6
-; RV64-LMULMAX8-NEXT:    vmv.x.s a0, v26
-; RV64-LMULMAX8-NEXT:    andi a0, a0, 1
-; RV64-LMULMAX8-NEXT:    neg a0, a0
-; RV64-LMULMAX8-NEXT:    fcvt.s.l ft0, a0
-; RV64-LMULMAX8-NEXT:    fsw ft0, 24(sp)
-; RV64-LMULMAX8-NEXT:    vslidedown.vi v26, v25, 5
-; RV64-LMULMAX8-NEXT:    vmv.x.s a0, v26
-; RV64-LMULMAX8-NEXT:    andi a0, a0, 1
-; RV64-LMULMAX8-NEXT:    neg a0, a0
-; RV64-LMULMAX8-NEXT:    fcvt.s.l ft0, a0
-; RV64-LMULMAX8-NEXT:    fsw ft0, 20(sp)
-; RV64-LMULMAX8-NEXT:    vslidedown.vi v26, v25, 4
-; RV64-LMULMAX8-NEXT:    vmv.x.s a0, v26
-; RV64-LMULMAX8-NEXT:    andi a0, a0, 1
-; RV64-LMULMAX8-NEXT:    neg a0, a0
-; RV64-LMULMAX8-NEXT:    fcvt.s.l ft0, a0
-; RV64-LMULMAX8-NEXT:    fsw ft0, 16(sp)
-; RV64-LMULMAX8-NEXT:    vslidedown.vi v26, v25, 3
-; RV64-LMULMAX8-NEXT:    vmv.x.s a0, v26
-; RV64-LMULMAX8-NEXT:    andi a0, a0, 1
-; RV64-LMULMAX8-NEXT:    neg a0, a0
-; RV64-LMULMAX8-NEXT:    fcvt.s.l ft0, a0
-; RV64-LMULMAX8-NEXT:    fsw ft0, 12(sp)
-; RV64-LMULMAX8-NEXT:    vslidedown.vi v26, v25, 2
-; RV64-LMULMAX8-NEXT:    vmv.x.s a0, v26
-; RV64-LMULMAX8-NEXT:    andi a0, a0, 1
-; RV64-LMULMAX8-NEXT:    neg a0, a0
-; RV64-LMULMAX8-NEXT:    fcvt.s.l ft0, a0
-; RV64-LMULMAX8-NEXT:    fsw ft0, 8(sp)
-; RV64-LMULMAX8-NEXT:    vslidedown.vi v25, v25, 1
-; RV64-LMULMAX8-NEXT:    vmv.x.s a0, v25
-; RV64-LMULMAX8-NEXT:    andi a0, a0, 1
-; RV64-LMULMAX8-NEXT:    neg a0, a0
-; RV64-LMULMAX8-NEXT:    fcvt.s.l ft0, a0
-; RV64-LMULMAX8-NEXT:    fsw ft0, 4(sp)
-; RV64-LMULMAX8-NEXT:    vsetivli zero, 8, e32,m2,ta,mu
-; RV64-LMULMAX8-NEXT:    vle32.v v8, (sp)
-; RV64-LMULMAX8-NEXT:    addi sp, s0, -64
-; RV64-LMULMAX8-NEXT:    ld s0, 48(sp) # 8-byte Folded Reload
-; RV64-LMULMAX8-NEXT:    ld ra, 56(sp) # 8-byte Folded Reload
-; RV64-LMULMAX8-NEXT:    addi sp, sp, 64
-; RV64-LMULMAX8-NEXT:    ret
-;
-; RV32-LMULMAX1-LABEL: si2fp_v8i1_v8f32:
-; RV32-LMULMAX1:       # %bb.0:
-; RV32-LMULMAX1-NEXT:    addi sp, sp, -32
-; RV32-LMULMAX1-NEXT:    .cfi_def_cfa_offset 32
-; RV32-LMULMAX1-NEXT:    vsetivli zero, 4, e8,mf4,ta,mu
-; RV32-LMULMAX1-NEXT:    vmv.v.i v25, 0
-; RV32-LMULMAX1-NEXT:    vmerge.vim v26, v25, 1, v0
-; RV32-LMULMAX1-NEXT:    vmv.x.s a0, v26
-; RV32-LMULMAX1-NEXT:    andi a0, a0, 1
-; RV32-LMULMAX1-NEXT:    neg a0, a0
-; RV32-LMULMAX1-NEXT:    fcvt.s.w ft0, a0
-; RV32-LMULMAX1-NEXT:    fsw ft0, 16(sp)
-; RV32-LMULMAX1-NEXT:    vsetivli zero, 1, e8,mf4,ta,mu
-; RV32-LMULMAX1-NEXT:    vslidedown.vi v27, v26, 3
-; RV32-LMULMAX1-NEXT:    vmv.x.s a0, v27
-; RV32-LMULMAX1-NEXT:    andi a0, a0, 1
-; RV32-LMULMAX1-NEXT:    neg a0, a0
-; RV32-LMULMAX1-NEXT:    fcvt.s.w ft0, a0
-; RV32-LMULMAX1-NEXT:    fsw ft0, 28(sp)
-; RV32-LMULMAX1-NEXT:    vslidedown.vi v27, v26, 2
-; RV32-LMULMAX1-NEXT:    vmv.x.s a0, v27
-; RV32-LMULMAX1-NEXT:    andi a0, a0, 1
-; RV32-LMULMAX1-NEXT:    neg a0, a0
-; RV32-LMULMAX1-NEXT:    fcvt.s.w ft0, a0
-; RV32-LMULMAX1-NEXT:    fsw ft0, 24(sp)
-; RV32-LMULMAX1-NEXT:    vslidedown.vi v26, v26, 1
-; RV32-LMULMAX1-NEXT:    vmv.x.s a0, v26
-; RV32-LMULMAX1-NEXT:    andi a0, a0, 1
-; RV32-LMULMAX1-NEXT:    neg a0, a0
-; RV32-LMULMAX1-NEXT:    fcvt.s.w ft0, a0
-; RV32-LMULMAX1-NEXT:    fsw ft0, 20(sp)
-; RV32-LMULMAX1-NEXT:    vsetivli zero, 8, e8,mf2,ta,mu
-; RV32-LMULMAX1-NEXT:    vmv.v.i v26, 0
-; RV32-LMULMAX1-NEXT:    vmerge.vim v26, v26, 1, v0
-; RV32-LMULMAX1-NEXT:    vsetivli zero, 4, e8,mf2,ta,mu
-; RV32-LMULMAX1-NEXT:    vslidedown.vi v26, v26, 4
-; RV32-LMULMAX1-NEXT:    vsetivli zero, 4, e8,mf4,ta,mu
-; RV32-LMULMAX1-NEXT:    vmsne.vi v0, v26, 0
-; RV32-LMULMAX1-NEXT:    vmerge.vim v25, v25, 1, v0
-; RV32-LMULMAX1-NEXT:    vmv.x.s a0, v25
-; RV32-LMULMAX1-NEXT:    andi a0, a0, 1
-; RV32-LMULMAX1-NEXT:    neg a0, a0
-; RV32-LMULMAX1-NEXT:    fcvt.s.w ft0, a0
-; RV32-LMULMAX1-NEXT:    fsw ft0, 0(sp)
-; RV32-LMULMAX1-NEXT:    vsetivli zero, 1, e8,mf4,ta,mu
-; RV32-LMULMAX1-NEXT:    vslidedown.vi v26, v25, 3
-; RV32-LMULMAX1-NEXT:    vmv.x.s a0, v26
-; RV32-LMULMAX1-NEXT:    andi a0, a0, 1
-; RV32-LMULMAX1-NEXT:    neg a0, a0
-; RV32-LMULMAX1-NEXT:    fcvt.s.w ft0, a0
-; RV32-LMULMAX1-NEXT:    fsw ft0, 12(sp)
-; RV32-LMULMAX1-NEXT:    vslidedown.vi v26, v25, 2
-; RV32-LMULMAX1-NEXT:    vmv.x.s a0, v26
-; RV32-LMULMAX1-NEXT:    andi a0, a0, 1
-; RV32-LMULMAX1-NEXT:    neg a0, a0
-; RV32-LMULMAX1-NEXT:    fcvt.s.w ft0, a0
-; RV32-LMULMAX1-NEXT:    fsw ft0, 8(sp)
-; RV32-LMULMAX1-NEXT:    vslidedown.vi v25, v25, 1
-; RV32-LMULMAX1-NEXT:    vmv.x.s a0, v25
-; RV32-LMULMAX1-NEXT:    andi a0, a0, 1
-; RV32-LMULMAX1-NEXT:    neg a0, a0
-; RV32-LMULMAX1-NEXT:    fcvt.s.w ft0, a0
-; RV32-LMULMAX1-NEXT:    fsw ft0, 4(sp)
-; RV32-LMULMAX1-NEXT:    vsetivli zero, 4, e32,m1,ta,mu
-; RV32-LMULMAX1-NEXT:    addi a0, sp, 16
-; RV32-LMULMAX1-NEXT:    vle32.v v8, (a0)
-; RV32-LMULMAX1-NEXT:    vle32.v v9, (sp)
-; RV32-LMULMAX1-NEXT:    addi sp, sp, 32
-; RV32-LMULMAX1-NEXT:    ret
+; LMULMAX8-LABEL: si2fp_v8i1_v8f32:
+; LMULMAX8:       # %bb.0:
+; LMULMAX8-NEXT:    vsetivli zero, 8, e32,m2,ta,mu
+; LMULMAX8-NEXT:    vmv.v.i v26, 0
+; LMULMAX8-NEXT:    vmerge.vim v26, v26, -1, v0
+; LMULMAX8-NEXT:    vfcvt.f.x.v v8, v26
+; LMULMAX8-NEXT:    ret
 ;
-; RV64-LMULMAX1-LABEL: si2fp_v8i1_v8f32:
-; RV64-LMULMAX1:       # %bb.0:
-; RV64-LMULMAX1-NEXT:    addi sp, sp, -32
-; RV64-LMULMAX1-NEXT:    .cfi_def_cfa_offset 32
-; RV64-LMULMAX1-NEXT:    vsetivli zero, 4, e8,mf4,ta,mu
-; RV64-LMULMAX1-NEXT:    vmv.v.i v25, 0
-; RV64-LMULMAX1-NEXT:    vmerge.vim v26, v25, 1, v0
-; RV64-LMULMAX1-NEXT:    vmv.x.s a0, v26
-; RV64-LMULMAX1-NEXT:    andi a0, a0, 1
-; RV64-LMULMAX1-NEXT:    neg a0, a0
-; RV64-LMULMAX1-NEXT:    fcvt.s.l ft0, a0
-; RV64-LMULMAX1-NEXT:    fsw ft0, 16(sp)
-; RV64-LMULMAX1-NEXT:    vsetivli zero, 1, e8,mf4,ta,mu
-; RV64-LMULMAX1-NEXT:    vslidedown.vi v27, v26, 3
-; RV64-LMULMAX1-NEXT:    vmv.x.s a0, v27
-; RV64-LMULMAX1-NEXT:    andi a0, a0, 1
-; RV64-LMULMAX1-NEXT:    neg a0, a0
-; RV64-LMULMAX1-NEXT:    fcvt.s.l ft0, a0
-; RV64-LMULMAX1-NEXT:    fsw ft0, 28(sp)
-; RV64-LMULMAX1-NEXT:    vslidedown.vi v27, v26, 2
-; RV64-LMULMAX1-NEXT:    vmv.x.s a0, v27
-; RV64-LMULMAX1-NEXT:    andi a0, a0, 1
-; RV64-LMULMAX1-NEXT:    neg a0, a0
-; RV64-LMULMAX1-NEXT:    fcvt.s.l ft0, a0
-; RV64-LMULMAX1-NEXT:    fsw ft0, 24(sp)
-; RV64-LMULMAX1-NEXT:    vslidedown.vi v26, v26, 1
-; RV64-LMULMAX1-NEXT:    vmv.x.s a0, v26
-; RV64-LMULMAX1-NEXT:    andi a0, a0, 1
-; RV64-LMULMAX1-NEXT:    neg a0, a0
-; RV64-LMULMAX1-NEXT:    fcvt.s.l ft0, a0
-; RV64-LMULMAX1-NEXT:    fsw ft0, 20(sp)
-; RV64-LMULMAX1-NEXT:    vsetivli zero, 8, e8,mf2,ta,mu
-; RV64-LMULMAX1-NEXT:    vmv.v.i v26, 0
-; RV64-LMULMAX1-NEXT:    vmerge.vim v26, v26, 1, v0
-; RV64-LMULMAX1-NEXT:    vsetivli zero, 4, e8,mf2,ta,mu
-; RV64-LMULMAX1-NEXT:    vslidedown.vi v26, v26, 4
-; RV64-LMULMAX1-NEXT:    vsetivli zero, 4, e8,mf4,ta,mu
-; RV64-LMULMAX1-NEXT:    vmsne.vi v0, v26, 0
-; RV64-LMULMAX1-NEXT:    vmerge.vim v25, v25, 1, v0
-; RV64-LMULMAX1-NEXT:    vmv.x.s a0, v25
-; RV64-LMULMAX1-NEXT:    andi a0, a0, 1
-; RV64-LMULMAX1-NEXT:    neg a0, a0
-; RV64-LMULMAX1-NEXT:    fcvt.s.l ft0, a0
-; RV64-LMULMAX1-NEXT:    fsw ft0, 0(sp)
-; RV64-LMULMAX1-NEXT:    vsetivli zero, 1, e8,mf4,ta,mu
-; RV64-LMULMAX1-NEXT:    vslidedown.vi v26, v25, 3
-; RV64-LMULMAX1-NEXT:    vmv.x.s a0, v26
-; RV64-LMULMAX1-NEXT:    andi a0, a0, 1
-; RV64-LMULMAX1-NEXT:    neg a0, a0
-; RV64-LMULMAX1-NEXT:    fcvt.s.l ft0, a0
-; RV64-LMULMAX1-NEXT:    fsw ft0, 12(sp)
-; RV64-LMULMAX1-NEXT:    vslidedown.vi v26, v25, 2
-; RV64-LMULMAX1-NEXT:    vmv.x.s a0, v26
-; RV64-LMULMAX1-NEXT:    andi a0, a0, 1
-; RV64-LMULMAX1-NEXT:    neg a0, a0
-; RV64-LMULMAX1-NEXT:    fcvt.s.l ft0, a0
-; RV64-LMULMAX1-NEXT:    fsw ft0, 8(sp)
-; RV64-LMULMAX1-NEXT:    vslidedown.vi v25, v25, 1
-; RV64-LMULMAX1-NEXT:    vmv.x.s a0, v25
-; RV64-LMULMAX1-NEXT:    andi a0, a0, 1
-; RV64-LMULMAX1-NEXT:    neg a0, a0
-; RV64-LMULMAX1-NEXT:    fcvt.s.l ft0, a0
-; RV64-LMULMAX1-NEXT:    fsw ft0, 4(sp)
-; RV64-LMULMAX1-NEXT:    vsetivli zero, 4, e32,m1,ta,mu
-; RV64-LMULMAX1-NEXT:    addi a0, sp, 16
-; RV64-LMULMAX1-NEXT:    vle32.v v8, (a0)
-; RV64-LMULMAX1-NEXT:    vle32.v v9, (sp)
-; RV64-LMULMAX1-NEXT:    addi sp, sp, 32
-; RV64-LMULMAX1-NEXT:    ret
+; LMULMAX1-LABEL: si2fp_v8i1_v8f32:
+; LMULMAX1:       # %bb.0:
+; LMULMAX1-NEXT:    vsetivli zero, 4, e32,m1,ta,mu
+; LMULMAX1-NEXT:    vmv.v.i v25, 0
+; LMULMAX1-NEXT:    vmerge.vim v26, v25, -1, v0
+; LMULMAX1-NEXT:    vfcvt.f.x.v v8, v26
+; LMULMAX1-NEXT:    vsetivli zero, 8, e8,mf2,ta,mu
+; LMULMAX1-NEXT:    vmv.v.i v26, 0
+; LMULMAX1-NEXT:    vmerge.vim v26, v26, 1, v0
+; LMULMAX1-NEXT:    vsetivli zero, 4, e8,mf2,ta,mu
+; LMULMAX1-NEXT:    vslidedown.vi v26, v26, 4
+; LMULMAX1-NEXT:    vsetivli zero, 4, e8,mf4,ta,mu
+; LMULMAX1-NEXT:    vmsne.vi v0, v26, 0
+; LMULMAX1-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
+; LMULMAX1-NEXT:    vmerge.vim v25, v25, -1, v0
+; LMULMAX1-NEXT:    vfcvt.f.x.v v9, v25
+; LMULMAX1-NEXT:    ret
   %z = sitofp <8 x i1> %x to <8 x float>
   ret <8 x float> %z
 }
 
 define <8 x float> @ui2fp_v8i1_v8f32(<8 x i1> %x) {
-; RV32-LMULMAX8-LABEL: ui2fp_v8i1_v8f32:
-; RV32-LMULMAX8:       # %bb.0:
-; RV32-LMULMAX8-NEXT:    addi sp, sp, -64
-; RV32-LMULMAX8-NEXT:    .cfi_def_cfa_offset 64
-; RV32-LMULMAX8-NEXT:    sw ra, 60(sp) # 4-byte Folded Spill
-; RV32-LMULMAX8-NEXT:    sw s0, 56(sp) # 4-byte Folded Spill
-; RV32-LMULMAX8-NEXT:    .cfi_offset ra, -4
-; RV32-LMULMAX8-NEXT:    .cfi_offset s0, -8
-; RV32-LMULMAX8-NEXT:    addi s0, sp, 64
-; RV32-LMULMAX8-NEXT:    .cfi_def_cfa s0, 0
-; RV32-LMULMAX8-NEXT:    andi sp, sp, -32
-; RV32-LMULMAX8-NEXT:    vsetivli zero, 8, e8,mf2,ta,mu
-; RV32-LMULMAX8-NEXT:    vmv.v.i v25, 0
-; RV32-LMULMAX8-NEXT:    vmerge.vim v25, v25, 1, v0
-; RV32-LMULMAX8-NEXT:    vmv.x.s a0, v25
-; RV32-LMULMAX8-NEXT:    andi a0, a0, 1
-; RV32-LMULMAX8-NEXT:    fcvt.s.wu ft0, a0
-; RV32-LMULMAX8-NEXT:    fsw ft0, 0(sp)
-; RV32-LMULMAX8-NEXT:    vsetivli zero, 1, e8,mf2,ta,mu
-; RV32-LMULMAX8-NEXT:    vslidedown.vi v26, v25, 7
-; RV32-LMULMAX8-NEXT:    vmv.x.s a0, v26
-; RV32-LMULMAX8-NEXT:    andi a0, a0, 1
-; RV32-LMULMAX8-NEXT:    fcvt.s.wu ft0, a0
-; RV32-LMULMAX8-NEXT:    fsw ft0, 28(sp)
-; RV32-LMULMAX8-NEXT:    vslidedown.vi v26, v25, 6
-; RV32-LMULMAX8-NEXT:    vmv.x.s a0, v26
-; RV32-LMULMAX8-NEXT:    andi a0, a0, 1
-; RV32-LMULMAX8-NEXT:    fcvt.s.wu ft0, a0
-; RV32-LMULMAX8-NEXT:    fsw ft0, 24(sp)
-; RV32-LMULMAX8-NEXT:    vslidedown.vi v26, v25, 5
-; RV32-LMULMAX8-NEXT:    vmv.x.s a0, v26
-; RV32-LMULMAX8-NEXT:    andi a0, a0, 1
-; RV32-LMULMAX8-NEXT:    fcvt.s.wu ft0, a0
-; RV32-LMULMAX8-NEXT:    fsw ft0, 20(sp)
-; RV32-LMULMAX8-NEXT:    vslidedown.vi v26, v25, 4
-; RV32-LMULMAX8-NEXT:    vmv.x.s a0, v26
-; RV32-LMULMAX8-NEXT:    andi a0, a0, 1
-; RV32-LMULMAX8-NEXT:    fcvt.s.wu ft0, a0
-; RV32-LMULMAX8-NEXT:    fsw ft0, 16(sp)
-; RV32-LMULMAX8-NEXT:    vslidedown.vi v26, v25, 3
-; RV32-LMULMAX8-NEXT:    vmv.x.s a0, v26
-; RV32-LMULMAX8-NEXT:    andi a0, a0, 1
-; RV32-LMULMAX8-NEXT:    fcvt.s.wu ft0, a0
-; RV32-LMULMAX8-NEXT:    fsw ft0, 12(sp)
-; RV32-LMULMAX8-NEXT:    vslidedown.vi v26, v25, 2
-; RV32-LMULMAX8-NEXT:    vmv.x.s a0, v26
-; RV32-LMULMAX8-NEXT:    andi a0, a0, 1
-; RV32-LMULMAX8-NEXT:    fcvt.s.wu ft0, a0
-; RV32-LMULMAX8-NEXT:    fsw ft0, 8(sp)
-; RV32-LMULMAX8-NEXT:    vslidedown.vi v25, v25, 1
-; RV32-LMULMAX8-NEXT:    vmv.x.s a0, v25
-; RV32-LMULMAX8-NEXT:    andi a0, a0, 1
-; RV32-LMULMAX8-NEXT:    fcvt.s.wu ft0, a0
-; RV32-LMULMAX8-NEXT:    fsw ft0, 4(sp)
-; RV32-LMULMAX8-NEXT:    vsetivli zero, 8, e32,m2,ta,mu
-; RV32-LMULMAX8-NEXT:    vle32.v v8, (sp)
-; RV32-LMULMAX8-NEXT:    addi sp, s0, -64
-; RV32-LMULMAX8-NEXT:    lw s0, 56(sp) # 4-byte Folded Reload
-; RV32-LMULMAX8-NEXT:    lw ra, 60(sp) # 4-byte Folded Reload
-; RV32-LMULMAX8-NEXT:    addi sp, sp, 64
-; RV32-LMULMAX8-NEXT:    ret
-;
-; RV64-LMULMAX8-LABEL: ui2fp_v8i1_v8f32:
-; RV64-LMULMAX8:       # %bb.0:
-; RV64-LMULMAX8-NEXT:    addi sp, sp, -64
-; RV64-LMULMAX8-NEXT:    .cfi_def_cfa_offset 64
-; RV64-LMULMAX8-NEXT:    sd ra, 56(sp) # 8-byte Folded Spill
-; RV64-LMULMAX8-NEXT:    sd s0, 48(sp) # 8-byte Folded Spill
-; RV64-LMULMAX8-NEXT:    .cfi_offset ra, -8
-; RV64-LMULMAX8-NEXT:    .cfi_offset s0, -16
-; RV64-LMULMAX8-NEXT:    addi s0, sp, 64
-; RV64-LMULMAX8-NEXT:    .cfi_def_cfa s0, 0
-; RV64-LMULMAX8-NEXT:    andi sp, sp, -32
-; RV64-LMULMAX8-NEXT:    vsetivli zero, 8, e8,mf2,ta,mu
-; RV64-LMULMAX8-NEXT:    vmv.v.i v25, 0
-; RV64-LMULMAX8-NEXT:    vmerge.vim v25, v25, 1, v0
-; RV64-LMULMAX8-NEXT:    vmv.x.s a0, v25
-; RV64-LMULMAX8-NEXT:    andi a0, a0, 1
-; RV64-LMULMAX8-NEXT:    fcvt.s.lu ft0, a0
-; RV64-LMULMAX8-NEXT:    fsw ft0, 0(sp)
-; RV64-LMULMAX8-NEXT:    vsetivli zero, 1, e8,mf2,ta,mu
-; RV64-LMULMAX8-NEXT:    vslidedown.vi v26, v25, 7
-; RV64-LMULMAX8-NEXT:    vmv.x.s a0, v26
-; RV64-LMULMAX8-NEXT:    andi a0, a0, 1
-; RV64-LMULMAX8-NEXT:    fcvt.s.lu ft0, a0
-; RV64-LMULMAX8-NEXT:    fsw ft0, 28(sp)
-; RV64-LMULMAX8-NEXT:    vslidedown.vi v26, v25, 6
-; RV64-LMULMAX8-NEXT:    vmv.x.s a0, v26
-; RV64-LMULMAX8-NEXT:    andi a0, a0, 1
-; RV64-LMULMAX8-NEXT:    fcvt.s.lu ft0, a0
-; RV64-LMULMAX8-NEXT:    fsw ft0, 24(sp)
-; RV64-LMULMAX8-NEXT:    vslidedown.vi v26, v25, 5
-; RV64-LMULMAX8-NEXT:    vmv.x.s a0, v26
-; RV64-LMULMAX8-NEXT:    andi a0, a0, 1
-; RV64-LMULMAX8-NEXT:    fcvt.s.lu ft0, a0
-; RV64-LMULMAX8-NEXT:    fsw ft0, 20(sp)
-; RV64-LMULMAX8-NEXT:    vslidedown.vi v26, v25, 4
-; RV64-LMULMAX8-NEXT:    vmv.x.s a0, v26
-; RV64-LMULMAX8-NEXT:    andi a0, a0, 1
-; RV64-LMULMAX8-NEXT:    fcvt.s.lu ft0, a0
-; RV64-LMULMAX8-NEXT:    fsw ft0, 16(sp)
-; RV64-LMULMAX8-NEXT:    vslidedown.vi v26, v25, 3
-; RV64-LMULMAX8-NEXT:    vmv.x.s a0, v26
-; RV64-LMULMAX8-NEXT:    andi a0, a0, 1
-; RV64-LMULMAX8-NEXT:    fcvt.s.lu ft0, a0
-; RV64-LMULMAX8-NEXT:    fsw ft0, 12(sp)
-; RV64-LMULMAX8-NEXT:    vslidedown.vi v26, v25, 2
-; RV64-LMULMAX8-NEXT:    vmv.x.s a0, v26
-; RV64-LMULMAX8-NEXT:    andi a0, a0, 1
-; RV64-LMULMAX8-NEXT:    fcvt.s.lu ft0, a0
-; RV64-LMULMAX8-NEXT:    fsw ft0, 8(sp)
-; RV64-LMULMAX8-NEXT:    vslidedown.vi v25, v25, 1
-; RV64-LMULMAX8-NEXT:    vmv.x.s a0, v25
-; RV64-LMULMAX8-NEXT:    andi a0, a0, 1
-; RV64-LMULMAX8-NEXT:    fcvt.s.lu ft0, a0
-; RV64-LMULMAX8-NEXT:    fsw ft0, 4(sp)
-; RV64-LMULMAX8-NEXT:    vsetivli zero, 8, e32,m2,ta,mu
-; RV64-LMULMAX8-NEXT:    vle32.v v8, (sp)
-; RV64-LMULMAX8-NEXT:    addi sp, s0, -64
-; RV64-LMULMAX8-NEXT:    ld s0, 48(sp) # 8-byte Folded Reload
-; RV64-LMULMAX8-NEXT:    ld ra, 56(sp) # 8-byte Folded Reload
-; RV64-LMULMAX8-NEXT:    addi sp, sp, 64
-; RV64-LMULMAX8-NEXT:    ret
-;
-; RV32-LMULMAX1-LABEL: ui2fp_v8i1_v8f32:
-; RV32-LMULMAX1:       # %bb.0:
-; RV32-LMULMAX1-NEXT:    addi sp, sp, -32
-; RV32-LMULMAX1-NEXT:    .cfi_def_cfa_offset 32
-; RV32-LMULMAX1-NEXT:    vsetivli zero, 4, e8,mf4,ta,mu
-; RV32-LMULMAX1-NEXT:    vmv.v.i v25, 0
-; RV32-LMULMAX1-NEXT:    vmerge.vim v26, v25, 1, v0
-; RV32-LMULMAX1-NEXT:    vmv.x.s a0, v26
-; RV32-LMULMAX1-NEXT:    andi a0, a0, 1
-; RV32-LMULMAX1-NEXT:    fcvt.s.wu ft0, a0
-; RV32-LMULMAX1-NEXT:    fsw ft0, 16(sp)
-; RV32-LMULMAX1-NEXT:    vsetivli zero, 1, e8,mf4,ta,mu
-; RV32-LMULMAX1-NEXT:    vslidedown.vi v27, v26, 3
-; RV32-LMULMAX1-NEXT:    vmv.x.s a0, v27
-; RV32-LMULMAX1-NEXT:    andi a0, a0, 1
-; RV32-LMULMAX1-NEXT:    fcvt.s.wu ft0, a0
-; RV32-LMULMAX1-NEXT:    fsw ft0, 28(sp)
-; RV32-LMULMAX1-NEXT:    vslidedown.vi v27, v26, 2
-; RV32-LMULMAX1-NEXT:    vmv.x.s a0, v27
-; RV32-LMULMAX1-NEXT:    andi a0, a0, 1
-; RV32-LMULMAX1-NEXT:    fcvt.s.wu ft0, a0
-; RV32-LMULMAX1-NEXT:    fsw ft0, 24(sp)
-; RV32-LMULMAX1-NEXT:    vslidedown.vi v26, v26, 1
-; RV32-LMULMAX1-NEXT:    vmv.x.s a0, v26
-; RV32-LMULMAX1-NEXT:    andi a0, a0, 1
-; RV32-LMULMAX1-NEXT:    fcvt.s.wu ft0, a0
-; RV32-LMULMAX1-NEXT:    fsw ft0, 20(sp)
-; RV32-LMULMAX1-NEXT:    vsetivli zero, 8, e8,mf2,ta,mu
-; RV32-LMULMAX1-NEXT:    vmv.v.i v26, 0
-; RV32-LMULMAX1-NEXT:    vmerge.vim v26, v26, 1, v0
-; RV32-LMULMAX1-NEXT:    vsetivli zero, 4, e8,mf2,ta,mu
-; RV32-LMULMAX1-NEXT:    vslidedown.vi v26, v26, 4
-; RV32-LMULMAX1-NEXT:    vsetivli zero, 4, e8,mf4,ta,mu
-; RV32-LMULMAX1-NEXT:    vmsne.vi v0, v26, 0
-; RV32-LMULMAX1-NEXT:    vmerge.vim v25, v25, 1, v0
-; RV32-LMULMAX1-NEXT:    vmv.x.s a0, v25
-; RV32-LMULMAX1-NEXT:    andi a0, a0, 1
-; RV32-LMULMAX1-NEXT:    fcvt.s.wu ft0, a0
-; RV32-LMULMAX1-NEXT:    fsw ft0, 0(sp)
-; RV32-LMULMAX1-NEXT:    vsetivli zero, 1, e8,mf4,ta,mu
-; RV32-LMULMAX1-NEXT:    vslidedown.vi v26, v25, 3
-; RV32-LMULMAX1-NEXT:    vmv.x.s a0, v26
-; RV32-LMULMAX1-NEXT:    andi a0, a0, 1
-; RV32-LMULMAX1-NEXT:    fcvt.s.wu ft0, a0
-; RV32-LMULMAX1-NEXT:    fsw ft0, 12(sp)
-; RV32-LMULMAX1-NEXT:    vslidedown.vi v26, v25, 2
-; RV32-LMULMAX1-NEXT:    vmv.x.s a0, v26
-; RV32-LMULMAX1-NEXT:    andi a0, a0, 1
-; RV32-LMULMAX1-NEXT:    fcvt.s.wu ft0, a0
-; RV32-LMULMAX1-NEXT:    fsw ft0, 8(sp)
-; RV32-LMULMAX1-NEXT:    vslidedown.vi v25, v25, 1
-; RV32-LMULMAX1-NEXT:    vmv.x.s a0, v25
-; RV32-LMULMAX1-NEXT:    andi a0, a0, 1
-; RV32-LMULMAX1-NEXT:    fcvt.s.wu ft0, a0
-; RV32-LMULMAX1-NEXT:    fsw ft0, 4(sp)
-; RV32-LMULMAX1-NEXT:    vsetivli zero, 4, e32,m1,ta,mu
-; RV32-LMULMAX1-NEXT:    addi a0, sp, 16
-; RV32-LMULMAX1-NEXT:    vle32.v v8, (a0)
-; RV32-LMULMAX1-NEXT:    vle32.v v9, (sp)
-; RV32-LMULMAX1-NEXT:    addi sp, sp, 32
-; RV32-LMULMAX1-NEXT:    ret
+; LMULMAX8-LABEL: ui2fp_v8i1_v8f32:
+; LMULMAX8:       # %bb.0:
+; LMULMAX8-NEXT:    vsetivli zero, 8, e32,m2,ta,mu
+; LMULMAX8-NEXT:    vmv.v.i v26, 0
+; LMULMAX8-NEXT:    vmerge.vim v26, v26, 1, v0
+; LMULMAX8-NEXT:    vfcvt.f.xu.v v8, v26
+; LMULMAX8-NEXT:    ret
 ;
-; RV64-LMULMAX1-LABEL: ui2fp_v8i1_v8f32:
-; RV64-LMULMAX1:       # %bb.0:
-; RV64-LMULMAX1-NEXT:    addi sp, sp, -32
-; RV64-LMULMAX1-NEXT:    .cfi_def_cfa_offset 32
-; RV64-LMULMAX1-NEXT:    vsetivli zero, 4, e8,mf4,ta,mu
-; RV64-LMULMAX1-NEXT:    vmv.v.i v25, 0
-; RV64-LMULMAX1-NEXT:    vmerge.vim v26, v25, 1, v0
-; RV64-LMULMAX1-NEXT:    vmv.x.s a0, v26
-; RV64-LMULMAX1-NEXT:    andi a0, a0, 1
-; RV64-LMULMAX1-NEXT:    fcvt.s.lu ft0, a0
-; RV64-LMULMAX1-NEXT:    fsw ft0, 16(sp)
-; RV64-LMULMAX1-NEXT:    vsetivli zero, 1, e8,mf4,ta,mu
-; RV64-LMULMAX1-NEXT:    vslidedown.vi v27, v26, 3
-; RV64-LMULMAX1-NEXT:    vmv.x.s a0, v27
-; RV64-LMULMAX1-NEXT:    andi a0, a0, 1
-; RV64-LMULMAX1-NEXT:    fcvt.s.lu ft0, a0
-; RV64-LMULMAX1-NEXT:    fsw ft0, 28(sp)
-; RV64-LMULMAX1-NEXT:    vslidedown.vi v27, v26, 2
-; RV64-LMULMAX1-NEXT:    vmv.x.s a0, v27
-; RV64-LMULMAX1-NEXT:    andi a0, a0, 1
-; RV64-LMULMAX1-NEXT:    fcvt.s.lu ft0, a0
-; RV64-LMULMAX1-NEXT:    fsw ft0, 24(sp)
-; RV64-LMULMAX1-NEXT:    vslidedown.vi v26, v26, 1
-; RV64-LMULMAX1-NEXT:    vmv.x.s a0, v26
-; RV64-LMULMAX1-NEXT:    andi a0, a0, 1
-; RV64-LMULMAX1-NEXT:    fcvt.s.lu ft0, a0
-; RV64-LMULMAX1-NEXT:    fsw ft0, 20(sp)
-; RV64-LMULMAX1-NEXT:    vsetivli zero, 8, e8,mf2,ta,mu
-; RV64-LMULMAX1-NEXT:    vmv.v.i v26, 0
-; RV64-LMULMAX1-NEXT:    vmerge.vim v26, v26, 1, v0
-; RV64-LMULMAX1-NEXT:    vsetivli zero, 4, e8,mf2,ta,mu
-; RV64-LMULMAX1-NEXT:    vslidedown.vi v26, v26, 4
-; RV64-LMULMAX1-NEXT:    vsetivli zero, 4, e8,mf4,ta,mu
-; RV64-LMULMAX1-NEXT:    vmsne.vi v0, v26, 0
-; RV64-LMULMAX1-NEXT:    vmerge.vim v25, v25, 1, v0
-; RV64-LMULMAX1-NEXT:    vmv.x.s a0, v25
-; RV64-LMULMAX1-NEXT:    andi a0, a0, 1
-; RV64-LMULMAX1-NEXT:    fcvt.s.lu ft0, a0
-; RV64-LMULMAX1-NEXT:    fsw ft0, 0(sp)
-; RV64-LMULMAX1-NEXT:    vsetivli zero, 1, e8,mf4,ta,mu
-; RV64-LMULMAX1-NEXT:    vslidedown.vi v26, v25, 3
-; RV64-LMULMAX1-NEXT:    vmv.x.s a0, v26
-; RV64-LMULMAX1-NEXT:    andi a0, a0, 1
-; RV64-LMULMAX1-NEXT:    fcvt.s.lu ft0, a0
-; RV64-LMULMAX1-NEXT:    fsw ft0, 12(sp)
-; RV64-LMULMAX1-NEXT:    vslidedown.vi v26, v25, 2
-; RV64-LMULMAX1-NEXT:    vmv.x.s a0, v26
-; RV64-LMULMAX1-NEXT:    andi a0, a0, 1
-; RV64-LMULMAX1-NEXT:    fcvt.s.lu ft0, a0
-; RV64-LMULMAX1-NEXT:    fsw ft0, 8(sp)
-; RV64-LMULMAX1-NEXT:    vslidedown.vi v25, v25, 1
-; RV64-LMULMAX1-NEXT:    vmv.x.s a0, v25
-; RV64-LMULMAX1-NEXT:    andi a0, a0, 1
-; RV64-LMULMAX1-NEXT:    fcvt.s.lu ft0, a0
-; RV64-LMULMAX1-NEXT:    fsw ft0, 4(sp)
-; RV64-LMULMAX1-NEXT:    vsetivli zero, 4, e32,m1,ta,mu
-; RV64-LMULMAX1-NEXT:    addi a0, sp, 16
-; RV64-LMULMAX1-NEXT:    vle32.v v8, (a0)
-; RV64-LMULMAX1-NEXT:    vle32.v v9, (sp)
-; RV64-LMULMAX1-NEXT:    addi sp, sp, 32
-; RV64-LMULMAX1-NEXT:    ret
+; LMULMAX1-LABEL: ui2fp_v8i1_v8f32:
+; LMULMAX1:       # %bb.0:
+; LMULMAX1-NEXT:    vsetivli zero, 4, e32,m1,ta,mu
+; LMULMAX1-NEXT:    vmv.v.i v25, 0
+; LMULMAX1-NEXT:    vmerge.vim v26, v25, 1, v0
+; LMULMAX1-NEXT:    vfcvt.f.xu.v v8, v26
+; LMULMAX1-NEXT:    vsetivli zero, 8, e8,mf2,ta,mu
+; LMULMAX1-NEXT:    vmv.v.i v26, 0
+; LMULMAX1-NEXT:    vmerge.vim v26, v26, 1, v0
+; LMULMAX1-NEXT:    vsetivli zero, 4, e8,mf2,ta,mu
+; LMULMAX1-NEXT:    vslidedown.vi v26, v26, 4
+; LMULMAX1-NEXT:    vsetivli zero, 4, e8,mf4,ta,mu
+; LMULMAX1-NEXT:    vmsne.vi v0, v26, 0
+; LMULMAX1-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
+; LMULMAX1-NEXT:    vmerge.vim v25, v25, 1, v0
+; LMULMAX1-NEXT:    vfcvt.f.xu.v v9, v25
+; LMULMAX1-NEXT:    ret
   %z = uitofp <8 x i1> %x to <8 x float>
   ret <8 x float> %z
 }
@@ -829,597 +293,103 @@ define void @ui2fp_v8i16_v8f64(<8 x i16>* %x, <8 x double>* %y) {
 }
 
 define <8 x double> @si2fp_v8i1_v8f64(<8 x i1> %x) {
-; RV32-LMULMAX8-LABEL: si2fp_v8i1_v8f64:
-; RV32-LMULMAX8:       # %bb.0:
-; RV32-LMULMAX8-NEXT:    addi sp, sp, -128
-; RV32-LMULMAX8-NEXT:    .cfi_def_cfa_offset 128
-; RV32-LMULMAX8-NEXT:    sw ra, 124(sp) # 4-byte Folded Spill
-; RV32-LMULMAX8-NEXT:    sw s0, 120(sp) # 4-byte Folded Spill
-; RV32-LMULMAX8-NEXT:    .cfi_offset ra, -4
-; RV32-LMULMAX8-NEXT:    .cfi_offset s0, -8
-; RV32-LMULMAX8-NEXT:    addi s0, sp, 128
-; RV32-LMULMAX8-NEXT:    .cfi_def_cfa s0, 0
-; RV32-LMULMAX8-NEXT:    andi sp, sp, -64
-; RV32-LMULMAX8-NEXT:    vsetivli zero, 8, e8,mf2,ta,mu
-; RV32-LMULMAX8-NEXT:    vmv.v.i v25, 0
-; RV32-LMULMAX8-NEXT:    vmerge.vim v25, v25, 1, v0
-; RV32-LMULMAX8-NEXT:    vmv.x.s a0, v25
-; RV32-LMULMAX8-NEXT:    andi a0, a0, 1
-; RV32-LMULMAX8-NEXT:    neg a0, a0
-; RV32-LMULMAX8-NEXT:    fcvt.d.w ft0, a0
-; RV32-LMULMAX8-NEXT:    fsd ft0, 0(sp)
-; RV32-LMULMAX8-NEXT:    vsetivli zero, 1, e8,mf2,ta,mu
-; RV32-LMULMAX8-NEXT:    vslidedown.vi v26, v25, 7
-; RV32-LMULMAX8-NEXT:    vmv.x.s a0, v26
-; RV32-LMULMAX8-NEXT:    andi a0, a0, 1
-; RV32-LMULMAX8-NEXT:    neg a0, a0
-; RV32-LMULMAX8-NEXT:    fcvt.d.w ft0, a0
-; RV32-LMULMAX8-NEXT:    fsd ft0, 56(sp)
-; RV32-LMULMAX8-NEXT:    vslidedown.vi v26, v25, 6
-; RV32-LMULMAX8-NEXT:    vmv.x.s a0, v26
-; RV32-LMULMAX8-NEXT:    andi a0, a0, 1
-; RV32-LMULMAX8-NEXT:    neg a0, a0
-; RV32-LMULMAX8-NEXT:    fcvt.d.w ft0, a0
-; RV32-LMULMAX8-NEXT:    fsd ft0, 48(sp)
-; RV32-LMULMAX8-NEXT:    vslidedown.vi v26, v25, 5
-; RV32-LMULMAX8-NEXT:    vmv.x.s a0, v26
-; RV32-LMULMAX8-NEXT:    andi a0, a0, 1
-; RV32-LMULMAX8-NEXT:    neg a0, a0
-; RV32-LMULMAX8-NEXT:    fcvt.d.w ft0, a0
-; RV32-LMULMAX8-NEXT:    fsd ft0, 40(sp)
-; RV32-LMULMAX8-NEXT:    vslidedown.vi v26, v25, 4
-; RV32-LMULMAX8-NEXT:    vmv.x.s a0, v26
-; RV32-LMULMAX8-NEXT:    andi a0, a0, 1
-; RV32-LMULMAX8-NEXT:    neg a0, a0
-; RV32-LMULMAX8-NEXT:    fcvt.d.w ft0, a0
-; RV32-LMULMAX8-NEXT:    fsd ft0, 32(sp)
-; RV32-LMULMAX8-NEXT:    vslidedown.vi v26, v25, 3
-; RV32-LMULMAX8-NEXT:    vmv.x.s a0, v26
-; RV32-LMULMAX8-NEXT:    andi a0, a0, 1
-; RV32-LMULMAX8-NEXT:    neg a0, a0
-; RV32-LMULMAX8-NEXT:    fcvt.d.w ft0, a0
-; RV32-LMULMAX8-NEXT:    fsd ft0, 24(sp)
-; RV32-LMULMAX8-NEXT:    vslidedown.vi v26, v25, 2
-; RV32-LMULMAX8-NEXT:    vmv.x.s a0, v26
-; RV32-LMULMAX8-NEXT:    andi a0, a0, 1
-; RV32-LMULMAX8-NEXT:    neg a0, a0
-; RV32-LMULMAX8-NEXT:    fcvt.d.w ft0, a0
-; RV32-LMULMAX8-NEXT:    fsd ft0, 16(sp)
-; RV32-LMULMAX8-NEXT:    vslidedown.vi v25, v25, 1
-; RV32-LMULMAX8-NEXT:    vmv.x.s a0, v25
-; RV32-LMULMAX8-NEXT:    andi a0, a0, 1
-; RV32-LMULMAX8-NEXT:    neg a0, a0
-; RV32-LMULMAX8-NEXT:    fcvt.d.w ft0, a0
-; RV32-LMULMAX8-NEXT:    fsd ft0, 8(sp)
-; RV32-LMULMAX8-NEXT:    vsetivli zero, 8, e64,m4,ta,mu
-; RV32-LMULMAX8-NEXT:    vle64.v v8, (sp)
-; RV32-LMULMAX8-NEXT:    addi sp, s0, -128
-; RV32-LMULMAX8-NEXT:    lw s0, 120(sp) # 4-byte Folded Reload
-; RV32-LMULMAX8-NEXT:    lw ra, 124(sp) # 4-byte Folded Reload
-; RV32-LMULMAX8-NEXT:    addi sp, sp, 128
-; RV32-LMULMAX8-NEXT:    ret
-;
-; RV64-LMULMAX8-LABEL: si2fp_v8i1_v8f64:
-; RV64-LMULMAX8:       # %bb.0:
-; RV64-LMULMAX8-NEXT:    addi sp, sp, -128
-; RV64-LMULMAX8-NEXT:    .cfi_def_cfa_offset 128
-; RV64-LMULMAX8-NEXT:    sd ra, 120(sp) # 8-byte Folded Spill
-; RV64-LMULMAX8-NEXT:    sd s0, 112(sp) # 8-byte Folded Spill
-; RV64-LMULMAX8-NEXT:    .cfi_offset ra, -8
-; RV64-LMULMAX8-NEXT:    .cfi_offset s0, -16
-; RV64-LMULMAX8-NEXT:    addi s0, sp, 128
-; RV64-LMULMAX8-NEXT:    .cfi_def_cfa s0, 0
-; RV64-LMULMAX8-NEXT:    andi sp, sp, -64
-; RV64-LMULMAX8-NEXT:    vsetivli zero, 8, e8,mf2,ta,mu
-; RV64-LMULMAX8-NEXT:    vmv.v.i v25, 0
-; RV64-LMULMAX8-NEXT:    vmerge.vim v25, v25, 1, v0
-; RV64-LMULMAX8-NEXT:    vmv.x.s a0, v25
-; RV64-LMULMAX8-NEXT:    andi a0, a0, 1
-; RV64-LMULMAX8-NEXT:    neg a0, a0
-; RV64-LMULMAX8-NEXT:    fcvt.d.l ft0, a0
-; RV64-LMULMAX8-NEXT:    fsd ft0, 0(sp)
-; RV64-LMULMAX8-NEXT:    vsetivli zero, 1, e8,mf2,ta,mu
-; RV64-LMULMAX8-NEXT:    vslidedown.vi v26, v25, 7
-; RV64-LMULMAX8-NEXT:    vmv.x.s a0, v26
-; RV64-LMULMAX8-NEXT:    andi a0, a0, 1
-; RV64-LMULMAX8-NEXT:    neg a0, a0
-; RV64-LMULMAX8-NEXT:    fcvt.d.l ft0, a0
-; RV64-LMULMAX8-NEXT:    fsd ft0, 56(sp)
-; RV64-LMULMAX8-NEXT:    vslidedown.vi v26, v25, 6
-; RV64-LMULMAX8-NEXT:    vmv.x.s a0, v26
-; RV64-LMULMAX8-NEXT:    andi a0, a0, 1
-; RV64-LMULMAX8-NEXT:    neg a0, a0
-; RV64-LMULMAX8-NEXT:    fcvt.d.l ft0, a0
-; RV64-LMULMAX8-NEXT:    fsd ft0, 48(sp)
-; RV64-LMULMAX8-NEXT:    vslidedown.vi v26, v25, 5
-; RV64-LMULMAX8-NEXT:    vmv.x.s a0, v26
-; RV64-LMULMAX8-NEXT:    andi a0, a0, 1
-; RV64-LMULMAX8-NEXT:    neg a0, a0
-; RV64-LMULMAX8-NEXT:    fcvt.d.l ft0, a0
-; RV64-LMULMAX8-NEXT:    fsd ft0, 40(sp)
-; RV64-LMULMAX8-NEXT:    vslidedown.vi v26, v25, 4
-; RV64-LMULMAX8-NEXT:    vmv.x.s a0, v26
-; RV64-LMULMAX8-NEXT:    andi a0, a0, 1
-; RV64-LMULMAX8-NEXT:    neg a0, a0
-; RV64-LMULMAX8-NEXT:    fcvt.d.l ft0, a0
-; RV64-LMULMAX8-NEXT:    fsd ft0, 32(sp)
-; RV64-LMULMAX8-NEXT:    vslidedown.vi v26, v25, 3
-; RV64-LMULMAX8-NEXT:    vmv.x.s a0, v26
-; RV64-LMULMAX8-NEXT:    andi a0, a0, 1
-; RV64-LMULMAX8-NEXT:    neg a0, a0
-; RV64-LMULMAX8-NEXT:    fcvt.d.l ft0, a0
-; RV64-LMULMAX8-NEXT:    fsd ft0, 24(sp)
-; RV64-LMULMAX8-NEXT:    vslidedown.vi v26, v25, 2
-; RV64-LMULMAX8-NEXT:    vmv.x.s a0, v26
-; RV64-LMULMAX8-NEXT:    andi a0, a0, 1
-; RV64-LMULMAX8-NEXT:    neg a0, a0
-; RV64-LMULMAX8-NEXT:    fcvt.d.l ft0, a0
-; RV64-LMULMAX8-NEXT:    fsd ft0, 16(sp)
-; RV64-LMULMAX8-NEXT:    vslidedown.vi v25, v25, 1
-; RV64-LMULMAX8-NEXT:    vmv.x.s a0, v25
-; RV64-LMULMAX8-NEXT:    andi a0, a0, 1
-; RV64-LMULMAX8-NEXT:    neg a0, a0
-; RV64-LMULMAX8-NEXT:    fcvt.d.l ft0, a0
-; RV64-LMULMAX8-NEXT:    fsd ft0, 8(sp)
-; RV64-LMULMAX8-NEXT:    vsetivli zero, 8, e64,m4,ta,mu
-; RV64-LMULMAX8-NEXT:    vle64.v v8, (sp)
-; RV64-LMULMAX8-NEXT:    addi sp, s0, -128
-; RV64-LMULMAX8-NEXT:    ld s0, 112(sp) # 8-byte Folded Reload
-; RV64-LMULMAX8-NEXT:    ld ra, 120(sp) # 8-byte Folded Reload
-; RV64-LMULMAX8-NEXT:    addi sp, sp, 128
-; RV64-LMULMAX8-NEXT:    ret
-;
-; RV32-LMULMAX1-LABEL: si2fp_v8i1_v8f64:
-; RV32-LMULMAX1:       # %bb.0:
-; RV32-LMULMAX1-NEXT:    vsetivli zero, 2, e8,mf8,ta,mu
-; RV32-LMULMAX1-NEXT:    vmv.v.i v25, 0
-; RV32-LMULMAX1-NEXT:    vmerge.vim v26, v25, 1, v0
-; RV32-LMULMAX1-NEXT:    vmv.x.s a0, v26
-; RV32-LMULMAX1-NEXT:    andi a0, a0, 1
-; RV32-LMULMAX1-NEXT:    neg a0, a0
-; RV32-LMULMAX1-NEXT:    fcvt.d.w ft0, a0
-; RV32-LMULMAX1-NEXT:    vsetivli zero, 1, e8,mf8,ta,mu
-; RV32-LMULMAX1-NEXT:    vslidedown.vi v26, v26, 1
-; RV32-LMULMAX1-NEXT:    vmv.x.s a0, v26
-; RV32-LMULMAX1-NEXT:    andi a0, a0, 1
-; RV32-LMULMAX1-NEXT:    neg a0, a0
-; RV32-LMULMAX1-NEXT:    fcvt.d.w ft1, a0
-; RV32-LMULMAX1-NEXT:    vsetivli zero, 2, e64,m1,ta,mu
-; RV32-LMULMAX1-NEXT:    vfmv.v.f v8, ft1
-; RV32-LMULMAX1-NEXT:    vfmv.s.f v8, ft0
-; RV32-LMULMAX1-NEXT:    vsetivli zero, 4, e8,mf4,ta,mu
-; RV32-LMULMAX1-NEXT:    vmv.v.i v26, 0
-; RV32-LMULMAX1-NEXT:    vmerge.vim v27, v26, 1, v0
-; RV32-LMULMAX1-NEXT:    vmv1r.v v28, v0
-; RV32-LMULMAX1-NEXT:    vsetivli zero, 2, e8,mf4,ta,mu
-; RV32-LMULMAX1-NEXT:    vslidedown.vi v27, v27, 2
-; RV32-LMULMAX1-NEXT:    vsetivli zero, 2, e8,mf8,ta,mu
-; RV32-LMULMAX1-NEXT:    vmsne.vi v0, v27, 0
-; RV32-LMULMAX1-NEXT:    vmerge.vim v27, v25, 1, v0
-; RV32-LMULMAX1-NEXT:    vmv.x.s a0, v27
-; RV32-LMULMAX1-NEXT:    andi a0, a0, 1
-; RV32-LMULMAX1-NEXT:    neg a0, a0
-; RV32-LMULMAX1-NEXT:    fcvt.d.w ft0, a0
-; RV32-LMULMAX1-NEXT:    vsetivli zero, 1, e8,mf8,ta,mu
-; RV32-LMULMAX1-NEXT:    vslidedown.vi v27, v27, 1
-; RV32-LMULMAX1-NEXT:    vmv.x.s a0, v27
-; RV32-LMULMAX1-NEXT:    andi a0, a0, 1
-; RV32-LMULMAX1-NEXT:    neg a0, a0
-; RV32-LMULMAX1-NEXT:    fcvt.d.w ft1, a0
-; RV32-LMULMAX1-NEXT:    vsetivli zero, 2, e64,m1,ta,mu
-; RV32-LMULMAX1-NEXT:    vfmv.v.f v9, ft1
-; RV32-LMULMAX1-NEXT:    vfmv.s.f v9, ft0
-; RV32-LMULMAX1-NEXT:    vsetivli zero, 8, e8,mf2,ta,mu
-; RV32-LMULMAX1-NEXT:    vmv.v.i v27, 0
-; RV32-LMULMAX1-NEXT:    vmv1r.v v0, v28
-; RV32-LMULMAX1-NEXT:    vmerge.vim v27, v27, 1, v0
-; RV32-LMULMAX1-NEXT:    vsetivli zero, 4, e8,mf2,ta,mu
-; RV32-LMULMAX1-NEXT:    vslidedown.vi v27, v27, 4
-; RV32-LMULMAX1-NEXT:    vsetivli zero, 4, e8,mf4,ta,mu
-; RV32-LMULMAX1-NEXT:    vmsne.vi v0, v27, 0
-; RV32-LMULMAX1-NEXT:    vsetivli zero, 2, e8,mf8,ta,mu
-; RV32-LMULMAX1-NEXT:    vmerge.vim v27, v25, 1, v0
-; RV32-LMULMAX1-NEXT:    vmv.x.s a0, v27
-; RV32-LMULMAX1-NEXT:    andi a0, a0, 1
-; RV32-LMULMAX1-NEXT:    neg a0, a0
-; RV32-LMULMAX1-NEXT:    fcvt.d.w ft0, a0
-; RV32-LMULMAX1-NEXT:    vsetivli zero, 1, e8,mf8,ta,mu
-; RV32-LMULMAX1-NEXT:    vslidedown.vi v27, v27, 1
-; RV32-LMULMAX1-NEXT:    vmv.x.s a0, v27
-; RV32-LMULMAX1-NEXT:    andi a0, a0, 1
-; RV32-LMULMAX1-NEXT:    neg a0, a0
-; RV32-LMULMAX1-NEXT:    fcvt.d.w ft1, a0
-; RV32-LMULMAX1-NEXT:    vsetivli zero, 2, e64,m1,ta,mu
-; RV32-LMULMAX1-NEXT:    vfmv.v.f v10, ft1
-; RV32-LMULMAX1-NEXT:    vfmv.s.f v10, ft0
-; RV32-LMULMAX1-NEXT:    vsetivli zero, 4, e8,mf4,ta,mu
-; RV32-LMULMAX1-NEXT:    vmerge.vim v26, v26, 1, v0
-; RV32-LMULMAX1-NEXT:    vsetivli zero, 2, e8,mf4,ta,mu
-; RV32-LMULMAX1-NEXT:    vslidedown.vi v26, v26, 2
-; RV32-LMULMAX1-NEXT:    vsetivli zero, 2, e8,mf8,ta,mu
-; RV32-LMULMAX1-NEXT:    vmsne.vi v0, v26, 0
-; RV32-LMULMAX1-NEXT:    vmerge.vim v25, v25, 1, v0
-; RV32-LMULMAX1-NEXT:    vmv.x.s a0, v25
-; RV32-LMULMAX1-NEXT:    andi a0, a0, 1
-; RV32-LMULMAX1-NEXT:    neg a0, a0
-; RV32-LMULMAX1-NEXT:    fcvt.d.w ft0, a0
-; RV32-LMULMAX1-NEXT:    vsetivli zero, 1, e8,mf8,ta,mu
-; RV32-LMULMAX1-NEXT:    vslidedown.vi v25, v25, 1
-; RV32-LMULMAX1-NEXT:    vmv.x.s a0, v25
-; RV32-LMULMAX1-NEXT:    andi a0, a0, 1
-; RV32-LMULMAX1-NEXT:    neg a0, a0
-; RV32-LMULMAX1-NEXT:    fcvt.d.w ft1, a0
-; RV32-LMULMAX1-NEXT:    vsetivli zero, 2, e64,m1,ta,mu
-; RV32-LMULMAX1-NEXT:    vfmv.v.f v11, ft1
-; RV32-LMULMAX1-NEXT:    vfmv.s.f v11, ft0
-; RV32-LMULMAX1-NEXT:    ret
+; LMULMAX8-LABEL: si2fp_v8i1_v8f64:
+; LMULMAX8:       # %bb.0:
+; LMULMAX8-NEXT:    vsetivli zero, 8, e64,m4,ta,mu
+; LMULMAX8-NEXT:    vmv.v.i v28, 0
+; LMULMAX8-NEXT:    vmerge.vim v28, v28, -1, v0
+; LMULMAX8-NEXT:    vfcvt.f.x.v v8, v28
+; LMULMAX8-NEXT:    ret
 ;
-; RV64-LMULMAX1-LABEL: si2fp_v8i1_v8f64:
-; RV64-LMULMAX1:       # %bb.0:
-; RV64-LMULMAX1-NEXT:    vsetivli zero, 2, e8,mf8,ta,mu
-; RV64-LMULMAX1-NEXT:    vmv.v.i v25, 0
-; RV64-LMULMAX1-NEXT:    vmerge.vim v26, v25, 1, v0
-; RV64-LMULMAX1-NEXT:    vmv.x.s a0, v26
-; RV64-LMULMAX1-NEXT:    andi a0, a0, 1
-; RV64-LMULMAX1-NEXT:    neg a0, a0
-; RV64-LMULMAX1-NEXT:    fcvt.d.l ft0, a0
-; RV64-LMULMAX1-NEXT:    vsetivli zero, 1, e8,mf8,ta,mu
-; RV64-LMULMAX1-NEXT:    vslidedown.vi v26, v26, 1
-; RV64-LMULMAX1-NEXT:    vmv.x.s a0, v26
-; RV64-LMULMAX1-NEXT:    andi a0, a0, 1
-; RV64-LMULMAX1-NEXT:    neg a0, a0
-; RV64-LMULMAX1-NEXT:    fcvt.d.l ft1, a0
-; RV64-LMULMAX1-NEXT:    vsetivli zero, 2, e64,m1,ta,mu
-; RV64-LMULMAX1-NEXT:    vfmv.v.f v8, ft1
-; RV64-LMULMAX1-NEXT:    vfmv.s.f v8, ft0
-; RV64-LMULMAX1-NEXT:    vsetivli zero, 4, e8,mf4,ta,mu
-; RV64-LMULMAX1-NEXT:    vmv.v.i v26, 0
-; RV64-LMULMAX1-NEXT:    vmerge.vim v27, v26, 1, v0
-; RV64-LMULMAX1-NEXT:    vmv1r.v v28, v0
-; RV64-LMULMAX1-NEXT:    vsetivli zero, 2, e8,mf4,ta,mu
-; RV64-LMULMAX1-NEXT:    vslidedown.vi v27, v27, 2
-; RV64-LMULMAX1-NEXT:    vsetivli zero, 2, e8,mf8,ta,mu
-; RV64-LMULMAX1-NEXT:    vmsne.vi v0, v27, 0
-; RV64-LMULMAX1-NEXT:    vmerge.vim v27, v25, 1, v0
-; RV64-LMULMAX1-NEXT:    vmv.x.s a0, v27
-; RV64-LMULMAX1-NEXT:    andi a0, a0, 1
-; RV64-LMULMAX1-NEXT:    neg a0, a0
-; RV64-LMULMAX1-NEXT:    fcvt.d.l ft0, a0
-; RV64-LMULMAX1-NEXT:    vsetivli zero, 1, e8,mf8,ta,mu
-; RV64-LMULMAX1-NEXT:    vslidedown.vi v27, v27, 1
-; RV64-LMULMAX1-NEXT:    vmv.x.s a0, v27
-; RV64-LMULMAX1-NEXT:    andi a0, a0, 1
-; RV64-LMULMAX1-NEXT:    neg a0, a0
-; RV64-LMULMAX1-NEXT:    fcvt.d.l ft1, a0
-; RV64-LMULMAX1-NEXT:    vsetivli zero, 2, e64,m1,ta,mu
-; RV64-LMULMAX1-NEXT:    vfmv.v.f v9, ft1
-; RV64-LMULMAX1-NEXT:    vfmv.s.f v9, ft0
-; RV64-LMULMAX1-NEXT:    vsetivli zero, 8, e8,mf2,ta,mu
-; RV64-LMULMAX1-NEXT:    vmv.v.i v27, 0
-; RV64-LMULMAX1-NEXT:    vmv1r.v v0, v28
-; RV64-LMULMAX1-NEXT:    vmerge.vim v27, v27, 1, v0
-; RV64-LMULMAX1-NEXT:    vsetivli zero, 4, e8,mf2,ta,mu
-; RV64-LMULMAX1-NEXT:    vslidedown.vi v27, v27, 4
-; RV64-LMULMAX1-NEXT:    vsetivli zero, 4, e8,mf4,ta,mu
-; RV64-LMULMAX1-NEXT:    vmsne.vi v0, v27, 0
-; RV64-LMULMAX1-NEXT:    vsetivli zero, 2, e8,mf8,ta,mu
-; RV64-LMULMAX1-NEXT:    vmerge.vim v27, v25, 1, v0
-; RV64-LMULMAX1-NEXT:    vmv.x.s a0, v27
-; RV64-LMULMAX1-NEXT:    andi a0, a0, 1
-; RV64-LMULMAX1-NEXT:    neg a0, a0
-; RV64-LMULMAX1-NEXT:    fcvt.d.l ft0, a0
-; RV64-LMULMAX1-NEXT:    vsetivli zero, 1, e8,mf8,ta,mu
-; RV64-LMULMAX1-NEXT:    vslidedown.vi v27, v27, 1
-; RV64-LMULMAX1-NEXT:    vmv.x.s a0, v27
-; RV64-LMULMAX1-NEXT:    andi a0, a0, 1
-; RV64-LMULMAX1-NEXT:    neg a0, a0
-; RV64-LMULMAX1-NEXT:    fcvt.d.l ft1, a0
-; RV64-LMULMAX1-NEXT:    vsetivli zero, 2, e64,m1,ta,mu
-; RV64-LMULMAX1-NEXT:    vfmv.v.f v10, ft1
-; RV64-LMULMAX1-NEXT:    vfmv.s.f v10, ft0
-; RV64-LMULMAX1-NEXT:    vsetivli zero, 4, e8,mf4,ta,mu
-; RV64-LMULMAX1-NEXT:    vmerge.vim v26, v26, 1, v0
-; RV64-LMULMAX1-NEXT:    vsetivli zero, 2, e8,mf4,ta,mu
-; RV64-LMULMAX1-NEXT:    vslidedown.vi v26, v26, 2
-; RV64-LMULMAX1-NEXT:    vsetivli zero, 2, e8,mf8,ta,mu
-; RV64-LMULMAX1-NEXT:    vmsne.vi v0, v26, 0
-; RV64-LMULMAX1-NEXT:    vmerge.vim v25, v25, 1, v0
-; RV64-LMULMAX1-NEXT:    vmv.x.s a0, v25
-; RV64-LMULMAX1-NEXT:    andi a0, a0, 1
-; RV64-LMULMAX1-NEXT:    neg a0, a0
-; RV64-LMULMAX1-NEXT:    fcvt.d.l ft0, a0
-; RV64-LMULMAX1-NEXT:    vsetivli zero, 1, e8,mf8,ta,mu
-; RV64-LMULMAX1-NEXT:    vslidedown.vi v25, v25, 1
-; RV64-LMULMAX1-NEXT:    vmv.x.s a0, v25
-; RV64-LMULMAX1-NEXT:    andi a0, a0, 1
-; RV64-LMULMAX1-NEXT:    neg a0, a0
-; RV64-LMULMAX1-NEXT:    fcvt.d.l ft1, a0
-; RV64-LMULMAX1-NEXT:    vsetivli zero, 2, e64,m1,ta,mu
-; RV64-LMULMAX1-NEXT:    vfmv.v.f v11, ft1
-; RV64-LMULMAX1-NEXT:    vfmv.s.f v11, ft0
-; RV64-LMULMAX1-NEXT:    ret
+; LMULMAX1-LABEL: si2fp_v8i1_v8f64:
+; LMULMAX1:       # %bb.0:
+; LMULMAX1-NEXT:    vsetivli zero, 2, e64,m1,ta,mu
+; LMULMAX1-NEXT:    vmv.v.i v25, 0
+; LMULMAX1-NEXT:    vmerge.vim v26, v25, -1, v0
+; LMULMAX1-NEXT:    vfcvt.f.x.v v8, v26
+; LMULMAX1-NEXT:    vsetivli zero, 4, e8,mf4,ta,mu
+; LMULMAX1-NEXT:    vmv.v.i v26, 0
+; LMULMAX1-NEXT:    vmerge.vim v27, v26, 1, v0
+; LMULMAX1-NEXT:    vmv1r.v v29, v0
+; LMULMAX1-NEXT:    vsetivli zero, 2, e8,mf4,ta,mu
+; LMULMAX1-NEXT:    vslidedown.vi v27, v27, 2
+; LMULMAX1-NEXT:    vsetivli zero, 2, e8,mf8,ta,mu
+; LMULMAX1-NEXT:    vmsne.vi v0, v27, 0
+; LMULMAX1-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
+; LMULMAX1-NEXT:    vmerge.vim v27, v25, -1, v0
+; LMULMAX1-NEXT:    vfcvt.f.x.v v9, v27
+; LMULMAX1-NEXT:    vsetivli zero, 8, e8,mf2,ta,mu
+; LMULMAX1-NEXT:    vmv.v.i v27, 0
+; LMULMAX1-NEXT:    vmv1r.v v0, v29
+; LMULMAX1-NEXT:    vmerge.vim v27, v27, 1, v0
+; LMULMAX1-NEXT:    vsetivli zero, 4, e8,mf2,ta,mu
+; LMULMAX1-NEXT:    vslidedown.vi v27, v27, 4
+; LMULMAX1-NEXT:    vsetivli zero, 4, e8,mf4,ta,mu
+; LMULMAX1-NEXT:    vmsne.vi v0, v27, 0
+; LMULMAX1-NEXT:    vsetivli zero, 2, e64,m1,ta,mu
+; LMULMAX1-NEXT:    vmerge.vim v27, v25, -1, v0
+; LMULMAX1-NEXT:    vfcvt.f.x.v v10, v27
+; LMULMAX1-NEXT:    vsetivli zero, 4, e8,mf4,ta,mu
+; LMULMAX1-NEXT:    vmerge.vim v26, v26, 1, v0
+; LMULMAX1-NEXT:    vsetivli zero, 2, e8,mf4,ta,mu
+; LMULMAX1-NEXT:    vslidedown.vi v26, v26, 2
+; LMULMAX1-NEXT:    vsetivli zero, 2, e8,mf8,ta,mu
+; LMULMAX1-NEXT:    vmsne.vi v0, v26, 0
+; LMULMAX1-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
+; LMULMAX1-NEXT:    vmerge.vim v25, v25, -1, v0
+; LMULMAX1-NEXT:    vfcvt.f.x.v v11, v25
+; LMULMAX1-NEXT:    ret
   %z = sitofp <8 x i1> %x to <8 x double>
   ret <8 x double> %z
 }
 
 define <8 x double> @ui2fp_v8i1_v8f64(<8 x i1> %x) {
-; RV32-LMULMAX8-LABEL: ui2fp_v8i1_v8f64:
-; RV32-LMULMAX8:       # %bb.0:
-; RV32-LMULMAX8-NEXT:    addi sp, sp, -128
-; RV32-LMULMAX8-NEXT:    .cfi_def_cfa_offset 128
-; RV32-LMULMAX8-NEXT:    sw ra, 124(sp) # 4-byte Folded Spill
-; RV32-LMULMAX8-NEXT:    sw s0, 120(sp) # 4-byte Folded Spill
-; RV32-LMULMAX8-NEXT:    .cfi_offset ra, -4
-; RV32-LMULMAX8-NEXT:    .cfi_offset s0, -8
-; RV32-LMULMAX8-NEXT:    addi s0, sp, 128
-; RV32-LMULMAX8-NEXT:    .cfi_def_cfa s0, 0
-; RV32-LMULMAX8-NEXT:    andi sp, sp, -64
-; RV32-LMULMAX8-NEXT:    vsetivli zero, 8, e8,mf2,ta,mu
-; RV32-LMULMAX8-NEXT:    vmv.v.i v25, 0
-; RV32-LMULMAX8-NEXT:    vmerge.vim v25, v25, 1, v0
-; RV32-LMULMAX8-NEXT:    vmv.x.s a0, v25
-; RV32-LMULMAX8-NEXT:    andi a0, a0, 1
-; RV32-LMULMAX8-NEXT:    fcvt.d.wu ft0, a0
-; RV32-LMULMAX8-NEXT:    fsd ft0, 0(sp)
-; RV32-LMULMAX8-NEXT:    vsetivli zero, 1, e8,mf2,ta,mu
-; RV32-LMULMAX8-NEXT:    vslidedown.vi v26, v25, 7
-; RV32-LMULMAX8-NEXT:    vmv.x.s a0, v26
-; RV32-LMULMAX8-NEXT:    andi a0, a0, 1
-; RV32-LMULMAX8-NEXT:    fcvt.d.wu ft0, a0
-; RV32-LMULMAX8-NEXT:    fsd ft0, 56(sp)
-; RV32-LMULMAX8-NEXT:    vslidedown.vi v26, v25, 6
-; RV32-LMULMAX8-NEXT:    vmv.x.s a0, v26
-; RV32-LMULMAX8-NEXT:    andi a0, a0, 1
-; RV32-LMULMAX8-NEXT:    fcvt.d.wu ft0, a0
-; RV32-LMULMAX8-NEXT:    fsd ft0, 48(sp)
-; RV32-LMULMAX8-NEXT:    vslidedown.vi v26, v25, 5
-; RV32-LMULMAX8-NEXT:    vmv.x.s a0, v26
-; RV32-LMULMAX8-NEXT:    andi a0, a0, 1
-; RV32-LMULMAX8-NEXT:    fcvt.d.wu ft0, a0
-; RV32-LMULMAX8-NEXT:    fsd ft0, 40(sp)
-; RV32-LMULMAX8-NEXT:    vslidedown.vi v26, v25, 4
-; RV32-LMULMAX8-NEXT:    vmv.x.s a0, v26
-; RV32-LMULMAX8-NEXT:    andi a0, a0, 1
-; RV32-LMULMAX8-NEXT:    fcvt.d.wu ft0, a0
-; RV32-LMULMAX8-NEXT:    fsd ft0, 32(sp)
-; RV32-LMULMAX8-NEXT:    vslidedown.vi v26, v25, 3
-; RV32-LMULMAX8-NEXT:    vmv.x.s a0, v26
-; RV32-LMULMAX8-NEXT:    andi a0, a0, 1
-; RV32-LMULMAX8-NEXT:    fcvt.d.wu ft0, a0
-; RV32-LMULMAX8-NEXT:    fsd ft0, 24(sp)
-; RV32-LMULMAX8-NEXT:    vslidedown.vi v26, v25, 2
-; RV32-LMULMAX8-NEXT:    vmv.x.s a0, v26
-; RV32-LMULMAX8-NEXT:    andi a0, a0, 1
-; RV32-LMULMAX8-NEXT:    fcvt.d.wu ft0, a0
-; RV32-LMULMAX8-NEXT:    fsd ft0, 16(sp)
-; RV32-LMULMAX8-NEXT:    vslidedown.vi v25, v25, 1
-; RV32-LMULMAX8-NEXT:    vmv.x.s a0, v25
-; RV32-LMULMAX8-NEXT:    andi a0, a0, 1
-; RV32-LMULMAX8-NEXT:    fcvt.d.wu ft0, a0
-; RV32-LMULMAX8-NEXT:    fsd ft0, 8(sp)
-; RV32-LMULMAX8-NEXT:    vsetivli zero, 8, e64,m4,ta,mu
-; RV32-LMULMAX8-NEXT:    vle64.v v8, (sp)
-; RV32-LMULMAX8-NEXT:    addi sp, s0, -128
-; RV32-LMULMAX8-NEXT:    lw s0, 120(sp) # 4-byte Folded Reload
-; RV32-LMULMAX8-NEXT:    lw ra, 124(sp) # 4-byte Folded Reload
-; RV32-LMULMAX8-NEXT:    addi sp, sp, 128
-; RV32-LMULMAX8-NEXT:    ret
-;
-; RV64-LMULMAX8-LABEL: ui2fp_v8i1_v8f64:
-; RV64-LMULMAX8:       # %bb.0:
-; RV64-LMULMAX8-NEXT:    addi sp, sp, -128
-; RV64-LMULMAX8-NEXT:    .cfi_def_cfa_offset 128
-; RV64-LMULMAX8-NEXT:    sd ra, 120(sp) # 8-byte Folded Spill
-; RV64-LMULMAX8-NEXT:    sd s0, 112(sp) # 8-byte Folded Spill
-; RV64-LMULMAX8-NEXT:    .cfi_offset ra, -8
-; RV64-LMULMAX8-NEXT:    .cfi_offset s0, -16
-; RV64-LMULMAX8-NEXT:    addi s0, sp, 128
-; RV64-LMULMAX8-NEXT:    .cfi_def_cfa s0, 0
-; RV64-LMULMAX8-NEXT:    andi sp, sp, -64
-; RV64-LMULMAX8-NEXT:    vsetivli zero, 8, e8,mf2,ta,mu
-; RV64-LMULMAX8-NEXT:    vmv.v.i v25, 0
-; RV64-LMULMAX8-NEXT:    vmerge.vim v25, v25, 1, v0
-; RV64-LMULMAX8-NEXT:    vmv.x.s a0, v25
-; RV64-LMULMAX8-NEXT:    andi a0, a0, 1
-; RV64-LMULMAX8-NEXT:    fcvt.d.lu ft0, a0
-; RV64-LMULMAX8-NEXT:    fsd ft0, 0(sp)
-; RV64-LMULMAX8-NEXT:    vsetivli zero, 1, e8,mf2,ta,mu
-; RV64-LMULMAX8-NEXT:    vslidedown.vi v26, v25, 7
-; RV64-LMULMAX8-NEXT:    vmv.x.s a0, v26
-; RV64-LMULMAX8-NEXT:    andi a0, a0, 1
-; RV64-LMULMAX8-NEXT:    fcvt.d.lu ft0, a0
-; RV64-LMULMAX8-NEXT:    fsd ft0, 56(sp)
-; RV64-LMULMAX8-NEXT:    vslidedown.vi v26, v25, 6
-; RV64-LMULMAX8-NEXT:    vmv.x.s a0, v26
-; RV64-LMULMAX8-NEXT:    andi a0, a0, 1
-; RV64-LMULMAX8-NEXT:    fcvt.d.lu ft0, a0
-; RV64-LMULMAX8-NEXT:    fsd ft0, 48(sp)
-; RV64-LMULMAX8-NEXT:    vslidedown.vi v26, v25, 5
-; RV64-LMULMAX8-NEXT:    vmv.x.s a0, v26
-; RV64-LMULMAX8-NEXT:    andi a0, a0, 1
-; RV64-LMULMAX8-NEXT:    fcvt.d.lu ft0, a0
-; RV64-LMULMAX8-NEXT:    fsd ft0, 40(sp)
-; RV64-LMULMAX8-NEXT:    vslidedown.vi v26, v25, 4
-; RV64-LMULMAX8-NEXT:    vmv.x.s a0, v26
-; RV64-LMULMAX8-NEXT:    andi a0, a0, 1
-; RV64-LMULMAX8-NEXT:    fcvt.d.lu ft0, a0
-; RV64-LMULMAX8-NEXT:    fsd ft0, 32(sp)
-; RV64-LMULMAX8-NEXT:    vslidedown.vi v26, v25, 3
-; RV64-LMULMAX8-NEXT:    vmv.x.s a0, v26
-; RV64-LMULMAX8-NEXT:    andi a0, a0, 1
-; RV64-LMULMAX8-NEXT:    fcvt.d.lu ft0, a0
-; RV64-LMULMAX8-NEXT:    fsd ft0, 24(sp)
-; RV64-LMULMAX8-NEXT:    vslidedown.vi v26, v25, 2
-; RV64-LMULMAX8-NEXT:    vmv.x.s a0, v26
-; RV64-LMULMAX8-NEXT:    andi a0, a0, 1
-; RV64-LMULMAX8-NEXT:    fcvt.d.lu ft0, a0
-; RV64-LMULMAX8-NEXT:    fsd ft0, 16(sp)
-; RV64-LMULMAX8-NEXT:    vslidedown.vi v25, v25, 1
-; RV64-LMULMAX8-NEXT:    vmv.x.s a0, v25
-; RV64-LMULMAX8-NEXT:    andi a0, a0, 1
-; RV64-LMULMAX8-NEXT:    fcvt.d.lu ft0, a0
-; RV64-LMULMAX8-NEXT:    fsd ft0, 8(sp)
-; RV64-LMULMAX8-NEXT:    vsetivli zero, 8, e64,m4,ta,mu
-; RV64-LMULMAX8-NEXT:    vle64.v v8, (sp)
-; RV64-LMULMAX8-NEXT:    addi sp, s0, -128
-; RV64-LMULMAX8-NEXT:    ld s0, 112(sp) # 8-byte Folded Reload
-; RV64-LMULMAX8-NEXT:    ld ra, 120(sp) # 8-byte Folded Reload
-; RV64-LMULMAX8-NEXT:    addi sp, sp, 128
-; RV64-LMULMAX8-NEXT:    ret
-;
-; RV32-LMULMAX1-LABEL: ui2fp_v8i1_v8f64:
-; RV32-LMULMAX1:       # %bb.0:
-; RV32-LMULMAX1-NEXT:    vsetivli zero, 2, e8,mf8,ta,mu
-; RV32-LMULMAX1-NEXT:    vmv.v.i v25, 0
-; RV32-LMULMAX1-NEXT:    vmerge.vim v26, v25, 1, v0
-; RV32-LMULMAX1-NEXT:    vmv.x.s a0, v26
-; RV32-LMULMAX1-NEXT:    andi a0, a0, 1
-; RV32-LMULMAX1-NEXT:    fcvt.d.wu ft0, a0
-; RV32-LMULMAX1-NEXT:    vsetivli zero, 1, e8,mf8,ta,mu
-; RV32-LMULMAX1-NEXT:    vslidedown.vi v26, v26, 1
-; RV32-LMULMAX1-NEXT:    vmv.x.s a0, v26
-; RV32-LMULMAX1-NEXT:    andi a0, a0, 1
-; RV32-LMULMAX1-NEXT:    fcvt.d.wu ft1, a0
-; RV32-LMULMAX1-NEXT:    vsetivli zero, 2, e64,m1,ta,mu
-; RV32-LMULMAX1-NEXT:    vfmv.v.f v8, ft1
-; RV32-LMULMAX1-NEXT:    vfmv.s.f v8, ft0
-; RV32-LMULMAX1-NEXT:    vsetivli zero, 4, e8,mf4,ta,mu
-; RV32-LMULMAX1-NEXT:    vmv.v.i v26, 0
-; RV32-LMULMAX1-NEXT:    vmerge.vim v27, v26, 1, v0
-; RV32-LMULMAX1-NEXT:    vmv1r.v v28, v0
-; RV32-LMULMAX1-NEXT:    vsetivli zero, 2, e8,mf4,ta,mu
-; RV32-LMULMAX1-NEXT:    vslidedown.vi v27, v27, 2
-; RV32-LMULMAX1-NEXT:    vsetivli zero, 2, e8,mf8,ta,mu
-; RV32-LMULMAX1-NEXT:    vmsne.vi v0, v27, 0
-; RV32-LMULMAX1-NEXT:    vmerge.vim v27, v25, 1, v0
-; RV32-LMULMAX1-NEXT:    vmv.x.s a0, v27
-; RV32-LMULMAX1-NEXT:    andi a0, a0, 1
-; RV32-LMULMAX1-NEXT:    fcvt.d.wu ft0, a0
-; RV32-LMULMAX1-NEXT:    vsetivli zero, 1, e8,mf8,ta,mu
-; RV32-LMULMAX1-NEXT:    vslidedown.vi v27, v27, 1
-; RV32-LMULMAX1-NEXT:    vmv.x.s a0, v27
-; RV32-LMULMAX1-NEXT:    andi a0, a0, 1
-; RV32-LMULMAX1-NEXT:    fcvt.d.wu ft1, a0
-; RV32-LMULMAX1-NEXT:    vsetivli zero, 2, e64,m1,ta,mu
-; RV32-LMULMAX1-NEXT:    vfmv.v.f v9, ft1
-; RV32-LMULMAX1-NEXT:    vfmv.s.f v9, ft0
-; RV32-LMULMAX1-NEXT:    vsetivli zero, 8, e8,mf2,ta,mu
-; RV32-LMULMAX1-NEXT:    vmv.v.i v27, 0
-; RV32-LMULMAX1-NEXT:    vmv1r.v v0, v28
-; RV32-LMULMAX1-NEXT:    vmerge.vim v27, v27, 1, v0
-; RV32-LMULMAX1-NEXT:    vsetivli zero, 4, e8,mf2,ta,mu
-; RV32-LMULMAX1-NEXT:    vslidedown.vi v27, v27, 4
-; RV32-LMULMAX1-NEXT:    vsetivli zero, 4, e8,mf4,ta,mu
-; RV32-LMULMAX1-NEXT:    vmsne.vi v0, v27, 0
-; RV32-LMULMAX1-NEXT:    vsetivli zero, 2, e8,mf8,ta,mu
-; RV32-LMULMAX1-NEXT:    vmerge.vim v27, v25, 1, v0
-; RV32-LMULMAX1-NEXT:    vmv.x.s a0, v27
-; RV32-LMULMAX1-NEXT:    andi a0, a0, 1
-; RV32-LMULMAX1-NEXT:    fcvt.d.wu ft0, a0
-; RV32-LMULMAX1-NEXT:    vsetivli zero, 1, e8,mf8,ta,mu
-; RV32-LMULMAX1-NEXT:    vslidedown.vi v27, v27, 1
-; RV32-LMULMAX1-NEXT:    vmv.x.s a0, v27
-; RV32-LMULMAX1-NEXT:    andi a0, a0, 1
-; RV32-LMULMAX1-NEXT:    fcvt.d.wu ft1, a0
-; RV32-LMULMAX1-NEXT:    vsetivli zero, 2, e64,m1,ta,mu
-; RV32-LMULMAX1-NEXT:    vfmv.v.f v10, ft1
-; RV32-LMULMAX1-NEXT:    vfmv.s.f v10, ft0
-; RV32-LMULMAX1-NEXT:    vsetivli zero, 4, e8,mf4,ta,mu
-; RV32-LMULMAX1-NEXT:    vmerge.vim v26, v26, 1, v0
-; RV32-LMULMAX1-NEXT:    vsetivli zero, 2, e8,mf4,ta,mu
-; RV32-LMULMAX1-NEXT:    vslidedown.vi v26, v26, 2
-; RV32-LMULMAX1-NEXT:    vsetivli zero, 2, e8,mf8,ta,mu
-; RV32-LMULMAX1-NEXT:    vmsne.vi v0, v26, 0
-; RV32-LMULMAX1-NEXT:    vmerge.vim v25, v25, 1, v0
-; RV32-LMULMAX1-NEXT:    vmv.x.s a0, v25
-; RV32-LMULMAX1-NEXT:    andi a0, a0, 1
-; RV32-LMULMAX1-NEXT:    fcvt.d.wu ft0, a0
-; RV32-LMULMAX1-NEXT:    vsetivli zero, 1, e8,mf8,ta,mu
-; RV32-LMULMAX1-NEXT:    vslidedown.vi v25, v25, 1
-; RV32-LMULMAX1-NEXT:    vmv.x.s a0, v25
-; RV32-LMULMAX1-NEXT:    andi a0, a0, 1
-; RV32-LMULMAX1-NEXT:    fcvt.d.wu ft1, a0
-; RV32-LMULMAX1-NEXT:    vsetivli zero, 2, e64,m1,ta,mu
-; RV32-LMULMAX1-NEXT:    vfmv.v.f v11, ft1
-; RV32-LMULMAX1-NEXT:    vfmv.s.f v11, ft0
-; RV32-LMULMAX1-NEXT:    ret
+; LMULMAX8-LABEL: ui2fp_v8i1_v8f64:
+; LMULMAX8:       # %bb.0:
+; LMULMAX8-NEXT:    vsetivli zero, 8, e64,m4,ta,mu
+; LMULMAX8-NEXT:    vmv.v.i v28, 0
+; LMULMAX8-NEXT:    vmerge.vim v28, v28, 1, v0
+; LMULMAX8-NEXT:    vfcvt.f.xu.v v8, v28
+; LMULMAX8-NEXT:    ret
 ;
-; RV64-LMULMAX1-LABEL: ui2fp_v8i1_v8f64:
-; RV64-LMULMAX1:       # %bb.0:
-; RV64-LMULMAX1-NEXT:    vsetivli zero, 2, e8,mf8,ta,mu
-; RV64-LMULMAX1-NEXT:    vmv.v.i v25, 0
-; RV64-LMULMAX1-NEXT:    vmerge.vim v26, v25, 1, v0
-; RV64-LMULMAX1-NEXT:    vmv.x.s a0, v26
-; RV64-LMULMAX1-NEXT:    andi a0, a0, 1
-; RV64-LMULMAX1-NEXT:    fcvt.d.lu ft0, a0
-; RV64-LMULMAX1-NEXT:    vsetivli zero, 1, e8,mf8,ta,mu
-; RV64-LMULMAX1-NEXT:    vslidedown.vi v26, v26, 1
-; RV64-LMULMAX1-NEXT:    vmv.x.s a0, v26
-; RV64-LMULMAX1-NEXT:    andi a0, a0, 1
-; RV64-LMULMAX1-NEXT:    fcvt.d.lu ft1, a0
-; RV64-LMULMAX1-NEXT:    vsetivli zero, 2, e64,m1,ta,mu
-; RV64-LMULMAX1-NEXT:    vfmv.v.f v8, ft1
-; RV64-LMULMAX1-NEXT:    vfmv.s.f v8, ft0
-; RV64-LMULMAX1-NEXT:    vsetivli zero, 4, e8,mf4,ta,mu
-; RV64-LMULMAX1-NEXT:    vmv.v.i v26, 0
-; RV64-LMULMAX1-NEXT:    vmerge.vim v27, v26, 1, v0
-; RV64-LMULMAX1-NEXT:    vmv1r.v v28, v0
-; RV64-LMULMAX1-NEXT:    vsetivli zero, 2, e8,mf4,ta,mu
-; RV64-LMULMAX1-NEXT:    vslidedown.vi v27, v27, 2
-; RV64-LMULMAX1-NEXT:    vsetivli zero, 2, e8,mf8,ta,mu
-; RV64-LMULMAX1-NEXT:    vmsne.vi v0, v27, 0
-; RV64-LMULMAX1-NEXT:    vmerge.vim v27, v25, 1, v0
-; RV64-LMULMAX1-NEXT:    vmv.x.s a0, v27
-; RV64-LMULMAX1-NEXT:    andi a0, a0, 1
-; RV64-LMULMAX1-NEXT:    fcvt.d.lu ft0, a0
-; RV64-LMULMAX1-NEXT:    vsetivli zero, 1, e8,mf8,ta,mu
-; RV64-LMULMAX1-NEXT:    vslidedown.vi v27, v27, 1
-; RV64-LMULMAX1-NEXT:    vmv.x.s a0, v27
-; RV64-LMULMAX1-NEXT:    andi a0, a0, 1
-; RV64-LMULMAX1-NEXT:    fcvt.d.lu ft1, a0
-; RV64-LMULMAX1-NEXT:    vsetivli zero, 2, e64,m1,ta,mu
-; RV64-LMULMAX1-NEXT:    vfmv.v.f v9, ft1
-; RV64-LMULMAX1-NEXT:    vfmv.s.f v9, ft0
-; RV64-LMULMAX1-NEXT:    vsetivli zero, 8, e8,mf2,ta,mu
-; RV64-LMULMAX1-NEXT:    vmv.v.i v27, 0
-; RV64-LMULMAX1-NEXT:    vmv1r.v v0, v28
-; RV64-LMULMAX1-NEXT:    vmerge.vim v27, v27, 1, v0
-; RV64-LMULMAX1-NEXT:    vsetivli zero, 4, e8,mf2,ta,mu
-; RV64-LMULMAX1-NEXT:    vslidedown.vi v27, v27, 4
-; RV64-LMULMAX1-NEXT:    vsetivli zero, 4, e8,mf4,ta,mu
-; RV64-LMULMAX1-NEXT:    vmsne.vi v0, v27, 0
-; RV64-LMULMAX1-NEXT:    vsetivli zero, 2, e8,mf8,ta,mu
-; RV64-LMULMAX1-NEXT:    vmerge.vim v27, v25, 1, v0
-; RV64-LMULMAX1-NEXT:    vmv.x.s a0, v27
-; RV64-LMULMAX1-NEXT:    andi a0, a0, 1
-; RV64-LMULMAX1-NEXT:    fcvt.d.lu ft0, a0
-; RV64-LMULMAX1-NEXT:    vsetivli zero, 1, e8,mf8,ta,mu
-; RV64-LMULMAX1-NEXT:    vslidedown.vi v27, v27, 1
-; RV64-LMULMAX1-NEXT:    vmv.x.s a0, v27
-; RV64-LMULMAX1-NEXT:    andi a0, a0, 1
-; RV64-LMULMAX1-NEXT:    fcvt.d.lu ft1, a0
-; RV64-LMULMAX1-NEXT:    vsetivli zero, 2, e64,m1,ta,mu
-; RV64-LMULMAX1-NEXT:    vfmv.v.f v10, ft1
-; RV64-LMULMAX1-NEXT:    vfmv.s.f v10, ft0
-; RV64-LMULMAX1-NEXT:    vsetivli zero, 4, e8,mf4,ta,mu
-; RV64-LMULMAX1-NEXT:    vmerge.vim v26, v26, 1, v0
-; RV64-LMULMAX1-NEXT:    vsetivli zero, 2, e8,mf4,ta,mu
-; RV64-LMULMAX1-NEXT:    vslidedown.vi v26, v26, 2
-; RV64-LMULMAX1-NEXT:    vsetivli zero, 2, e8,mf8,ta,mu
-; RV64-LMULMAX1-NEXT:    vmsne.vi v0, v26, 0
-; RV64-LMULMAX1-NEXT:    vmerge.vim v25, v25, 1, v0
-; RV64-LMULMAX1-NEXT:    vmv.x.s a0, v25
-; RV64-LMULMAX1-NEXT:    andi a0, a0, 1
-; RV64-LMULMAX1-NEXT:    fcvt.d.lu ft0, a0
-; RV64-LMULMAX1-NEXT:    vsetivli zero, 1, e8,mf8,ta,mu
-; RV64-LMULMAX1-NEXT:    vslidedown.vi v25, v25, 1
-; RV64-LMULMAX1-NEXT:    vmv.x.s a0, v25
-; RV64-LMULMAX1-NEXT:    andi a0, a0, 1
-; RV64-LMULMAX1-NEXT:    fcvt.d.lu ft1, a0
-; RV64-LMULMAX1-NEXT:    vsetivli zero, 2, e64,m1,ta,mu
-; RV64-LMULMAX1-NEXT:    vfmv.v.f v11, ft1
-; RV64-LMULMAX1-NEXT:    vfmv.s.f v11, ft0
-; RV64-LMULMAX1-NEXT:    ret
+; LMULMAX1-LABEL: ui2fp_v8i1_v8f64:
+; LMULMAX1:       # %bb.0:
+; LMULMAX1-NEXT:    vsetivli zero, 2, e64,m1,ta,mu
+; LMULMAX1-NEXT:    vmv.v.i v25, 0
+; LMULMAX1-NEXT:    vmerge.vim v26, v25, 1, v0
+; LMULMAX1-NEXT:    vfcvt.f.xu.v v8, v26
+; LMULMAX1-NEXT:    vsetivli zero, 4, e8,mf4,ta,mu
+; LMULMAX1-NEXT:    vmv.v.i v26, 0
+; LMULMAX1-NEXT:    vmerge.vim v27, v26, 1, v0
+; LMULMAX1-NEXT:    vmv1r.v v29, v0
+; LMULMAX1-NEXT:    vsetivli zero, 2, e8,mf4,ta,mu
+; LMULMAX1-NEXT:    vslidedown.vi v27, v27, 2
+; LMULMAX1-NEXT:    vsetivli zero, 2, e8,mf8,ta,mu
+; LMULMAX1-NEXT:    vmsne.vi v0, v27, 0
+; LMULMAX1-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
+; LMULMAX1-NEXT:    vmerge.vim v27, v25, 1, v0
+; LMULMAX1-NEXT:    vfcvt.f.xu.v v9, v27
+; LMULMAX1-NEXT:    vsetivli zero, 8, e8,mf2,ta,mu
+; LMULMAX1-NEXT:    vmv.v.i v27, 0
+; LMULMAX1-NEXT:    vmv1r.v v0, v29
+; LMULMAX1-NEXT:    vmerge.vim v27, v27, 1, v0
+; LMULMAX1-NEXT:    vsetivli zero, 4, e8,mf2,ta,mu
+; LMULMAX1-NEXT:    vslidedown.vi v27, v27, 4
+; LMULMAX1-NEXT:    vsetivli zero, 4, e8,mf4,ta,mu
+; LMULMAX1-NEXT:    vmsne.vi v0, v27, 0
+; LMULMAX1-NEXT:    vsetivli zero, 2, e64,m1,ta,mu
+; LMULMAX1-NEXT:    vmerge.vim v27, v25, 1, v0
+; LMULMAX1-NEXT:    vfcvt.f.xu.v v10, v27
+; LMULMAX1-NEXT:    vsetivli zero, 4, e8,mf4,ta,mu
+; LMULMAX1-NEXT:    vmerge.vim v26, v26, 1, v0
+; LMULMAX1-NEXT:    vsetivli zero, 2, e8,mf4,ta,mu
+; LMULMAX1-NEXT:    vslidedown.vi v26, v26, 2
+; LMULMAX1-NEXT:    vsetivli zero, 2, e8,mf8,ta,mu
+; LMULMAX1-NEXT:    vmsne.vi v0, v26, 0
+; LMULMAX1-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
+; LMULMAX1-NEXT:    vmerge.vim v25, v25, 1, v0
+; LMULMAX1-NEXT:    vfcvt.f.xu.v v11, v25
+; LMULMAX1-NEXT:    ret
   %z = uitofp <8 x i1> %x to <8 x double>
   ret <8 x double> %z
 }
@@ -1459,85 +429,25 @@ define void @ui2fp_v2i64_v2f16(<2 x i64>* %x, <2 x half>* %y) {
 }
 
 define <2 x half> @si2fp_v2i1_v2f16(<2 x i1> %x) {
-; RV32-LABEL: si2fp_v2i1_v2f16:
-; RV32:       # %bb.0:
-; RV32-NEXT:    vsetivli zero, 2, e8,mf8,ta,mu
-; RV32-NEXT:    vmv.v.i v25, 0
-; RV32-NEXT:    vmerge.vim v25, v25, 1, v0
-; RV32-NEXT:    vmv.x.s a0, v25
-; RV32-NEXT:    andi a0, a0, 1
-; RV32-NEXT:    neg a0, a0
-; RV32-NEXT:    fcvt.h.w ft0, a0
-; RV32-NEXT:    vsetivli zero, 1, e8,mf8,ta,mu
-; RV32-NEXT:    vslidedown.vi v25, v25, 1
-; RV32-NEXT:    vmv.x.s a0, v25
-; RV32-NEXT:    andi a0, a0, 1
-; RV32-NEXT:    neg a0, a0
-; RV32-NEXT:    fcvt.h.w ft1, a0
-; RV32-NEXT:    vsetivli zero, 2, e16,mf4,ta,mu
-; RV32-NEXT:    vfmv.v.f v8, ft1
-; RV32-NEXT:    vfmv.s.f v8, ft0
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: si2fp_v2i1_v2f16:
-; RV64:       # %bb.0:
-; RV64-NEXT:    vsetivli zero, 2, e8,mf8,ta,mu
-; RV64-NEXT:    vmv.v.i v25, 0
-; RV64-NEXT:    vmerge.vim v25, v25, 1, v0
-; RV64-NEXT:    vmv.x.s a0, v25
-; RV64-NEXT:    andi a0, a0, 1
-; RV64-NEXT:    neg a0, a0
-; RV64-NEXT:    fcvt.h.l ft0, a0
-; RV64-NEXT:    vsetivli zero, 1, e8,mf8,ta,mu
-; RV64-NEXT:    vslidedown.vi v25, v25, 1
-; RV64-NEXT:    vmv.x.s a0, v25
-; RV64-NEXT:    andi a0, a0, 1
-; RV64-NEXT:    neg a0, a0
-; RV64-NEXT:    fcvt.h.l ft1, a0
-; RV64-NEXT:    vsetivli zero, 2, e16,mf4,ta,mu
-; RV64-NEXT:    vfmv.v.f v8, ft1
-; RV64-NEXT:    vfmv.s.f v8, ft0
-; RV64-NEXT:    ret
+; CHECK-LABEL: si2fp_v2i1_v2f16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 2, e16,mf4,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, 0
+; CHECK-NEXT:    vmerge.vim v25, v25, -1, v0
+; CHECK-NEXT:    vfcvt.f.x.v v8, v25
+; CHECK-NEXT:    ret
   %z = sitofp <2 x i1> %x to <2 x half>
   ret <2 x half> %z
 }
 
 define <2 x half> @ui2fp_v2i1_v2f16(<2 x i1> %x) {
-; RV32-LABEL: ui2fp_v2i1_v2f16:
-; RV32:       # %bb.0:
-; RV32-NEXT:    vsetivli zero, 2, e8,mf8,ta,mu
-; RV32-NEXT:    vmv.v.i v25, 0
-; RV32-NEXT:    vmerge.vim v25, v25, 1, v0
-; RV32-NEXT:    vmv.x.s a0, v25
-; RV32-NEXT:    andi a0, a0, 1
-; RV32-NEXT:    fcvt.h.wu ft0, a0
-; RV32-NEXT:    vsetivli zero, 1, e8,mf8,ta,mu
-; RV32-NEXT:    vslidedown.vi v25, v25, 1
-; RV32-NEXT:    vmv.x.s a0, v25
-; RV32-NEXT:    andi a0, a0, 1
-; RV32-NEXT:    fcvt.h.wu ft1, a0
-; RV32-NEXT:    vsetivli zero, 2, e16,mf4,ta,mu
-; RV32-NEXT:    vfmv.v.f v8, ft1
-; RV32-NEXT:    vfmv.s.f v8, ft0
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: ui2fp_v2i1_v2f16:
-; RV64:       # %bb.0:
-; RV64-NEXT:    vsetivli zero, 2, e8,mf8,ta,mu
-; RV64-NEXT:    vmv.v.i v25, 0
-; RV64-NEXT:    vmerge.vim v25, v25, 1, v0
-; RV64-NEXT:    vmv.x.s a0, v25
-; RV64-NEXT:    andi a0, a0, 1
-; RV64-NEXT:    fcvt.h.lu ft0, a0
-; RV64-NEXT:    vsetivli zero, 1, e8,mf8,ta,mu
-; RV64-NEXT:    vslidedown.vi v25, v25, 1
-; RV64-NEXT:    vmv.x.s a0, v25
-; RV64-NEXT:    andi a0, a0, 1
-; RV64-NEXT:    fcvt.h.lu ft1, a0
-; RV64-NEXT:    vsetivli zero, 2, e16,mf4,ta,mu
-; RV64-NEXT:    vfmv.v.f v8, ft1
-; RV64-NEXT:    vfmv.s.f v8, ft0
-; RV64-NEXT:    ret
+; CHECK-LABEL: ui2fp_v2i1_v2f16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 2, e16,mf4,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, 0
+; CHECK-NEXT:    vmerge.vim v25, v25, 1, v0
+; CHECK-NEXT:    vfcvt.f.xu.v v8, v25
+; CHECK-NEXT:    ret
   %z = uitofp <2 x i1> %x to <2 x half>
   ret <2 x half> %z
 }
@@ -1679,233 +589,25 @@ define void @ui2fp_v8i64_v8f16(<8 x i64>* %x, <8 x half>* %y) {
 }
 
 define <8 x half> @si2fp_v8i1_v8f16(<8 x i1> %x) {
-; RV32-LABEL: si2fp_v8i1_v8f16:
-; RV32:       # %bb.0:
-; RV32-NEXT:    addi sp, sp, -16
-; RV32-NEXT:    .cfi_def_cfa_offset 16
-; RV32-NEXT:    vsetivli zero, 8, e8,mf2,ta,mu
-; RV32-NEXT:    vmv.v.i v25, 0
-; RV32-NEXT:    vmerge.vim v25, v25, 1, v0
-; RV32-NEXT:    vmv.x.s a0, v25
-; RV32-NEXT:    andi a0, a0, 1
-; RV32-NEXT:    neg a0, a0
-; RV32-NEXT:    fcvt.h.w ft0, a0
-; RV32-NEXT:    fsh ft0, 0(sp)
-; RV32-NEXT:    vsetivli zero, 1, e8,mf2,ta,mu
-; RV32-NEXT:    vslidedown.vi v26, v25, 7
-; RV32-NEXT:    vmv.x.s a0, v26
-; RV32-NEXT:    andi a0, a0, 1
-; RV32-NEXT:    neg a0, a0
-; RV32-NEXT:    fcvt.h.w ft0, a0
-; RV32-NEXT:    fsh ft0, 14(sp)
-; RV32-NEXT:    vslidedown.vi v26, v25, 6
-; RV32-NEXT:    vmv.x.s a0, v26
-; RV32-NEXT:    andi a0, a0, 1
-; RV32-NEXT:    neg a0, a0
-; RV32-NEXT:    fcvt.h.w ft0, a0
-; RV32-NEXT:    fsh ft0, 12(sp)
-; RV32-NEXT:    vslidedown.vi v26, v25, 5
-; RV32-NEXT:    vmv.x.s a0, v26
-; RV32-NEXT:    andi a0, a0, 1
-; RV32-NEXT:    neg a0, a0
-; RV32-NEXT:    fcvt.h.w ft0, a0
-; RV32-NEXT:    fsh ft0, 10(sp)
-; RV32-NEXT:    vslidedown.vi v26, v25, 4
-; RV32-NEXT:    vmv.x.s a0, v26
-; RV32-NEXT:    andi a0, a0, 1
-; RV32-NEXT:    neg a0, a0
-; RV32-NEXT:    fcvt.h.w ft0, a0
-; RV32-NEXT:    fsh ft0, 8(sp)
-; RV32-NEXT:    vslidedown.vi v26, v25, 3
-; RV32-NEXT:    vmv.x.s a0, v26
-; RV32-NEXT:    andi a0, a0, 1
-; RV32-NEXT:    neg a0, a0
-; RV32-NEXT:    fcvt.h.w ft0, a0
-; RV32-NEXT:    fsh ft0, 6(sp)
-; RV32-NEXT:    vslidedown.vi v26, v25, 2
-; RV32-NEXT:    vmv.x.s a0, v26
-; RV32-NEXT:    andi a0, a0, 1
-; RV32-NEXT:    neg a0, a0
-; RV32-NEXT:    fcvt.h.w ft0, a0
-; RV32-NEXT:    fsh ft0, 4(sp)
-; RV32-NEXT:    vslidedown.vi v25, v25, 1
-; RV32-NEXT:    vmv.x.s a0, v25
-; RV32-NEXT:    andi a0, a0, 1
-; RV32-NEXT:    neg a0, a0
-; RV32-NEXT:    fcvt.h.w ft0, a0
-; RV32-NEXT:    fsh ft0, 2(sp)
-; RV32-NEXT:    vsetivli zero, 8, e16,m1,ta,mu
-; RV32-NEXT:    vle16.v v8, (sp)
-; RV32-NEXT:    addi sp, sp, 16
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: si2fp_v8i1_v8f16:
-; RV64:       # %bb.0:
-; RV64-NEXT:    addi sp, sp, -16
-; RV64-NEXT:    .cfi_def_cfa_offset 16
-; RV64-NEXT:    vsetivli zero, 8, e8,mf2,ta,mu
-; RV64-NEXT:    vmv.v.i v25, 0
-; RV64-NEXT:    vmerge.vim v25, v25, 1, v0
-; RV64-NEXT:    vmv.x.s a0, v25
-; RV64-NEXT:    andi a0, a0, 1
-; RV64-NEXT:    neg a0, a0
-; RV64-NEXT:    fcvt.h.l ft0, a0
-; RV64-NEXT:    fsh ft0, 0(sp)
-; RV64-NEXT:    vsetivli zero, 1, e8,mf2,ta,mu
-; RV64-NEXT:    vslidedown.vi v26, v25, 7
-; RV64-NEXT:    vmv.x.s a0, v26
-; RV64-NEXT:    andi a0, a0, 1
-; RV64-NEXT:    neg a0, a0
-; RV64-NEXT:    fcvt.h.l ft0, a0
-; RV64-NEXT:    fsh ft0, 14(sp)
-; RV64-NEXT:    vslidedown.vi v26, v25, 6
-; RV64-NEXT:    vmv.x.s a0, v26
-; RV64-NEXT:    andi a0, a0, 1
-; RV64-NEXT:    neg a0, a0
-; RV64-NEXT:    fcvt.h.l ft0, a0
-; RV64-NEXT:    fsh ft0, 12(sp)
-; RV64-NEXT:    vslidedown.vi v26, v25, 5
-; RV64-NEXT:    vmv.x.s a0, v26
-; RV64-NEXT:    andi a0, a0, 1
-; RV64-NEXT:    neg a0, a0
-; RV64-NEXT:    fcvt.h.l ft0, a0
-; RV64-NEXT:    fsh ft0, 10(sp)
-; RV64-NEXT:    vslidedown.vi v26, v25, 4
-; RV64-NEXT:    vmv.x.s a0, v26
-; RV64-NEXT:    andi a0, a0, 1
-; RV64-NEXT:    neg a0, a0
-; RV64-NEXT:    fcvt.h.l ft0, a0
-; RV64-NEXT:    fsh ft0, 8(sp)
-; RV64-NEXT:    vslidedown.vi v26, v25, 3
-; RV64-NEXT:    vmv.x.s a0, v26
-; RV64-NEXT:    andi a0, a0, 1
-; RV64-NEXT:    neg a0, a0
-; RV64-NEXT:    fcvt.h.l ft0, a0
-; RV64-NEXT:    fsh ft0, 6(sp)
-; RV64-NEXT:    vslidedown.vi v26, v25, 2
-; RV64-NEXT:    vmv.x.s a0, v26
-; RV64-NEXT:    andi a0, a0, 1
-; RV64-NEXT:    neg a0, a0
-; RV64-NEXT:    fcvt.h.l ft0, a0
-; RV64-NEXT:    fsh ft0, 4(sp)
-; RV64-NEXT:    vslidedown.vi v25, v25, 1
-; RV64-NEXT:    vmv.x.s a0, v25
-; RV64-NEXT:    andi a0, a0, 1
-; RV64-NEXT:    neg a0, a0
-; RV64-NEXT:    fcvt.h.l ft0, a0
-; RV64-NEXT:    fsh ft0, 2(sp)
-; RV64-NEXT:    vsetivli zero, 8, e16,m1,ta,mu
-; RV64-NEXT:    vle16.v v8, (sp)
-; RV64-NEXT:    addi sp, sp, 16
-; RV64-NEXT:    ret
+; CHECK-LABEL: si2fp_v8i1_v8f16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 8, e16,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, 0
+; CHECK-NEXT:    vmerge.vim v25, v25, -1, v0
+; CHECK-NEXT:    vfcvt.f.x.v v8, v25
+; CHECK-NEXT:    ret
   %z = sitofp <8 x i1> %x to <8 x half>
   ret <8 x half> %z
 }
 
 define <8 x half> @ui2fp_v8i1_v8f16(<8 x i1> %x) {
-; RV32-LABEL: ui2fp_v8i1_v8f16:
-; RV32:       # %bb.0:
-; RV32-NEXT:    addi sp, sp, -16
-; RV32-NEXT:    .cfi_def_cfa_offset 16
-; RV32-NEXT:    vsetivli zero, 8, e8,mf2,ta,mu
-; RV32-NEXT:    vmv.v.i v25, 0
-; RV32-NEXT:    vmerge.vim v25, v25, 1, v0
-; RV32-NEXT:    vmv.x.s a0, v25
-; RV32-NEXT:    andi a0, a0, 1
-; RV32-NEXT:    fcvt.h.wu ft0, a0
-; RV32-NEXT:    fsh ft0, 0(sp)
-; RV32-NEXT:    vsetivli zero, 1, e8,mf2,ta,mu
-; RV32-NEXT:    vslidedown.vi v26, v25, 7
-; RV32-NEXT:    vmv.x.s a0, v26
-; RV32-NEXT:    andi a0, a0, 1
-; RV32-NEXT:    fcvt.h.wu ft0, a0
-; RV32-NEXT:    fsh ft0, 14(sp)
-; RV32-NEXT:    vslidedown.vi v26, v25, 6
-; RV32-NEXT:    vmv.x.s a0, v26
-; RV32-NEXT:    andi a0, a0, 1
-; RV32-NEXT:    fcvt.h.wu ft0, a0
-; RV32-NEXT:    fsh ft0, 12(sp)
-; RV32-NEXT:    vslidedown.vi v26, v25, 5
-; RV32-NEXT:    vmv.x.s a0, v26
-; RV32-NEXT:    andi a0, a0, 1
-; RV32-NEXT:    fcvt.h.wu ft0, a0
-; RV32-NEXT:    fsh ft0, 10(sp)
-; RV32-NEXT:    vslidedown.vi v26, v25, 4
-; RV32-NEXT:    vmv.x.s a0, v26
-; RV32-NEXT:    andi a0, a0, 1
-; RV32-NEXT:    fcvt.h.wu ft0, a0
-; RV32-NEXT:    fsh ft0, 8(sp)
-; RV32-NEXT:    vslidedown.vi v26, v25, 3
-; RV32-NEXT:    vmv.x.s a0, v26
-; RV32-NEXT:    andi a0, a0, 1
-; RV32-NEXT:    fcvt.h.wu ft0, a0
-; RV32-NEXT:    fsh ft0, 6(sp)
-; RV32-NEXT:    vslidedown.vi v26, v25, 2
-; RV32-NEXT:    vmv.x.s a0, v26
-; RV32-NEXT:    andi a0, a0, 1
-; RV32-NEXT:    fcvt.h.wu ft0, a0
-; RV32-NEXT:    fsh ft0, 4(sp)
-; RV32-NEXT:    vslidedown.vi v25, v25, 1
-; RV32-NEXT:    vmv.x.s a0, v25
-; RV32-NEXT:    andi a0, a0, 1
-; RV32-NEXT:    fcvt.h.wu ft0, a0
-; RV32-NEXT:    fsh ft0, 2(sp)
-; RV32-NEXT:    vsetivli zero, 8, e16,m1,ta,mu
-; RV32-NEXT:    vle16.v v8, (sp)
-; RV32-NEXT:    addi sp, sp, 16
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: ui2fp_v8i1_v8f16:
-; RV64:       # %bb.0:
-; RV64-NEXT:    addi sp, sp, -16
-; RV64-NEXT:    .cfi_def_cfa_offset 16
-; RV64-NEXT:    vsetivli zero, 8, e8,mf2,ta,mu
-; RV64-NEXT:    vmv.v.i v25, 0
-; RV64-NEXT:    vmerge.vim v25, v25, 1, v0
-; RV64-NEXT:    vmv.x.s a0, v25
-; RV64-NEXT:    andi a0, a0, 1
-; RV64-NEXT:    fcvt.h.lu ft0, a0
-; RV64-NEXT:    fsh ft0, 0(sp)
-; RV64-NEXT:    vsetivli zero, 1, e8,mf2,ta,mu
-; RV64-NEXT:    vslidedown.vi v26, v25, 7
-; RV64-NEXT:    vmv.x.s a0, v26
-; RV64-NEXT:    andi a0, a0, 1
-; RV64-NEXT:    fcvt.h.lu ft0, a0
-; RV64-NEXT:    fsh ft0, 14(sp)
-; RV64-NEXT:    vslidedown.vi v26, v25, 6
-; RV64-NEXT:    vmv.x.s a0, v26
-; RV64-NEXT:    andi a0, a0, 1
-; RV64-NEXT:    fcvt.h.lu ft0, a0
-; RV64-NEXT:    fsh ft0, 12(sp)
-; RV64-NEXT:    vslidedown.vi v26, v25, 5
-; RV64-NEXT:    vmv.x.s a0, v26
-; RV64-NEXT:    andi a0, a0, 1
-; RV64-NEXT:    fcvt.h.lu ft0, a0
-; RV64-NEXT:    fsh ft0, 10(sp)
-; RV64-NEXT:    vslidedown.vi v26, v25, 4
-; RV64-NEXT:    vmv.x.s a0, v26
-; RV64-NEXT:    andi a0, a0, 1
-; RV64-NEXT:    fcvt.h.lu ft0, a0
-; RV64-NEXT:    fsh ft0, 8(sp)
-; RV64-NEXT:    vslidedown.vi v26, v25, 3
-; RV64-NEXT:    vmv.x.s a0, v26
-; RV64-NEXT:    andi a0, a0, 1
-; RV64-NEXT:    fcvt.h.lu ft0, a0
-; RV64-NEXT:    fsh ft0, 6(sp)
-; RV64-NEXT:    vslidedown.vi v26, v25, 2
-; RV64-NEXT:    vmv.x.s a0, v26
-; RV64-NEXT:    andi a0, a0, 1
-; RV64-NEXT:    fcvt.h.lu ft0, a0
-; RV64-NEXT:    fsh ft0, 4(sp)
-; RV64-NEXT:    vslidedown.vi v25, v25, 1
-; RV64-NEXT:    vmv.x.s a0, v25
-; RV64-NEXT:    andi a0, a0, 1
-; RV64-NEXT:    fcvt.h.lu ft0, a0
-; RV64-NEXT:    fsh ft0, 2(sp)
-; RV64-NEXT:    vsetivli zero, 8, e16,m1,ta,mu
-; RV64-NEXT:    vle16.v v8, (sp)
-; RV64-NEXT:    addi sp, sp, 16
-; RV64-NEXT:    ret
+; CHECK-LABEL: ui2fp_v8i1_v8f16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 8, e16,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, 0
+; CHECK-NEXT:    vmerge.vim v25, v25, 1, v0
+; CHECK-NEXT:    vfcvt.f.xu.v v8, v25
+; CHECK-NEXT:    ret
   %z = uitofp <8 x i1> %x to <8 x half>
   ret <8 x half> %z
 }
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfptoi-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vfptoi-sdnode.ll
index f7bd2f1..3042ed4 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vfptoi-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vfptoi-sdnode.ll
@@ -4,6 +4,30 @@
 ; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-zfh,+experimental-v -target-abi=lp64d \
 ; RUN:     -verify-machineinstrs < %s | FileCheck %s
 
+define <vscale x 1 x i1> @vfptosi_nxv1f16_nxv1i1(<vscale x 1 x half> %va) {
+; CHECK-LABEL: vfptosi_nxv1f16_nxv1i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf8,ta,mu
+; CHECK-NEXT:    vfncvt.rtz.x.f.w v25, v8
+; CHECK-NEXT:    vand.vi v25, v25, 1
+; CHECK-NEXT:    vmsne.vi v0, v25, 0
+; CHECK-NEXT:    ret
+  %evec = fptosi <vscale x 1 x half> %va to <vscale x 1 x i1>
+  ret <vscale x 1 x i1> %evec
+}
+
+define <vscale x 1 x i1> @vfptoui_nxv1f16_nxv1i1(<vscale x 1 x half> %va) {
+; CHECK-LABEL: vfptoui_nxv1f16_nxv1i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf8,ta,mu
+; CHECK-NEXT:    vfncvt.rtz.xu.f.w v25, v8
+; CHECK-NEXT:    vand.vi v25, v25, 1
+; CHECK-NEXT:    vmsne.vi v0, v25, 0
+; CHECK-NEXT:    ret
+  %evec = fptoui <vscale x 1 x half> %va to <vscale x 1 x i1>
+  ret <vscale x 1 x i1> %evec
+}
+
 define <vscale x 1 x i8> @vfptosi_nxv1f16_nxv1i8(<vscale x 1 x half> %va) {
 ; CHECK-LABEL: vfptosi_nxv1f16_nxv1i8:
 ; CHECK:       # %bb.0:
@@ -92,6 +116,30 @@ define <vscale x 1 x i64> @vfptoui_nxv1f16_nxv1i64(<vscale x 1 x half> %va) {
   ret <vscale x 1 x i64> %evec
 }
 
+define <vscale x 2 x i1> @vfptosi_nxv2f16_nxv2i1(<vscale x 2 x half> %va) {
+; CHECK-LABEL: vfptosi_nxv2f16_nxv2i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf4,ta,mu
+; CHECK-NEXT:    vfncvt.rtz.x.f.w v25, v8
+; CHECK-NEXT:    vand.vi v25, v25, 1
+; CHECK-NEXT:    vmsne.vi v0, v25, 0
+; CHECK-NEXT:    ret
+  %evec = fptosi <vscale x 2 x half> %va to <vscale x 2 x i1>
+  ret <vscale x 2 x i1> %evec
+}
+
+define <vscale x 2 x i1> @vfptoui_nxv2f16_nxv2i1(<vscale x 2 x half> %va) {
+; CHECK-LABEL: vfptoui_nxv2f16_nxv2i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf4,ta,mu
+; CHECK-NEXT:    vfncvt.rtz.xu.f.w v25, v8
+; CHECK-NEXT:    vand.vi v25, v25, 1
+; CHECK-NEXT:    vmsne.vi v0, v25, 0
+; CHECK-NEXT:    ret
+  %evec = fptoui <vscale x 2 x half> %va to <vscale x 2 x i1>
+  ret <vscale x 2 x i1> %evec
+}
+
 define <vscale x 2 x i8> @vfptosi_nxv2f16_nxv2i8(<vscale x 2 x half> %va) {
 ; CHECK-LABEL: vfptosi_nxv2f16_nxv2i8:
 ; CHECK:       # %bb.0:
@@ -180,6 +228,30 @@ define <vscale x 2 x i64> @vfptoui_nxv2f16_nxv2i64(<vscale x 2 x half> %va) {
   ret <vscale x 2 x i64> %evec
 }
 
+define <vscale x 4 x i1> @vfptosi_nxv4f16_nxv4i1(<vscale x 4 x half> %va) {
+; CHECK-LABEL: vfptosi_nxv4f16_nxv4i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf2,ta,mu
+; CHECK-NEXT:    vfncvt.rtz.x.f.w v25, v8
+; CHECK-NEXT:    vand.vi v25, v25, 1
+; CHECK-NEXT:    vmsne.vi v0, v25, 0
+; CHECK-NEXT:    ret
+  %evec = fptosi <vscale x 4 x half> %va to <vscale x 4 x i1>
+  ret <vscale x 4 x i1> %evec
+}
+
+define <vscale x 4 x i1> @vfptoui_nxv4f16_nxv4i1(<vscale x 4 x half> %va) {
+; CHECK-LABEL: vfptoui_nxv4f16_nxv4i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf2,ta,mu
+; CHECK-NEXT:    vfncvt.rtz.xu.f.w v25, v8
+; CHECK-NEXT:    vand.vi v25, v25, 1
+; CHECK-NEXT:    vmsne.vi v0, v25, 0
+; CHECK-NEXT:    ret
+  %evec = fptoui <vscale x 4 x half> %va to <vscale x 4 x i1>
+  ret <vscale x 4 x i1> %evec
+}
+
 define <vscale x 4 x i8> @vfptosi_nxv4f16_nxv4i8(<vscale x 4 x half> %va) {
 ; CHECK-LABEL: vfptosi_nxv4f16_nxv4i8:
 ; CHECK:       # %bb.0:
@@ -268,6 +340,30 @@ define <vscale x 4 x i64> @vfptoui_nxv4f16_nxv4i64(<vscale x 4 x half> %va) {
   ret <vscale x 4 x i64> %evec
 }
 
+define <vscale x 8 x i1> @vfptosi_nxv8f16_nxv8i1(<vscale x 8 x half> %va) {
+; CHECK-LABEL: vfptosi_nxv8f16_nxv8i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vfncvt.rtz.x.f.w v25, v8
+; CHECK-NEXT:    vand.vi v25, v25, 1
+; CHECK-NEXT:    vmsne.vi v0, v25, 0
+; CHECK-NEXT:    ret
+  %evec = fptosi <vscale x 8 x half> %va to <vscale x 8 x i1>
+  ret <vscale x 8 x i1> %evec
+}
+
+define <vscale x 8 x i1> @vfptoui_nxv8f16_nxv8i1(<vscale x 8 x half> %va) {
+; CHECK-LABEL: vfptoui_nxv8f16_nxv8i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vfncvt.rtz.xu.f.w v25, v8
+; CHECK-NEXT:    vand.vi v25, v25, 1
+; CHECK-NEXT:    vmsne.vi v0, v25, 0
+; CHECK-NEXT:    ret
+  %evec = fptoui <vscale x 8 x half> %va to <vscale x 8 x i1>
+  ret <vscale x 8 x i1> %evec
+}
+
 define <vscale x 8 x i8> @vfptosi_nxv8f16_nxv8i8(<vscale x 8 x half> %va) {
 ; CHECK-LABEL: vfptosi_nxv8f16_nxv8i8:
 ; CHECK:       # %bb.0:
@@ -356,6 +452,30 @@ define <vscale x 8 x i64> @vfptoui_nxv8f16_nxv8i64(<vscale x 8 x half> %va) {
   ret <vscale x 8 x i64> %evec
 }
 
+define <vscale x 16 x i1> @vfptosi_nxv16f16_nxv16i1(<vscale x 16 x half> %va) {
+; CHECK-LABEL: vfptosi_nxv16f16_nxv16i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m2,ta,mu
+; CHECK-NEXT:    vfncvt.rtz.x.f.w v26, v8
+; CHECK-NEXT:    vand.vi v26, v26, 1
+; CHECK-NEXT:    vmsne.vi v0, v26, 0
+; CHECK-NEXT:    ret
+  %evec = fptosi <vscale x 16 x half> %va to <vscale x 16 x i1>
+  ret <vscale x 16 x i1> %evec
+}
+
+define <vscale x 16 x i1> @vfptoui_nxv16f16_nxv16i1(<vscale x 16 x half> %va) {
+; CHECK-LABEL: vfptoui_nxv16f16_nxv16i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m2,ta,mu
+; CHECK-NEXT:    vfncvt.rtz.xu.f.w v26, v8
+; CHECK-NEXT:    vand.vi v26, v26, 1
+; CHECK-NEXT:    vmsne.vi v0, v26, 0
+; CHECK-NEXT:    ret
+  %evec = fptoui <vscale x 16 x half> %va to <vscale x 16 x i1>
+  ret <vscale x 16 x i1> %evec
+}
+
 define <vscale x 16 x i8> @vfptosi_nxv16f16_nxv16i8(<vscale x 16 x half> %va) {
 ; CHECK-LABEL: vfptosi_nxv16f16_nxv16i8:
 ; CHECK:       # %bb.0:
@@ -420,6 +540,30 @@ define <vscale x 16 x i32> @vfptoui_nxv16f16_nxv16i32(<vscale x 16 x half> %va)
   ret <vscale x 16 x i32> %evec
 }
 
+define <vscale x 32 x i1> @vfptosi_nxv32f16_nxv32i1(<vscale x 32 x half> %va) {
+; CHECK-LABEL: vfptosi_nxv32f16_nxv32i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m4,ta,mu
+; CHECK-NEXT:    vfncvt.rtz.x.f.w v28, v8
+; CHECK-NEXT:    vand.vi v28, v28, 1
+; CHECK-NEXT:    vmsne.vi v0, v28, 0
+; CHECK-NEXT:    ret
+  %evec = fptosi <vscale x 32 x half> %va to <vscale x 32 x i1>
+  ret <vscale x 32 x i1> %evec
+}
+
+define <vscale x 32 x i1> @vfptoui_nxv32f16_nxv32i1(<vscale x 32 x half> %va) {
+; CHECK-LABEL: vfptoui_nxv32f16_nxv32i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m4,ta,mu
+; CHECK-NEXT:    vfncvt.rtz.xu.f.w v28, v8
+; CHECK-NEXT:    vand.vi v28, v28, 1
+; CHECK-NEXT:    vmsne.vi v0, v28, 0
+; CHECK-NEXT:    ret
+  %evec = fptoui <vscale x 32 x half> %va to <vscale x 32 x i1>
+  ret <vscale x 32 x i1> %evec
+}
+
 define <vscale x 32 x i8> @vfptosi_nxv32f16_nxv32i8(<vscale x 32 x half> %va) {
 ; CHECK-LABEL: vfptosi_nxv32f16_nxv32i8:
 ; CHECK:       # %bb.0:
@@ -462,6 +606,30 @@ define <vscale x 32 x i16> @vfptoui_nxv32f16_nxv32i16(<vscale x 32 x half> %va)
   ret <vscale x 32 x i16> %evec
 }
 
+define <vscale x 1 x i1> @vfptosi_nxv1f32_nxv1i1(<vscale x 1 x float> %va) {
+; CHECK-LABEL: vfptosi_nxv1f32_nxv1i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,mf4,ta,mu
+; CHECK-NEXT:    vfncvt.rtz.x.f.w v25, v8
+; CHECK-NEXT:    vand.vi v25, v25, 1
+; CHECK-NEXT:    vmsne.vi v0, v25, 0
+; CHECK-NEXT:    ret
+  %evec = fptosi <vscale x 1 x float> %va to <vscale x 1 x i1>
+  ret <vscale x 1 x i1> %evec
+}
+
+define <vscale x 1 x i1> @vfptoui_nxv1f32_nxv1i1(<vscale x 1 x float> %va) {
+; CHECK-LABEL: vfptoui_nxv1f32_nxv1i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,mf4,ta,mu
+; CHECK-NEXT:    vfncvt.rtz.xu.f.w v25, v8
+; CHECK-NEXT:    vand.vi v25, v25, 1
+; CHECK-NEXT:    vmsne.vi v0, v25, 0
+; CHECK-NEXT:    ret
+  %evec = fptoui <vscale x 1 x float> %va to <vscale x 1 x i1>
+  ret <vscale x 1 x i1> %evec
+}
+
 define <vscale x 1 x i8> @vfptosi_nxv1f32_nxv1i8(<vscale x 1 x float> %va) {
 ; CHECK-LABEL: vfptosi_nxv1f32_nxv1i8:
 ; CHECK:       # %bb.0:
@@ -550,6 +718,30 @@ define <vscale x 1 x i64> @vfptoui_nxv1f32_nxv1i64(<vscale x 1 x float> %va) {
   ret <vscale x 1 x i64> %evec
 }
 
+define <vscale x 2 x i1> @vfptosi_nxv2f32_nxv2i1(<vscale x 2 x float> %va) {
+; CHECK-LABEL: vfptosi_nxv2f32_nxv2i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,mf2,ta,mu
+; CHECK-NEXT:    vfncvt.rtz.x.f.w v25, v8
+; CHECK-NEXT:    vand.vi v25, v25, 1
+; CHECK-NEXT:    vmsne.vi v0, v25, 0
+; CHECK-NEXT:    ret
+  %evec = fptosi <vscale x 2 x float> %va to <vscale x 2 x i1>
+  ret <vscale x 2 x i1> %evec
+}
+
+define <vscale x 2 x i1> @vfptoui_nxv2f32_nxv2i1(<vscale x 2 x float> %va) {
+; CHECK-LABEL: vfptoui_nxv2f32_nxv2i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,mf2,ta,mu
+; CHECK-NEXT:    vfncvt.rtz.xu.f.w v25, v8
+; CHECK-NEXT:    vand.vi v25, v25, 1
+; CHECK-NEXT:    vmsne.vi v0, v25, 0
+; CHECK-NEXT:    ret
+  %evec = fptoui <vscale x 2 x float> %va to <vscale x 2 x i1>
+  ret <vscale x 2 x i1> %evec
+}
+
 define <vscale x 2 x i8> @vfptosi_nxv2f32_nxv2i8(<vscale x 2 x float> %va) {
 ; CHECK-LABEL: vfptosi_nxv2f32_nxv2i8:
 ; CHECK:       # %bb.0:
@@ -638,6 +830,30 @@ define <vscale x 2 x i64> @vfptoui_nxv2f32_nxv2i64(<vscale x 2 x float> %va) {
   ret <vscale x 2 x i64> %evec
 }
 
+define <vscale x 4 x i1> @vfptosi_nxv4f32_nxv4i1(<vscale x 4 x float> %va) {
+; CHECK-LABEL: vfptosi_nxv4f32_nxv4i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
+; CHECK-NEXT:    vfncvt.rtz.x.f.w v25, v8
+; CHECK-NEXT:    vand.vi v25, v25, 1
+; CHECK-NEXT:    vmsne.vi v0, v25, 0
+; CHECK-NEXT:    ret
+  %evec = fptosi <vscale x 4 x float> %va to <vscale x 4 x i1>
+  ret <vscale x 4 x i1> %evec
+}
+
+define <vscale x 4 x i1> @vfptoui_nxv4f32_nxv4i1(<vscale x 4 x float> %va) {
+; CHECK-LABEL: vfptoui_nxv4f32_nxv4i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
+; CHECK-NEXT:    vfncvt.rtz.xu.f.w v25, v8
+; CHECK-NEXT:    vand.vi v25, v25, 1
+; CHECK-NEXT:    vmsne.vi v0, v25, 0
+; CHECK-NEXT:    ret
+  %evec = fptoui <vscale x 4 x float> %va to <vscale x 4 x i1>
+  ret <vscale x 4 x i1> %evec
+}
+
 define <vscale x 4 x i8> @vfptosi_nxv4f32_nxv4i8(<vscale x 4 x float> %va) {
 ; CHECK-LABEL: vfptosi_nxv4f32_nxv4i8:
 ; CHECK:       # %bb.0:
@@ -726,6 +942,30 @@ define <vscale x 4 x i64> @vfptoui_nxv4f32_nxv4i64(<vscale x 4 x float> %va) {
   ret <vscale x 4 x i64> %evec
 }
 
+define <vscale x 8 x i1> @vfptosi_nxv8f32_nxv8i1(<vscale x 8 x float> %va) {
+; CHECK-LABEL: vfptosi_nxv8f32_nxv8i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vfncvt.rtz.x.f.w v26, v8
+; CHECK-NEXT:    vand.vi v26, v26, 1
+; CHECK-NEXT:    vmsne.vi v0, v26, 0
+; CHECK-NEXT:    ret
+  %evec = fptosi <vscale x 8 x float> %va to <vscale x 8 x i1>
+  ret <vscale x 8 x i1> %evec
+}
+
+define <vscale x 8 x i1> @vfptoui_nxv8f32_nxv8i1(<vscale x 8 x float> %va) {
+; CHECK-LABEL: vfptoui_nxv8f32_nxv8i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vfncvt.rtz.xu.f.w v26, v8
+; CHECK-NEXT:    vand.vi v26, v26, 1
+; CHECK-NEXT:    vmsne.vi v0, v26, 0
+; CHECK-NEXT:    ret
+  %evec = fptoui <vscale x 8 x float> %va to <vscale x 8 x i1>
+  ret <vscale x 8 x i1> %evec
+}
+
 define <vscale x 8 x i8> @vfptosi_nxv8f32_nxv8i8(<vscale x 8 x float> %va) {
 ; CHECK-LABEL: vfptosi_nxv8f32_nxv8i8:
 ; CHECK:       # %bb.0:
@@ -814,6 +1054,30 @@ define <vscale x 8 x i64> @vfptoui_nxv8f32_nxv8i64(<vscale x 8 x float> %va) {
   ret <vscale x 8 x i64> %evec
 }
 
+define <vscale x 16 x i1> @vfptosi_nxv16f32_nxv16i1(<vscale x 16 x float> %va) {
+; CHECK-LABEL: vfptosi_nxv16f32_nxv16i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m4,ta,mu
+; CHECK-NEXT:    vfncvt.rtz.x.f.w v28, v8
+; CHECK-NEXT:    vand.vi v28, v28, 1
+; CHECK-NEXT:    vmsne.vi v0, v28, 0
+; CHECK-NEXT:    ret
+  %evec = fptosi <vscale x 16 x float> %va to <vscale x 16 x i1>
+  ret <vscale x 16 x i1> %evec
+}
+
+define <vscale x 16 x i1> @vfptoui_nxv16f32_nxv16i1(<vscale x 16 x float> %va) {
+; CHECK-LABEL: vfptoui_nxv16f32_nxv16i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m4,ta,mu
+; CHECK-NEXT:    vfncvt.rtz.xu.f.w v28, v8
+; CHECK-NEXT:    vand.vi v28, v28, 1
+; CHECK-NEXT:    vmsne.vi v0, v28, 0
+; CHECK-NEXT:    ret
+  %evec = fptoui <vscale x 16 x float> %va to <vscale x 16 x i1>
+  ret <vscale x 16 x i1> %evec
+}
+
 define <vscale x 16 x i8> @vfptosi_nxv16f32_nxv16i8(<vscale x 16 x float> %va) {
 ; CHECK-LABEL: vfptosi_nxv16f32_nxv16i8:
 ; CHECK:       # %bb.0:
@@ -880,6 +1144,30 @@ define <vscale x 16 x i32> @vfptoui_nxv16f32_nxv16i32(<vscale x 16 x float> %va)
   ret <vscale x 16 x i32> %evec
 }
 
+define <vscale x 1 x i1> @vfptosi_nxv1f64_nxv1i1(<vscale x 1 x double> %va) {
+; CHECK-LABEL: vfptosi_nxv1f64_nxv1i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,mf2,ta,mu
+; CHECK-NEXT:    vfncvt.rtz.x.f.w v25, v8
+; CHECK-NEXT:    vand.vi v25, v25, 1
+; CHECK-NEXT:    vmsne.vi v0, v25, 0
+; CHECK-NEXT:    ret
+  %evec = fptosi <vscale x 1 x double> %va to <vscale x 1 x i1>
+  ret <vscale x 1 x i1> %evec
+}
+
+define <vscale x 1 x i1> @vfptoui_nxv1f64_nxv1i1(<vscale x 1 x double> %va) {
+; CHECK-LABEL: vfptoui_nxv1f64_nxv1i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,mf2,ta,mu
+; CHECK-NEXT:    vfncvt.rtz.xu.f.w v25, v8
+; CHECK-NEXT:    vand.vi v25, v25, 1
+; CHECK-NEXT:    vmsne.vi v0, v25, 0
+; CHECK-NEXT:    ret
+  %evec = fptoui <vscale x 1 x double> %va to <vscale x 1 x i1>
+  ret <vscale x 1 x i1> %evec
+}
+
 define <vscale x 1 x i8> @vfptosi_nxv1f64_nxv1i8(<vscale x 1 x double> %va) {
 ; CHECK-LABEL: vfptosi_nxv1f64_nxv1i8:
 ; CHECK:       # %bb.0:
@@ -974,6 +1262,30 @@ define <vscale x 1 x i64> @vfptoui_nxv1f64_nxv1i64(<vscale x 1 x double> %va) {
   ret <vscale x 1 x i64> %evec
 }
 
+define <vscale x 2 x i1> @vfptosi_nxv2f64_nxv2i1(<vscale x 2 x double> %va) {
+; CHECK-LABEL: vfptosi_nxv2f64_nxv2i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
+; CHECK-NEXT:    vfncvt.rtz.x.f.w v25, v8
+; CHECK-NEXT:    vand.vi v25, v25, 1
+; CHECK-NEXT:    vmsne.vi v0, v25, 0
+; CHECK-NEXT:    ret
+  %evec = fptosi <vscale x 2 x double> %va to <vscale x 2 x i1>
+  ret <vscale x 2 x i1> %evec
+}
+
+define <vscale x 2 x i1> @vfptoui_nxv2f64_nxv2i1(<vscale x 2 x double> %va) {
+; CHECK-LABEL: vfptoui_nxv2f64_nxv2i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
+; CHECK-NEXT:    vfncvt.rtz.xu.f.w v25, v8
+; CHECK-NEXT:    vand.vi v25, v25, 1
+; CHECK-NEXT:    vmsne.vi v0, v25, 0
+; CHECK-NEXT:    ret
+  %evec = fptoui <vscale x 2 x double> %va to <vscale x 2 x i1>
+  ret <vscale x 2 x i1> %evec
+}
+
 define <vscale x 2 x i8> @vfptosi_nxv2f64_nxv2i8(<vscale x 2 x double> %va) {
 ; CHECK-LABEL: vfptosi_nxv2f64_nxv2i8:
 ; CHECK:       # %bb.0:
@@ -1068,6 +1380,30 @@ define <vscale x 2 x i64> @vfptoui_nxv2f64_nxv2i64(<vscale x 2 x double> %va) {
   ret <vscale x 2 x i64> %evec
 }
 
+define <vscale x 4 x i1> @vfptosi_nxv4f64_nxv4i1(<vscale x 4 x double> %va) {
+; CHECK-LABEL: vfptosi_nxv4f64_nxv4i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m2,ta,mu
+; CHECK-NEXT:    vfncvt.rtz.x.f.w v26, v8
+; CHECK-NEXT:    vand.vi v26, v26, 1
+; CHECK-NEXT:    vmsne.vi v0, v26, 0
+; CHECK-NEXT:    ret
+  %evec = fptosi <vscale x 4 x double> %va to <vscale x 4 x i1>
+  ret <vscale x 4 x i1> %evec
+}
+
+define <vscale x 4 x i1> @vfptoui_nxv4f64_nxv4i1(<vscale x 4 x double> %va) {
+; CHECK-LABEL: vfptoui_nxv4f64_nxv4i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m2,ta,mu
+; CHECK-NEXT:    vfncvt.rtz.xu.f.w v26, v8
+; CHECK-NEXT:    vand.vi v26, v26, 1
+; CHECK-NEXT:    vmsne.vi v0, v26, 0
+; CHECK-NEXT:    ret
+  %evec = fptoui <vscale x 4 x double> %va to <vscale x 4 x i1>
+  ret <vscale x 4 x i1> %evec
+}
+
 define <vscale x 4 x i8> @vfptosi_nxv4f64_nxv4i8(<vscale x 4 x double> %va) {
 ; CHECK-LABEL: vfptosi_nxv4f64_nxv4i8:
 ; CHECK:       # %bb.0:
@@ -1162,6 +1498,30 @@ define <vscale x 4 x i64> @vfptoui_nxv4f64_nxv4i64(<vscale x 4 x double> %va) {
   ret <vscale x 4 x i64> %evec
 }
 
+define <vscale x 8 x i1> @vfptosi_nxv8f64_nxv8i1(<vscale x 8 x double> %va) {
+; CHECK-LABEL: vfptosi_nxv8f64_nxv8i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vfncvt.rtz.x.f.w v28, v8
+; CHECK-NEXT:    vand.vi v28, v28, 1
+; CHECK-NEXT:    vmsne.vi v0, v28, 0
+; CHECK-NEXT:    ret
+  %evec = fptosi <vscale x 8 x double> %va to <vscale x 8 x i1>
+  ret <vscale x 8 x i1> %evec
+}
+
+define <vscale x 8 x i1> @vfptoui_nxv8f64_nxv8i1(<vscale x 8 x double> %va) {
+; CHECK-LABEL: vfptoui_nxv8f64_nxv8i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vfncvt.rtz.xu.f.w v28, v8
+; CHECK-NEXT:    vand.vi v28, v28, 1
+; CHECK-NEXT:    vmsne.vi v0, v28, 0
+; CHECK-NEXT:    ret
+  %evec = fptoui <vscale x 8 x double> %va to <vscale x 8 x i1>
+  ret <vscale x 8 x i1> %evec
+}
+
 define <vscale x 8 x i8> @vfptosi_nxv8f64_nxv8i8(<vscale x 8 x double> %va) {
 ; CHECK-LABEL: vfptosi_nxv8f64_nxv8i8:
 ; CHECK:       # %bb.0:
diff --git a/llvm/test/CodeGen/RISCV/rvv/vitofp-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vitofp-sdnode.ll
index 3bcd4a5..a6cf9ac 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vitofp-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vitofp-sdnode.ll
@@ -4,6 +4,366 @@
 ; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-zfh,+experimental-v -target-abi=lp64d \
 ; RUN:     -verify-machineinstrs < %s | FileCheck %s
 
+define <vscale x 1 x half> @vsitofp_nxv1i1_nxv1f16(<vscale x 1 x i1> %va) {
+; CHECK-LABEL: vsitofp_nxv1i1_nxv1f16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,mf4,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, 0
+; CHECK-NEXT:    vmerge.vim v25, v25, -1, v0
+; CHECK-NEXT:    vfcvt.f.x.v v8, v25
+; CHECK-NEXT:    ret
+  %evec = sitofp <vscale x 1 x i1> %va to <vscale x 1 x half>
+  ret <vscale x 1 x half> %evec
+}
+
+define <vscale x 1 x half> @vuitofp_nxv1i1_nxv1f16(<vscale x 1 x i1> %va) {
+; CHECK-LABEL: vuitofp_nxv1i1_nxv1f16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,mf4,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, 0
+; CHECK-NEXT:    vmerge.vim v25, v25, 1, v0
+; CHECK-NEXT:    vfcvt.f.xu.v v8, v25
+; CHECK-NEXT:    ret
+  %evec = uitofp <vscale x 1 x i1> %va to <vscale x 1 x half>
+  ret <vscale x 1 x half> %evec
+}
+
+define <vscale x 1 x float> @vsitofp_nxv1i1_nxv1f32(<vscale x 1 x i1> %va) {
+; CHECK-LABEL: vsitofp_nxv1i1_nxv1f32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,mf2,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, 0
+; CHECK-NEXT:    vmerge.vim v25, v25, -1, v0
+; CHECK-NEXT:    vfcvt.f.x.v v8, v25
+; CHECK-NEXT:    ret
+  %evec = sitofp <vscale x 1 x i1> %va to <vscale x 1 x float>
+  ret <vscale x 1 x float> %evec
+}
+
+define <vscale x 1 x float> @vuitofp_nxv1i1_nxv1f32(<vscale x 1 x i1> %va) {
+; CHECK-LABEL: vuitofp_nxv1i1_nxv1f32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,mf2,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, 0
+; CHECK-NEXT:    vmerge.vim v25, v25, 1, v0
+; CHECK-NEXT:    vfcvt.f.xu.v v8, v25
+; CHECK-NEXT:    ret
+  %evec = uitofp <vscale x 1 x i1> %va to <vscale x 1 x float>
+  ret <vscale x 1 x float> %evec
+}
+
+define <vscale x 1 x double> @vsitofp_nxv1i1_nxv1f64(<vscale x 1 x i1> %va) {
+; CHECK-LABEL: vsitofp_nxv1i1_nxv1f64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, 0
+; CHECK-NEXT:    vmerge.vim v25, v25, -1, v0
+; CHECK-NEXT:    vfcvt.f.x.v v8, v25
+; CHECK-NEXT:    ret
+  %evec = sitofp <vscale x 1 x i1> %va to <vscale x 1 x double>
+  ret <vscale x 1 x double> %evec
+}
+
+define <vscale x 1 x double> @vuitofp_nxv1i1_nxv1f64(<vscale x 1 x i1> %va) {
+; CHECK-LABEL: vuitofp_nxv1i1_nxv1f64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, 0
+; CHECK-NEXT:    vmerge.vim v25, v25, 1, v0
+; CHECK-NEXT:    vfcvt.f.xu.v v8, v25
+; CHECK-NEXT:    ret
+  %evec = uitofp <vscale x 1 x i1> %va to <vscale x 1 x double>
+  ret <vscale x 1 x double> %evec
+}
+
+define <vscale x 2 x half> @vsitofp_nxv2i1_nxv2f16(<vscale x 2 x i1> %va) {
+; CHECK-LABEL: vsitofp_nxv2i1_nxv2f16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,mf2,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, 0
+; CHECK-NEXT:    vmerge.vim v25, v25, -1, v0
+; CHECK-NEXT:    vfcvt.f.x.v v8, v25
+; CHECK-NEXT:    ret
+  %evec = sitofp <vscale x 2 x i1> %va to <vscale x 2 x half>
+  ret <vscale x 2 x half> %evec
+}
+
+define <vscale x 2 x half> @vuitofp_nxv2i1_nxv2f16(<vscale x 2 x i1> %va) {
+; CHECK-LABEL: vuitofp_nxv2i1_nxv2f16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,mf2,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, 0
+; CHECK-NEXT:    vmerge.vim v25, v25, 1, v0
+; CHECK-NEXT:    vfcvt.f.xu.v v8, v25
+; CHECK-NEXT:    ret
+  %evec = uitofp <vscale x 2 x i1> %va to <vscale x 2 x half>
+  ret <vscale x 2 x half> %evec
+}
+
+define <vscale x 2 x float> @vsitofp_nxv2i1_nxv2f32(<vscale x 2 x i1> %va) {
+; CHECK-LABEL: vsitofp_nxv2i1_nxv2f32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, 0
+; CHECK-NEXT:    vmerge.vim v25, v25, -1, v0
+; CHECK-NEXT:    vfcvt.f.x.v v8, v25
+; CHECK-NEXT:    ret
+  %evec = sitofp <vscale x 2 x i1> %va to <vscale x 2 x float>
+  ret <vscale x 2 x float> %evec
+}
+
+define <vscale x 2 x float> @vuitofp_nxv2i1_nxv2f32(<vscale x 2 x i1> %va) {
+; CHECK-LABEL: vuitofp_nxv2i1_nxv2f32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, 0
+; CHECK-NEXT:    vmerge.vim v25, v25, 1, v0
+; CHECK-NEXT:    vfcvt.f.xu.v v8, v25
+; CHECK-NEXT:    ret
+  %evec = uitofp <vscale x 2 x i1> %va to <vscale x 2 x float>
+  ret <vscale x 2 x float> %evec
+}
+
+define <vscale x 2 x double> @vsitofp_nxv2i1_nxv2f64(<vscale x 2 x i1> %va) {
+; CHECK-LABEL: vsitofp_nxv2i1_nxv2f64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m2,ta,mu
+; CHECK-NEXT:    vmv.v.i v26, 0
+; CHECK-NEXT:    vmerge.vim v26, v26, -1, v0
+; CHECK-NEXT:    vfcvt.f.x.v v8, v26
+; CHECK-NEXT:    ret
+  %evec = sitofp <vscale x 2 x i1> %va to <vscale x 2 x double>
+  ret <vscale x 2 x double> %evec
+}
+
+define <vscale x 2 x double> @vuitofp_nxv2i1_nxv2f64(<vscale x 2 x i1> %va) {
+; CHECK-LABEL: vuitofp_nxv2i1_nxv2f64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m2,ta,mu
+; CHECK-NEXT:    vmv.v.i v26, 0
+; CHECK-NEXT:    vmerge.vim v26, v26, 1, v0
+; CHECK-NEXT:    vfcvt.f.xu.v v8, v26
+; CHECK-NEXT:    ret
+  %evec = uitofp <vscale x 2 x i1> %va to <vscale x 2 x double>
+  ret <vscale x 2 x double> %evec
+}
+
+define <vscale x 4 x half> @vsitofp_nxv4i1_nxv4f16(<vscale x 4 x i1> %va) {
+; CHECK-LABEL: vsitofp_nxv4i1_nxv4f16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, 0
+; CHECK-NEXT:    vmerge.vim v25, v25, -1, v0
+; CHECK-NEXT:    vfcvt.f.x.v v8, v25
+; CHECK-NEXT:    ret
+  %evec = sitofp <vscale x 4 x i1> %va to <vscale x 4 x half>
+  ret <vscale x 4 x half> %evec
+}
+
+define <vscale x 4 x half> @vuitofp_nxv4i1_nxv4f16(<vscale x 4 x i1> %va) {
+; CHECK-LABEL: vuitofp_nxv4i1_nxv4f16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, 0
+; CHECK-NEXT:    vmerge.vim v25, v25, 1, v0
+; CHECK-NEXT:    vfcvt.f.xu.v v8, v25
+; CHECK-NEXT:    ret
+  %evec = uitofp <vscale x 4 x i1> %va to <vscale x 4 x half>
+  ret <vscale x 4 x half> %evec
+}
+
+define <vscale x 4 x float> @vsitofp_nxv4i1_nxv4f32(<vscale x 4 x i1> %va) {
+; CHECK-LABEL: vsitofp_nxv4i1_nxv4f32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m2,ta,mu
+; CHECK-NEXT:    vmv.v.i v26, 0
+; CHECK-NEXT:    vmerge.vim v26, v26, -1, v0
+; CHECK-NEXT:    vfcvt.f.x.v v8, v26
+; CHECK-NEXT:    ret
+  %evec = sitofp <vscale x 4 x i1> %va to <vscale x 4 x float>
+  ret <vscale x 4 x float> %evec
+}
+
+define <vscale x 4 x float> @vuitofp_nxv4i1_nxv4f32(<vscale x 4 x i1> %va) {
+; CHECK-LABEL: vuitofp_nxv4i1_nxv4f32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m2,ta,mu
+; CHECK-NEXT:    vmv.v.i v26, 0
+; CHECK-NEXT:    vmerge.vim v26, v26, 1, v0
+; CHECK-NEXT:    vfcvt.f.xu.v v8, v26
+; CHECK-NEXT:    ret
+  %evec = uitofp <vscale x 4 x i1> %va to <vscale x 4 x float>
+  ret <vscale x 4 x float> %evec
+}
+
+define <vscale x 4 x double> @vsitofp_nxv4i1_nxv4f64(<vscale x 4 x i1> %va) {
+; CHECK-LABEL: vsitofp_nxv4i1_nxv4f64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m4,ta,mu
+; CHECK-NEXT:    vmv.v.i v28, 0
+; CHECK-NEXT:    vmerge.vim v28, v28, -1, v0
+; CHECK-NEXT:    vfcvt.f.x.v v8, v28
+; CHECK-NEXT:    ret
+  %evec = sitofp <vscale x 4 x i1> %va to <vscale x 4 x double>
+  ret <vscale x 4 x double> %evec
+}
+
+define <vscale x 4 x double> @vuitofp_nxv4i1_nxv4f64(<vscale x 4 x i1> %va) {
+; CHECK-LABEL: vuitofp_nxv4i1_nxv4f64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m4,ta,mu
+; CHECK-NEXT:    vmv.v.i v28, 0
+; CHECK-NEXT:    vmerge.vim v28, v28, 1, v0
+; CHECK-NEXT:    vfcvt.f.xu.v v8, v28
+; CHECK-NEXT:    ret
+  %evec = uitofp <vscale x 4 x i1> %va to <vscale x 4 x double>
+  ret <vscale x 4 x double> %evec
+}
+
+define <vscale x 8 x half> @vsitofp_nxv8i1_nxv8f16(<vscale x 8 x i1> %va) {
+; CHECK-LABEL: vsitofp_nxv8i1_nxv8f16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vmv.v.i v26, 0
+; CHECK-NEXT:    vmerge.vim v26, v26, -1, v0
+; CHECK-NEXT:    vfcvt.f.x.v v8, v26
+; CHECK-NEXT:    ret
+  %evec = sitofp <vscale x 8 x i1> %va to <vscale x 8 x half>
+  ret <vscale x 8 x half> %evec
+}
+
+define <vscale x 8 x half> @vuitofp_nxv8i1_nxv8f16(<vscale x 8 x i1> %va) {
+; CHECK-LABEL: vuitofp_nxv8i1_nxv8f16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vmv.v.i v26, 0
+; CHECK-NEXT:    vmerge.vim v26, v26, 1, v0
+; CHECK-NEXT:    vfcvt.f.xu.v v8, v26
+; CHECK-NEXT:    ret
+  %evec = uitofp <vscale x 8 x i1> %va to <vscale x 8 x half>
+  ret <vscale x 8 x half> %evec
+}
+
+define <vscale x 8 x float> @vsitofp_nxv8i1_nxv8f32(<vscale x 8 x i1> %va) {
+; CHECK-LABEL: vsitofp_nxv8i1_nxv8f32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vmv.v.i v28, 0
+; CHECK-NEXT:    vmerge.vim v28, v28, -1, v0
+; CHECK-NEXT:    vfcvt.f.x.v v8, v28
+; CHECK-NEXT:    ret
+  %evec = sitofp <vscale x 8 x i1> %va to <vscale x 8 x float>
+  ret <vscale x 8 x float> %evec
+}
+
+define <vscale x 8 x float> @vuitofp_nxv8i1_nxv8f32(<vscale x 8 x i1> %va) {
+; CHECK-LABEL: vuitofp_nxv8i1_nxv8f32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vmv.v.i v28, 0
+; CHECK-NEXT:    vmerge.vim v28, v28, 1, v0
+; CHECK-NEXT:    vfcvt.f.xu.v v8, v28
+; CHECK-NEXT:    ret
+  %evec = uitofp <vscale x 8 x i1> %va to <vscale x 8 x float>
+  ret <vscale x 8 x float> %evec
+}
+
+define <vscale x 8 x double> @vsitofp_nxv8i1_nxv8f64(<vscale x 8 x i1> %va) {
+; CHECK-LABEL: vsitofp_nxv8i1_nxv8f64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv.v.i v8, 0
+; CHECK-NEXT:    vmerge.vim v8, v8, -1, v0
+; CHECK-NEXT:    vfcvt.f.x.v v8, v8
+; CHECK-NEXT:    ret
+  %evec = sitofp <vscale x 8 x i1> %va to <vscale x 8 x double>
+  ret <vscale x 8 x double> %evec
+}
+
+define <vscale x 8 x double> @vuitofp_nxv8i1_nxv8f64(<vscale x 8 x i1> %va) {
+; CHECK-LABEL: vuitofp_nxv8i1_nxv8f64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv.v.i v8, 0
+; CHECK-NEXT:    vmerge.vim v8, v8, 1, v0
+; CHECK-NEXT:    vfcvt.f.xu.v v8, v8
+; CHECK-NEXT:    ret
+  %evec = uitofp <vscale x 8 x i1> %va to <vscale x 8 x double>
+  ret <vscale x 8 x double> %evec
+}
+
+define <vscale x 16 x half> @vsitofp_nxv16i1_nxv16f16(<vscale x 16 x i1> %va) {
+; CHECK-LABEL: vsitofp_nxv16i1_nxv16f16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m4,ta,mu
+; CHECK-NEXT:    vmv.v.i v28, 0
+; CHECK-NEXT:    vmerge.vim v28, v28, -1, v0
+; CHECK-NEXT:    vfcvt.f.x.v v8, v28
+; CHECK-NEXT:    ret
+  %evec = sitofp <vscale x 16 x i1> %va to <vscale x 16 x half>
+  ret <vscale x 16 x half> %evec
+}
+
+define <vscale x 16 x half> @vuitofp_nxv16i1_nxv16f16(<vscale x 16 x i1> %va) {
+; CHECK-LABEL: vuitofp_nxv16i1_nxv16f16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m4,ta,mu
+; CHECK-NEXT:    vmv.v.i v28, 0
+; CHECK-NEXT:    vmerge.vim v28, v28, 1, v0
+; CHECK-NEXT:    vfcvt.f.xu.v v8, v28
+; CHECK-NEXT:    ret
+  %evec = uitofp <vscale x 16 x i1> %va to <vscale x 16 x half>
+  ret <vscale x 16 x half> %evec
+}
+
+define <vscale x 16 x float> @vsitofp_nxv16i1_nxv16f32(<vscale x 16 x i1> %va) {
+; CHECK-LABEL: vsitofp_nxv16i1_nxv16f32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vmv.v.i v8, 0
+; CHECK-NEXT:    vmerge.vim v8, v8, -1, v0
+; CHECK-NEXT:    vfcvt.f.x.v v8, v8
+; CHECK-NEXT:    ret
+  %evec = sitofp <vscale x 16 x i1> %va to <vscale x 16 x float>
+  ret <vscale x 16 x float> %evec
+}
+
+define <vscale x 16 x float> @vuitofp_nxv16i1_nxv16f32(<vscale x 16 x i1> %va) {
+; CHECK-LABEL: vuitofp_nxv16i1_nxv16f32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vmv.v.i v8, 0
+; CHECK-NEXT:    vmerge.vim v8, v8, 1, v0
+; CHECK-NEXT:    vfcvt.f.xu.v v8, v8
+; CHECK-NEXT:    ret
+  %evec = uitofp <vscale x 16 x i1> %va to <vscale x 16 x float>
+  ret <vscale x 16 x float> %evec
+}
+
+define <vscale x 32 x half> @vsitofp_nxv32i1_nxv32f16(<vscale x 32 x i1> %va) {
+; CHECK-LABEL: vsitofp_nxv32i1_nxv32f16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vmv.v.i v8, 0
+; CHECK-NEXT:    vmerge.vim v8, v8, -1, v0
+; CHECK-NEXT:    vfcvt.f.x.v v8, v8
+; CHECK-NEXT:    ret
+  %evec = sitofp <vscale x 32 x i1> %va to <vscale x 32 x half>
+  ret <vscale x 32 x half> %evec
+}
+
+define <vscale x 32 x half> @vuitofp_nxv32i1_nxv32f16(<vscale x 32 x i1> %va) {
+; CHECK-LABEL: vuitofp_nxv32i1_nxv32f16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vmv.v.i v8, 0
+; CHECK-NEXT:    vmerge.vim v8, v8, 1, v0
+; CHECK-NEXT:    vfcvt.f.xu.v v8, v8
+; CHECK-NEXT:    ret
+  %evec = uitofp <vscale x 32 x i1> %va to <vscale x 32 x half>
+  ret <vscale x 32 x half> %evec
+}
+
 define <vscale x 1 x half> @vsitofp_nxv1i8_nxv1f16(<vscale x 1 x i8> %va) {
 ; CHECK-LABEL: vsitofp_nxv1i8_nxv1f16:
 ; CHECK:       # %bb.0:
-- 
2.7.4