From ead21518eb5e5dee8ddca3b98c78daaa00ece3f9 Mon Sep 17 00:00:00 2001 From: "ruixuan.li" Date: Thu, 21 Mar 2019 00:21:10 +0800 Subject: [PATCH] sm1: emmc run hs200 busmode [1/1] PD#SWPL-5404 Problem: emmc report data crc error in hs200 busmode Solution: set hs200 co_phase to 2 and did not reset the hs200 co_phase and tx_phase when adjust tuning is find the error point in sm1 Verify: verify pass on sm1_s905d3_ac200 Change-Id: I56aa8eb666fb55641db75878a3488f66c721bd6d Signed-off-by: ruixuan.li --- arch/arm64/boot/dts/amlogic/sm1_s905d3_ac200.dts | 4 ++-- arch/arm64/boot/dts/amlogic/sm1_s905d3_skt.dts | 4 ++-- drivers/amlogic/mmc/aml_sd_emmc.c | 2 +- drivers/amlogic/mmc/aml_sd_emmc_v3.c | 6 ++++-- 4 files changed, 9 insertions(+), 7 deletions(-) diff --git a/arch/arm64/boot/dts/amlogic/sm1_s905d3_ac200.dts b/arch/arm64/boot/dts/amlogic/sm1_s905d3_ac200.dts index c764ed0..373a3a2 100644 --- a/arch/arm64/boot/dts/amlogic/sm1_s905d3_ac200.dts +++ b/arch/arm64/boot/dts/amlogic/sm1_s905d3_ac200.dts @@ -1443,10 +1443,10 @@ "MMC_CAP_HW_RESET", "MMC_CAP_ERASE", "MMC_CAP_CMD23"; - /*caps2 = "MMC_CAP2_HS200";*/ + caps2 = "MMC_CAP2_HS200"; /* "MMC_CAP2_HS400";*/ f_min = <400000>; - f_max = <50000000>; + f_max = <200000000>; }; }; diff --git a/arch/arm64/boot/dts/amlogic/sm1_s905d3_skt.dts b/arch/arm64/boot/dts/amlogic/sm1_s905d3_skt.dts index efc1e2d..511c736 100644 --- a/arch/arm64/boot/dts/amlogic/sm1_s905d3_skt.dts +++ b/arch/arm64/boot/dts/amlogic/sm1_s905d3_skt.dts @@ -1442,10 +1442,10 @@ "MMC_CAP_HW_RESET", "MMC_CAP_ERASE", "MMC_CAP_CMD23"; - /*caps2 = "MMC_CAP2_HS200";*/ + caps2 = "MMC_CAP2_HS200"; /* "MMC_CAP2_HS400";*/ f_min = <400000>; - f_max = <50000000>; + f_max = <200000000>; }; }; diff --git a/drivers/amlogic/mmc/aml_sd_emmc.c b/drivers/amlogic/mmc/aml_sd_emmc.c index deb56ca..8757b73 100644 --- a/drivers/amlogic/mmc/aml_sd_emmc.c +++ b/drivers/amlogic/mmc/aml_sd_emmc.c @@ -3626,7 +3626,7 @@ static struct meson_mmc_data mmc_data_sm1 = { .sdmmc.hs.core_phase = 3, .sdmmc.ddr.core_phase = 2, .sdmmc.ddr.tx_phase = 0, - .sdmmc.hs2.core_phase = 3, + .sdmmc.hs2.core_phase = 2, .sdmmc.hs2.tx_phase = 0, .sdmmc.hs4.tx_delay = 0, .sdmmc.sd_hs.core_phase = 3, diff --git a/drivers/amlogic/mmc/aml_sd_emmc_v3.c b/drivers/amlogic/mmc/aml_sd_emmc_v3.c index 0a8cae0..b04f790 100644 --- a/drivers/amlogic/mmc/aml_sd_emmc_v3.c +++ b/drivers/amlogic/mmc/aml_sd_emmc_v3.c @@ -1192,8 +1192,10 @@ tunning: nmatch = aml_sd_emmc_tuning_transfer(mmc, opcode, blk_pattern, host->blk_test, blksz); if (nmatch != TUNING_NUM_PER_POINT) { - clkc->core_phase = para->hs2.tx_phase; - clkc->tx_phase = para->hs2.core_phase; + if (host->data->chip_type != MMC_CHIP_SM1) { + clkc->core_phase = para->hs2.tx_phase; + clkc->tx_phase = para->hs2.core_phase; + } writel(vclk, host->base + SD_EMMC_CLOCK_V3); pr_info("%s:try clock:0x%x>>>rx_tuning[%d] = %d\n", mmc_hostname(host->mmc), -- 2.7.4