From eac32a1357ac987e4fd4e0fa91d88177d95f2e2c Mon Sep 17 00:00:00 2001 From: Xingyu Chen Date: Mon, 10 Apr 2017 15:27:56 +0800 Subject: [PATCH] pinctrl: add pinctrl & gpio support for m8b PD#141217: add pinctrl & gpio support for m8b fix gpio irq bugs TODO: because of limitation of software framework and gpio irq lines, the ao gpio pins on M8B don't support external irq detect, and suggest using ee gpio pins to detect. Change-Id: I933b71104877d97444107d8fba56e3540f94efff Signed-off-by: Xingyu Chen --- MAINTAINERS | 3 + arch/arm/boot/dts/amlogic/meson8b.dtsi | 29 +- arch/arm/configs/meson32_defconfig | 1 + arch/arm/mach-meson/Kconfig | 1 - arch/arm64/boot/dts/amlogic/mesongxl.dtsi | 28 +- drivers/amlogic/pinctrl/Makefile | 2 +- drivers/amlogic/pinctrl/pinctrl-meson.c | 619 ++++++++++++------- drivers/amlogic/pinctrl/pinctrl-meson.h | 25 +- drivers/amlogic/pinctrl/pinctrl-meson8b.c | 950 ++++++++++++++++++++++++++++++ include/dt-bindings/gpio/meson8b-gpio.h | 146 ++++- 10 files changed, 1550 insertions(+), 254 deletions(-) create mode 100644 drivers/amlogic/pinctrl/pinctrl-meson8b.c diff --git a/MAINTAINERS b/MAINTAINERS index 16aa14f..7da8673 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -13781,3 +13781,6 @@ F: drivers/amlogic/media/video_processor/Kconfig F: drivers/amlogic/media/video_processor/Makefile F: drivers/amlogic/media/video_processor/ionvideo/* +AMLOGIC PINCTRL SUPPORT FOR M8B +M: Xingyu Chen +F: drivers/amlogic/pinctrl/pinctrl-meson8b.c diff --git a/arch/arm/boot/dts/amlogic/meson8b.dtsi b/arch/arm/boot/dts/amlogic/meson8b.dtsi index 10cb330..61f9d0f 100644 --- a/arch/arm/boot/dts/amlogic/meson8b.dtsi +++ b/arch/arm/boot/dts/amlogic/meson8b.dtsi @@ -181,7 +181,6 @@ pinctrl_cbus: pinctrl@c1109880 { compatible = "amlogic,meson8b-cbus-pinctrl"; - reg = <0xc1109880 0x10>; #address-cells = <1>; #size-cells = <1>; ranges; @@ -190,30 +189,46 @@ reg = <0xc11080b0 0x28>, <0xc11080e8 0x18>, <0xc1108120 0x18>, - <0xc1108030 0x38>; + <0xc1108030 0x38>, + <0xc1109880 0x10>; + interrupts = <0 64 1>, + <0 65 1>, + <0 66 1>, + <0 67 1>, + <0 68 1>, + <0 69 1>, + <0 70 1>, + <0 71 1>; reg-names = "mux", "pull", "pull-enable", - "gpio"; + "gpio", + "irq"; gpio-controller; #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; }; }; pinctrl_aobus: pinctrl@c8100084 { compatible = "amlogic,meson8b-aobus-pinctrl"; - reg = <0xc8100084 0xc>; #address-cells = <1>; #size-cells = <1>; ranges; gpio_ao: ao-bank@c1108030 { reg = <0xc8100014 0x4>, - <0xc810002c 0x4>, - <0xc8100024 0x8>; - reg-names = "mux", "pull", "gpio"; + <0xc810002c 0x4>, + <0xc8100024 0x8>, + <0xc8100084 0x4>; + interrupts = <0 200 1>, + <0 201 1>; + reg-names = "mux", "pull", "gpio", "irq"; gpio-controller; #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; }; uart_ao_a_pins: uart_ao_a { diff --git a/arch/arm/configs/meson32_defconfig b/arch/arm/configs/meson32_defconfig index f2218a6..a7ea61f 100644 --- a/arch/arm/configs/meson32_defconfig +++ b/arch/arm/configs/meson32_defconfig @@ -43,6 +43,7 @@ CONFIG_AMLOGIC_DRIVER=y CONFIG_AMLOGIC_UART=y CONFIG_AMLOGIC_SERIAL_MESON_CONSOLE=y CONFIG_AMLOGIC_IOMAP=y +CONFIG_AMLOGIC_PINCTRL=y CONFIG_AMLOGIC_USB=y CONFIG_AMLOGIC_USB_DWC_OTG_HCD=y CONFIG_AMLOGIC_USB_HOST_ELECT_TEST=y diff --git a/arch/arm/mach-meson/Kconfig b/arch/arm/mach-meson/Kconfig index da3e493..5e808a2 100644 --- a/arch/arm/mach-meson/Kconfig +++ b/arch/arm/mach-meson/Kconfig @@ -6,7 +6,6 @@ menuconfig ARCH_MESON select ARM_GIC select CACHE_L2X0 select PINCTRL - select PINCTRL_MESON select COMMON_CLK if ARCH_MESON diff --git a/arch/arm64/boot/dts/amlogic/mesongxl.dtsi b/arch/arm64/boot/dts/amlogic/mesongxl.dtsi index ff53849..21ad04b 100644 --- a/arch/arm64/boot/dts/amlogic/mesongxl.dtsi +++ b/arch/arm64/boot/dts/amlogic/mesongxl.dtsi @@ -380,7 +380,7 @@ aobus: aobus@c8100000 { compatible = "simple-bus"; reg = <0x0 0xc8100000 0x0 0x100000>, - <0x0 0xc1109880 0x0 0x10>; + <0x0 0xc8100084 0x0 0x4>; #address-cells = <2>; #size-cells = <2>; ranges = <0x0 0x0 0x0 0xc8100000 0x0 0x100000>; @@ -434,14 +434,8 @@ reg = <0x0 0x00014 0x0 0x8>, <0x0 0x0002c 0x0 0x4>, <0x0 0x00024 0x0 0x8>; - interrupts = , - , - , - , - , - , - , - ; + interrupts = <0 200 IRQ_TYPE_EDGE_RISING>, + <0 201 IRQ_TYPE_EDGE_RISING>; reg-names = "mux", "pull", "gpio"; gpio-controller; #gpio-cells = <2>; @@ -522,14 +516,14 @@ <0x0 0x004e8 0x0 0x14>, <0x0 0x00120 0x0 0x14>, <0x0 0x00430 0x0 0x40>; - interrupts = , - , - , - , - , - , - , - ; + interrupts = <0 64 IRQ_TYPE_EDGE_RISING>, + <0 65 IRQ_TYPE_EDGE_RISING>, + <0 66 IRQ_TYPE_EDGE_RISING>, + <0 67 IRQ_TYPE_EDGE_RISING>, + <0 68 IRQ_TYPE_EDGE_RISING>, + <0 69 IRQ_TYPE_EDGE_RISING>, + <0 70 IRQ_TYPE_EDGE_RISING>, + <0 71 IRQ_TYPE_EDGE_RISING>; reg-names = "mux", "pull", "pull-enable", "gpio"; gpio-controller; diff --git a/drivers/amlogic/pinctrl/Makefile b/drivers/amlogic/pinctrl/Makefile index 0839480..dbcd8ae 100644 --- a/drivers/amlogic/pinctrl/Makefile +++ b/drivers/amlogic/pinctrl/Makefile @@ -1,4 +1,4 @@ # #Makefile for the gpio dirver # -obj-$(CONFIG_AMLOGIC_PINCTRL) += pinctrl-meson.o pinctrl_gxl.o +obj-$(CONFIG_AMLOGIC_PINCTRL) += pinctrl-meson.o pinctrl_gxl.o pinctrl-meson8b.o diff --git a/drivers/amlogic/pinctrl/pinctrl-meson.c b/drivers/amlogic/pinctrl/pinctrl-meson.c index acfa4fb..3d27abe 100644 --- a/drivers/amlogic/pinctrl/pinctrl-meson.c +++ b/drivers/amlogic/pinctrl/pinctrl-meson.c @@ -70,18 +70,6 @@ #include "pinctrl-meson.h" /** - *EE Domain and AO Domain share the same gpio irq(irq0-irq7) - */ -static DEFINE_SPINLOCK(irq_res_lock); - -static struct meson_irq_resource meson_gpio_irq; - -static struct meson_irq_resource *meson_get_irq_res(void) -{ - return &meson_gpio_irq; -} - -/** * meson_get_bank() - find the bank containing a given pin * * @domain: the domain containing the pin @@ -560,17 +548,353 @@ static int meson_gpio_get(struct gpio_chip *chip, unsigned int gpio) return !!(val & BIT(bit)); } +/* + * NOP functions + */ +static void noop(struct irq_data *irqd) { } + +static void meson_gpio_irq_enable(struct irq_data *irqd) +{ + struct meson_domain *domain = to_meson_domain(irqd->chip_data); + struct irq_data *parent_data; + unsigned long flags; + unsigned char cnt; + + spin_lock_irqsave(&domain->irq_res.irq_res_lock, flags); + for (cnt = 0; cnt < domain->irq_res.irq_num; cnt++) { + if (domain->irq_res.gpio_irq[cnt].hwirq == irqd->hwirq) { + parent_data = + irq_get_irq_data( + domain->irq_res.gpio_irq[cnt].parent_virq); + /*enable the interrupt line of gpio in GIC controller*/ + parent_data->chip->irq_unmask(parent_data); + } + } + spin_unlock_irqrestore(&domain->irq_res.irq_res_lock, flags); + +} + +static void meson_gpio_irq_disable(struct irq_data *irqd) +{ + struct meson_domain *domain = to_meson_domain(irqd->chip_data); + struct irq_data *parent_data; + unsigned long flags; + unsigned char cnt; + + spin_lock_irqsave(&domain->irq_res.irq_res_lock, flags); + for (cnt = 0; cnt < domain->irq_res.irq_num; cnt++) { + if (domain->irq_res.gpio_irq[cnt].hwirq == irqd->hwirq) { + parent_data = + irq_get_irq_data( + domain->irq_res.gpio_irq[cnt].parent_virq); + /*disable the interrupt line of gpio in GIC controller*/ + parent_data->chip->irq_mask(parent_data); + } + } + spin_unlock_irqrestore(&domain->irq_res.irq_res_lock, flags); +} + +/** + *free gpio irq when free_irq() is called, and another pin can use it again. + */ +static void meson_gpio_irq_shutdown(struct irq_data *irqd) +{ + struct meson_domain *domain = to_meson_domain(irqd->chip_data); + unsigned long flags; + unsigned char cnt; + + spin_lock_irqsave(&domain->irq_res.irq_res_lock, flags); + for (cnt = 0; cnt < domain->irq_res.irq_num; cnt++) { + if (domain->irq_res.gpio_irq[cnt].hwirq == irqd->hwirq) + domain->irq_res.gpio_irq[cnt].used_flag = 0; + } + spin_unlock_irqrestore(&domain->irq_res.irq_res_lock, flags); +} + +static int meson_ee_gpio_irq_type(struct irq_data *irqd, unsigned int type) +{ + struct meson_domain *domain = to_meson_domain(irqd->chip_data); + struct irq_data *parent_data; + unsigned long flags; + unsigned int trigger_type[2]; + unsigned char type_num; + unsigned char type_cnt; + unsigned char start_bit; + unsigned int gpio_virq; + unsigned char cnt; + unsigned char pin; + + type = type & IRQ_TYPE_SENSE_MASK; + + switch (type) { + case IRQ_TYPE_LEVEL_LOW: + trigger_type[0] = 0x10000; + type_num = 1; + break; + case IRQ_TYPE_LEVEL_HIGH: + trigger_type[0] = 0x0; + type_num = 1; + break; + case IRQ_TYPE_EDGE_RISING: + trigger_type[0] = 0x1; + type_num = 1; + break; + case IRQ_TYPE_EDGE_FALLING: + trigger_type[0] = 0x10001; + type_num = 1; + break; + case IRQ_TYPE_EDGE_BOTH: + trigger_type[0] = 0x1; + trigger_type[1] = 0x10001; + type_num = 2; + break; + default: + return -EINVAL; + } + + for (type_cnt = 0; type_cnt < type_num; type_cnt++) { + /* dynamic allocate gpio irq for request pin*/ + spin_lock_irqsave(&domain->irq_res.irq_res_lock, flags); + for (cnt = 0; cnt < domain->irq_res.irq_num; cnt++) { + if (domain->irq_res.gpio_irq[cnt].used_flag) + continue; + else { + domain->irq_res.gpio_irq[cnt].used_flag = 1; + domain->irq_res.gpio_irq[cnt].hwirq = + irqd->hwirq; + break; + } + } + spin_unlock_irqrestore(&domain->irq_res.irq_res_lock, flags); + + if (domain->irq_res.irq_num == cnt) { + pr_err("meson_pinctrl: no more gpio irq available in EE GPIO INTC, allocate gpio irq for pin[%ld] failed.\n", + irqd->hwirq); + return -EINVAL; + } + + regmap_update_bits(domain->reg_irq, + (GPIO_IRQ_EDGE_OFFSET * 4), + 0x10001 << cnt, + trigger_type[type_cnt] << cnt); + + /*the gpio hwirq eqaul to gpio offset in gpio chip*/ +#ifdef CONFIG_ARM64 + pin = domain->data->pin_base + irqd->hwirq; +#else /*for m8b platform*/ + pin = domain->data->pin_base + irqd->hwirq + 14; +#endif + + /*set pin select register*/ + start_bit = (cnt & 3) << 3; + regmap_update_bits(domain->reg_irq, + (cnt < 4)?(GPIO_IRQ_MUX_0_3 * 4):(GPIO_IRQ_MUX_4_7 * 4), + 0xff << start_bit, + pin << start_bit); + /** + *TODO: support to configure the filter registers by + * the func interface. + * all filter registers for gpio will been set 0x7. + */ + start_bit = cnt << 2; + regmap_update_bits(domain->reg_irq, + (GPIO_IRQ_FILTER_OFFSET * 4), + 0x7 << start_bit, 0x7 << start_bit); + + parent_data = + irq_get_irq_data( + domain->irq_res.gpio_irq[cnt].parent_virq); + + /*set trigger type of gpio in GIC controller*/ + if (type & IRQ_TYPE_EDGE_BOTH) + parent_data->chip->irq_set_type(parent_data, + IRQ_TYPE_EDGE_RISING); + else + parent_data->chip->irq_set_type(parent_data, + IRQ_TYPE_LEVEL_HIGH); + + gpio_virq = irq_find_mapping(domain->chip.irqdomain, + domain->irq_res.gpio_irq[cnt].hwirq); + + pr_info("meson_pinctrl: gpio virq[%d] connect to GIC hwirq[%ld]\n", + gpio_virq, + parent_data->hwirq); + } + + return 0; +} + +static int meson_ao_gpio_irq_type(struct irq_data *irqd, unsigned int type) +{ + struct meson_domain *domain = to_meson_domain(irqd->chip_data); + struct irq_data *parent_data; + unsigned long flags; + unsigned int trigger_type[2]; + unsigned char type_num; + unsigned char type_cnt; + unsigned char start_bit; + unsigned int gpio_virq; + unsigned char cnt; + unsigned char pin; + + type = type & IRQ_TYPE_SENSE_MASK; + + switch (type) { + case IRQ_TYPE_LEVEL_LOW: + trigger_type[0] = 0x10000; + type_num = 1; + break; + case IRQ_TYPE_LEVEL_HIGH: + trigger_type[0] = 0x0; + type_num = 1; + break; + case IRQ_TYPE_EDGE_RISING: + trigger_type[0] = 0x40000; + type_num = 1; + break; + case IRQ_TYPE_EDGE_FALLING: + trigger_type[0] = 0x50000; + type_num = 1; + break; + case IRQ_TYPE_EDGE_BOTH: + trigger_type[0] = 0x40000; + trigger_type[1] = 0x50000; + type_num = 2; + break; + default: + return -EINVAL; + } + + + for (type_cnt = 0; type_cnt < type_num; type_cnt++) { + /* dynamic allocate gpio irq for request pin*/ + spin_lock_irqsave(&domain->irq_res.irq_res_lock, flags); + for (cnt = 0; cnt < domain->irq_res.irq_num; cnt++) { + if (domain->irq_res.gpio_irq[cnt].used_flag) + continue; + else { + domain->irq_res.gpio_irq[cnt].used_flag = 1; + domain->irq_res.gpio_irq[cnt].hwirq = + irqd->hwirq; + break; + } + } + spin_unlock_irqrestore(&domain->irq_res.irq_res_lock, flags); + + if (domain->irq_res.irq_num == cnt) { + pr_err("meson_pinctrl: no more gpio irq available in AO GPIO INTC, allocate gpio irq for pin[%ld] failed.\n", + irqd->hwirq); + return -EINVAL; + } + + /*set trigger type*/ + regmap_update_bits(domain->reg_irq, 0, + 0x50000 << cnt, + trigger_type[type_cnt] << cnt); + + /*the gpio hwirq eqaul to gpio offset in gpio chip*/ +#ifdef CONFIG_ARM64 + pin = domain->data->pin_base + irqd->hwirq; +#else /*for m8b platform*/ + pin = irqd->hwirq; +#endif + /*set pin select register*/ + start_bit = cnt << 2; + regmap_update_bits(domain->reg_irq, 0, + 0xf << start_bit, + pin << start_bit); + /** + *TODO: support to configure the filter registers by + * the func interface. + * all filter registers for gpio will been set 0x7. + */ + start_bit = cnt << 2; + regmap_update_bits(domain->reg_irq, 0, + 0x700 << start_bit, 0x700 << start_bit); + + parent_data = + irq_get_irq_data( + domain->irq_res.gpio_irq[cnt].parent_virq); + + /*set trigger type of gpio in GIC controller*/ + if (type & IRQ_TYPE_EDGE_BOTH) + parent_data->chip->irq_set_type(parent_data, + IRQ_TYPE_EDGE_RISING); + else + parent_data->chip->irq_set_type(parent_data, + IRQ_TYPE_LEVEL_HIGH); + + gpio_virq = irq_find_mapping(domain->chip.irqdomain, + domain->irq_res.gpio_irq[cnt].hwirq); + + pr_info("meson_pinctrl: gpio virq[%d] connect to GIC hwirq[%ld]\n", + gpio_virq, + parent_data->hwirq); + } + + return 0; + +} +static struct irq_chip meson_ee_gpio_irq_chip = { + .name = "GPIO-EE", + .irq_enable = meson_gpio_irq_enable, + .irq_disable = meson_gpio_irq_disable, + .irq_set_type = meson_ee_gpio_irq_type, + .irq_mask = noop, + .irq_unmask = noop, + .irq_shutdown = meson_gpio_irq_shutdown, +}; + +static struct irq_chip meson_ao_gpio_irq_chip = { + .name = "GPIO-AO", + .irq_enable = meson_gpio_irq_enable, + .irq_disable = meson_gpio_irq_disable, + .irq_set_type = meson_ao_gpio_irq_type, + .irq_mask = noop, + .irq_unmask = noop, + .irq_shutdown = meson_gpio_irq_shutdown, +}; + +struct meson_pinctrl_private meson_gxl_periphs = { + .pinctrl_data = &meson_gxl_periphs_pinctrl_data, + .irq_chip = &meson_ee_gpio_irq_chip, +}; + +struct meson_pinctrl_private meson_gxl_aobus = { + .pinctrl_data = &meson_gxl_aobus_pinctrl_data, + .irq_chip = &meson_ao_gpio_irq_chip, +}; + +struct meson_pinctrl_private meson_m8b_cbus = { + .pinctrl_data = &meson8b_cbus_pinctrl_data, + .irq_chip = &meson_ee_gpio_irq_chip, +}; + +struct meson_pinctrl_private meson_m8b_aobus = { + .pinctrl_data = &meson8b_aobus_pinctrl_data, + .irq_chip = &meson_ao_gpio_irq_chip, +}; + static const struct of_device_id meson_pinctrl_dt_match[] = { { .compatible = "amlogic,meson-gxl-periphs-pinctrl", - .data = &meson_gxl_periphs_pinctrl_data, + .data = &meson_gxl_periphs, }, { .compatible = "amlogic,meson-gxl-aobus-pinctrl", - .data = &meson_gxl_aobus_pinctrl_data, + .data = &meson_gxl_aobus, + }, + { + .compatible = "amlogic,meson8b-cbus-pinctrl", + .data = &meson_m8b_cbus, + }, + { + .compatible = "amlogic,meson8b-aobus-pinctrl", + .data = &meson_m8b_aobus, }, { }, }; + MODULE_DEVICE_TABLE(of, meson_pinctrl_dt_match); static int meson_gpiolib_register(struct meson_pinctrl *pc) @@ -581,35 +905,35 @@ static int meson_gpiolib_register(struct meson_pinctrl *pc) domain = pc->domain; domain->chip.label = domain->data->name; - /* domain->chip.dev = pc->dev; */ - domain->chip.parent = pc->dev; - domain->chip.request = meson_gpio_request; - domain->chip.free = meson_gpio_free; - domain->chip.direction_input = meson_gpio_direction_input; - domain->chip.direction_output = meson_gpio_direction_output; - domain->chip.get = meson_gpio_get; - domain->chip.set = meson_gpio_set; - domain->chip.base = domain->data->pin_base; - domain->chip.ngpio = domain->data->num_pins; - domain->chip.can_sleep = false; - domain->chip.of_node = domain->of_node; - domain->chip.of_gpio_n_cells = 2; - - ret = gpiochip_add(&domain->chip); - if (ret) { - dev_err(pc->dev, "can't add gpio chip %s\n", - domain->data->name); - goto fail; - } - - ret = gpiochip_add_pin_range(&domain->chip, dev_name(pc->dev), - 0, domain->data->pin_base, - domain->chip.ngpio); - if (ret) { - dev_err(pc->dev, "can't add pin range\n"); + /* domain->chip.dev = pc->dev; */ + domain->chip.parent = pc->dev; + domain->chip.request = meson_gpio_request; + domain->chip.free = meson_gpio_free; + domain->chip.direction_input = meson_gpio_direction_input; + domain->chip.direction_output = meson_gpio_direction_output; + domain->chip.get = meson_gpio_get; + domain->chip.set = meson_gpio_set; + domain->chip.base = domain->data->pin_base; + domain->chip.ngpio = domain->data->num_pins; + domain->chip.can_sleep = false; + domain->chip.of_node = domain->of_node; + domain->chip.of_gpio_n_cells = 2; + + ret = gpiochip_add(&domain->chip); + if (ret) { + dev_err(pc->dev, "can't add gpio chip %s\n", + domain->data->name); goto fail; } + ret = gpiochip_add_pin_range(&domain->chip, dev_name(pc->dev), + 0, domain->data->pin_base, + domain->chip.ngpio); + if (ret) { + dev_err(pc->dev, "can't add pin range\n"); + goto fail; + } + return 0; fail: gpiochip_remove(&pc->domain->chip); @@ -648,13 +972,13 @@ static struct regmap *meson_map_resource(struct meson_pinctrl *pc, return devm_regmap_init_mmio(pc->dev, base, &meson_regmap_config); } +#ifdef CONFIG_ARM64 static struct regmap *meson_irq_map_resource(struct meson_pinctrl *pc, struct device_node *node, char *name) { struct platform_device *pdev; struct resource *res; void __iomem *base; - pdev = of_find_device_by_node(of_get_parent(node)); res = platform_get_resource(pdev, IORESOURCE_MEM, 1); if (IS_ERR(res)) { @@ -674,35 +998,34 @@ static struct regmap *meson_irq_map_resource(struct meson_pinctrl *pc, return devm_regmap_init_mmio(pc->dev, base, &meson_regmap_config); } - +#endif static int meson_irq_parse_and_map(struct meson_pinctrl *pc, struct device_node *node) { - struct meson_irq_resource *meson_irq = meson_get_irq_res(); + struct meson_domain *domain = pc->domain; int cnt; - meson_irq->irq_num = of_irq_count(node); - if (!meson_irq->irq_num) { + domain->irq_res.irq_num = of_irq_count(node); + if (!domain->irq_res.irq_num) { dev_err(pc->dev, "meson_pinctrl: can't find valid property 'interrupts'\n"); return -EINVAL; } - meson_irq->gpio_irq = devm_kzalloc(pc->dev, - sizeof(struct meson_gpio_irq_desc)*(meson_irq->irq_num), - GFP_KERNEL); - if (IS_ERR_OR_NULL(meson_irq->gpio_irq)) + domain->irq_res.gpio_irq = devm_kzalloc(pc->dev, + sizeof(struct meson_gpio_irq_desc)*(domain->irq_res.irq_num), + GFP_KERNEL); + if (IS_ERR_OR_NULL(domain->irq_res.gpio_irq)) return -ENOMEM; - for (cnt = 0; cnt < meson_irq->irq_num; cnt++) - meson_irq->gpio_irq[cnt].parent_virq = + for (cnt = 0; cnt < domain->irq_res.irq_num; cnt++) { + domain->irq_res.gpio_irq[cnt].parent_virq = irq_of_parse_and_map(node, cnt); - + } return 0; } static int meson_pinctrl_parse_dt(struct meson_pinctrl *pc, struct device_node *node) { - struct meson_irq_resource *meson_irq = meson_get_irq_res(); struct device_node *np; struct meson_domain *domain; int num_domains = 0; @@ -726,13 +1049,13 @@ static int meson_pinctrl_parse_dt(struct meson_pinctrl *pc, domain = pc->domain; domain->data = pc->data->domain_data; - if (!meson_irq->init_flag) { - meson_irq->reg_irq = meson_irq_map_resource(pc, node, "irq"); - if (IS_ERR(meson_irq->reg_irq)) { - dev_err(pc->dev, "gpio irq registers not found\n"); - return PTR_ERR(meson_irq->reg_irq); - } +#ifdef CONFIG_ARM64 + domain->reg_irq = meson_irq_map_resource(pc, node, "irq"); + if (IS_ERR(domain->reg_irq)) { + dev_err(pc->dev, "gpio irq registers not found\n"); + return PTR_ERR(domain->reg_irq); } +#endif for_each_child_of_node(node, np) { if (!of_find_property(np, "gpio-controller", NULL)) @@ -763,127 +1086,17 @@ static int meson_pinctrl_parse_dt(struct meson_pinctrl *pc, return PTR_ERR(domain->reg_gpio); } - if (!meson_irq->init_flag) - meson_irq_parse_and_map(pc, np); - - break; - } - return 0; -} - -static void meson_gpio_irq_mask(struct irq_data *irqd) -{ - -} -static void meson_gpio_irq_unmask(struct irq_data *irqd) -{ - -} -static void meson_gpio_irq_ack(struct irq_data *irqd) -{ - -} -static int meson_gpio_irq_type(struct irq_data *irqd, unsigned int type) -{ - struct meson_irq_resource *meson_irq = meson_get_irq_res(); - struct meson_domain *domain = to_meson_domain(irqd->chip_data); - struct irq_data *parent_data; - unsigned int trigger_type[2]; - unsigned long flags; - unsigned char type_num; - unsigned char type_cnt; - unsigned char start_bit; - unsigned char cnt; - unsigned char pin; - - type = type & IRQ_TYPE_SENSE_MASK; - - if (type & IRQ_TYPE_EDGE_BOTH) - irq_set_handler_locked(irqd, handle_edge_irq); - else - irq_set_handler_locked(irqd, handle_level_irq); - - switch (type) { - case IRQ_TYPE_LEVEL_LOW: - trigger_type[0] = 0x10000; - type_num = 1; - break; - case IRQ_TYPE_LEVEL_HIGH: - trigger_type[0] = 0x0; - type_num = 1; - break; - case IRQ_TYPE_EDGE_RISING: - trigger_type[0] = 0x1; - type_num = 1; - break; - case IRQ_TYPE_EDGE_FALLING: - trigger_type[0] = 0x10001; - type_num = 1; - break; - case IRQ_TYPE_EDGE_BOTH: - trigger_type[0] = 0x1; - trigger_type[1] = 0x10001; - type_num = 2; - break; - default: - return -EINVAL; - } - - for (type_cnt = 0; type_cnt < type_num; type_cnt++) { - - spin_lock_irqsave(&irq_res_lock, flags); - - /* dynamic allocate gpio irq for request pin*/ - for (cnt = 0; cnt < meson_irq->irq_num; cnt++) { - if (meson_irq->gpio_irq[cnt].used_flag) - continue; - else { - meson_irq->gpio_irq[cnt].used_flag = 1; - meson_irq->gpio_irq[cnt].hwirq = irqd->hwirq; - break; - } - } - - spin_unlock_irqrestore(&irq_res_lock, flags); - - if (meson_irq->irq_num == cnt) { - pr_err("meson_pinctrl: not gpio irq to be used, allocate gpio irq for pin failed.\n"); - return -EINVAL; +#ifndef CONFIG_ARM64 /*for m8b platform*/ + domain->reg_irq = meson_map_resource(pc, np, "irq"); + if (IS_ERR(domain->reg_irq)) { + dev_err(pc->dev, "gpio irq registers not found\n"); + return PTR_ERR(domain->reg_irq); } +#endif + meson_irq_parse_and_map(pc, np); - regmap_update_bits(meson_irq->reg_irq, - (GPIO_IRQ_EDGE_OFFSET * 4), - 0x10001 << cnt, - trigger_type[type_cnt] << cnt); - - /*the gpio hwirq eqaul to gpio offset in gpio chip*/ - pin = domain->data->pin_base + irqd->hwirq; - pr_debug("meson_pinctrl: pin_base = %d, pin_offset = %ld, parent_irq_offset = %d\n", - domain->data->pin_base, irqd->hwirq, cnt); - - /*set pin select register*/ - start_bit = (cnt & 3) << 3; - regmap_update_bits(meson_irq->reg_irq, - (cnt < 4)?(GPIO_IRQ_MUX_0_3 * 4):(GPIO_IRQ_MUX_4_7 * 4), - 0xff << start_bit, - pin << start_bit); - /** - *TODO: support to configure the filter registers by - * the func interface. - * all filter registers for gpio will been set 0x7. - */ - start_bit = cnt << 2; - regmap_update_bits(meson_irq->reg_irq, - (GPIO_IRQ_FILTER_OFFSET * 4), - 0x7 << start_bit, 0x7 << start_bit); - - /*enable the interrupt line of gpio in GIC controller*/ - parent_data = - irq_get_irq_data(meson_irq->gpio_irq[cnt].parent_virq); - parent_data->chip->irq_unmask(parent_data); - + break; } - return 0; } @@ -891,41 +1104,35 @@ void meson_gpio_irq_handler(struct irq_desc *desc) { struct irq_chip *chip = irq_desc_get_chip(desc); struct gpio_chip *gpio_chip = irq_desc_get_handler_data(desc); - struct meson_irq_resource *meson_irq = meson_get_irq_res(); + struct meson_domain *domain = to_meson_domain(gpio_chip); unsigned char cnt; unsigned int parent_virq; parent_virq = irq_desc_get_irq(desc); chained_irq_enter(chip, desc); - for (cnt = 0; cnt < meson_irq->irq_num; cnt++) - if (parent_virq == meson_irq->gpio_irq[cnt].parent_virq && - meson_irq->gpio_irq[cnt].used_flag) + for (cnt = 0; cnt < domain->irq_res.irq_num; cnt++) { + if (parent_virq == domain->irq_res.gpio_irq[cnt].parent_virq && + domain->irq_res.gpio_irq[cnt].used_flag) generic_handle_irq(irq_find_mapping(gpio_chip->irqdomain, - meson_irq->gpio_irq[cnt].hwirq)); + domain->irq_res.gpio_irq[cnt].hwirq)); + } chained_irq_exit(chip, desc); } -static struct irq_chip meson_gpio_irq_chip = { - .name = "GPIO", - .irq_set_type = meson_gpio_irq_type, - .irq_mask = meson_gpio_irq_mask, - .irq_unmask = meson_gpio_irq_unmask, - .irq_ack = meson_gpio_irq_ack, -}; - -static int meson_irq_setup(struct meson_pinctrl *pc) +static int meson_irq_setup(struct meson_pinctrl *pc, struct irq_chip *irq_chip) { - struct meson_irq_resource *meson_irq = meson_get_irq_res(); struct meson_domain *domain = pc->domain; struct irq_data *parent_data; unsigned char cnt; unsigned char ret; + spin_lock_init(&domain->irq_res.irq_res_lock); + ret = gpiochip_irqchip_add(&domain->chip, - &meson_gpio_irq_chip, + irq_chip, 0, - handle_level_irq, + handle_simple_irq, IRQ_TYPE_NONE); if (ret) { dev_err(pc->dev, "couldn't add irqchip to gpiochip.\n"); @@ -933,15 +1140,16 @@ static int meson_irq_setup(struct meson_pinctrl *pc) } /* Then register the chain on the parent IRQ */ - for (cnt = 0; cnt < meson_irq->irq_num; cnt++) { + for (cnt = 0; cnt < domain->irq_res.irq_num; cnt++) { gpiochip_set_chained_irqchip(&domain->chip, - &meson_gpio_irq_chip, - meson_irq->gpio_irq[cnt].parent_virq, - meson_gpio_irq_handler); + irq_chip, + domain->irq_res.gpio_irq[cnt].parent_virq, + meson_gpio_irq_handler); /*disable the interrupt line of gpio in GIC controller*/ parent_data = - irq_get_irq_data(meson_irq->gpio_irq[cnt].parent_virq); + irq_get_irq_data( + domain->irq_res.gpio_irq[cnt].parent_virq); parent_data->chip->irq_mask(parent_data); } @@ -951,7 +1159,7 @@ static int meson_irq_setup(struct meson_pinctrl *pc) static int meson_pinctrl_probe(struct platform_device *pdev) { - struct meson_irq_resource *meson_irq = meson_get_irq_res(); + struct meson_pinctrl_private *priv; const struct of_device_id *match; struct device *dev = &pdev->dev; struct meson_pinctrl *pc; @@ -963,7 +1171,8 @@ static int meson_pinctrl_probe(struct platform_device *pdev) pc->dev = dev; match = of_match_node(meson_pinctrl_dt_match, pdev->dev.of_node); - pc->data = (struct meson_pinctrl_data *) match->data; + priv = (struct meson_pinctrl_private *)match->data; + pc->data = (struct meson_pinctrl_data *) priv->pinctrl_data; ret = meson_pinctrl_parse_dt(pc, pdev->dev.of_node); if (ret) @@ -989,13 +1198,7 @@ static int meson_pinctrl_probe(struct platform_device *pdev) return ret; } - meson_irq_setup(pc); - - /** - *the 'meson_pinctrl_probe' will been invoked twice, - *and use the flag below to avoid allocating some resource again. - */ - meson_irq->init_flag = 1; + meson_irq_setup(pc, priv->irq_chip); return 0; } diff --git a/drivers/amlogic/pinctrl/pinctrl-meson.h b/drivers/amlogic/pinctrl/pinctrl-meson.h index f0d1339..c999ece 100644 --- a/drivers/amlogic/pinctrl/pinctrl-meson.h +++ b/drivers/amlogic/pinctrl/pinctrl-meson.h @@ -137,18 +137,16 @@ struct meson_gpio_irq_desc { unsigned int hwirq; }; -/** - *struct meson_irq_resource - describe resource for irq +/*struct meson_irq_res - describe resource for gpio irq * - *@irq_num: number of gpio irq - *@gpio_irq: a pointer to 'struct meson_gpio_irq_desc' - *@reg_irq: registers for gpio irq settings + * @irq_num: number of gpio irq + * @irq_res_lock: + * @gpio_irq: a pointer to 'struct meson_gpio_irq_desc' */ struct meson_irq_resource { unsigned char irq_num; - unsigned char init_flag; + spinlock_t irq_res_lock; struct meson_gpio_irq_desc *gpio_irq; - struct regmap *reg_irq; }; /** @@ -158,9 +156,11 @@ struct meson_irq_resource { * @reg_pullen: registers for pull-enable settings * @reg_pull: registers for pull settings * @reg_gpio: registers for gpio settings + * @reg_irq: registers for gpio irq settings * @chip: gpio chip associated with the domain - * @data; platform data for the domain - * @node: device tree node for the domain + * @irq_res: irq resource + * @data: platform data for the domain + * @node: device tree node for the domain * * A domain represents a set of banks controlled by the same set of * registers. @@ -170,8 +170,10 @@ struct meson_domain { struct regmap *reg_pullen; struct regmap *reg_pull; struct regmap *reg_gpio; + struct regmap *reg_irq; struct gpio_chip chip; + struct meson_irq_resource irq_res; struct meson_domain_data *data; struct device_node *of_node; }; @@ -186,6 +188,11 @@ struct meson_pinctrl_data { unsigned int num_funcs; }; +struct meson_pinctrl_private { + struct meson_pinctrl_data *pinctrl_data; + struct irq_chip *irq_chip; +}; + struct meson_pinctrl { struct device *dev; struct pinctrl_dev *pcdev; diff --git a/drivers/amlogic/pinctrl/pinctrl-meson8b.c b/drivers/amlogic/pinctrl/pinctrl-meson8b.c new file mode 100644 index 0000000..2949269 --- /dev/null +++ b/drivers/amlogic/pinctrl/pinctrl-meson8b.c @@ -0,0 +1,950 @@ +/* + * drivers/amlogic/pinctrl/pinctrl-meson8b.c + * + * Copyright (C) 2017 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +#include +#include "pinctrl-meson.h" + +#define AO_OFF 115 + +static const struct pinctrl_pin_desc meson8b_cbus_pins[] = { + MESON_PIN(GPIOX_0, 0), + MESON_PIN(GPIOX_1, 0), + MESON_PIN(GPIOX_2, 0), + MESON_PIN(GPIOX_3, 0), + MESON_PIN(GPIOX_4, 0), + MESON_PIN(GPIOX_5, 0), + MESON_PIN(GPIOX_6, 0), + MESON_PIN(GPIOX_7, 0), + MESON_PIN(GPIOX_8, 0), + MESON_PIN(GPIOX_9, 0), + MESON_PIN(GPIOX_10, 0), + MESON_PIN(GPIOX_11, 0), + MESON_PIN(GPIOX_16, 0), + MESON_PIN(GPIOX_17, 0), + MESON_PIN(GPIOX_18, 0), + MESON_PIN(GPIOX_19, 0), + MESON_PIN(GPIOX_20, 0), + MESON_PIN(GPIOX_21, 0), + + MESON_PIN(GPIOY_0, 0), + MESON_PIN(GPIOY_1, 0), + MESON_PIN(GPIOY_3, 0), + MESON_PIN(GPIOY_6, 0), + MESON_PIN(GPIOY_7, 0), + MESON_PIN(GPIOY_8, 0), + MESON_PIN(GPIOY_9, 0), + MESON_PIN(GPIOY_10, 0), + MESON_PIN(GPIOY_11, 0), + MESON_PIN(GPIOY_12, 0), + MESON_PIN(GPIOY_13, 0), + MESON_PIN(GPIOY_14, 0), + + MESON_PIN(GPIODV_9, 0), + MESON_PIN(GPIODV_24, 0), + MESON_PIN(GPIODV_25, 0), + MESON_PIN(GPIODV_26, 0), + MESON_PIN(GPIODV_27, 0), + MESON_PIN(GPIODV_28, 0), + MESON_PIN(GPIODV_29, 0), + + MESON_PIN(GPIOH_0, 0), + MESON_PIN(GPIOH_1, 0), + MESON_PIN(GPIOH_2, 0), + MESON_PIN(GPIOH_3, 0), + MESON_PIN(GPIOH_4, 0), + MESON_PIN(GPIOH_5, 0), + MESON_PIN(GPIOH_6, 0), + MESON_PIN(GPIOH_7, 0), + MESON_PIN(GPIOH_8, 0), + MESON_PIN(GPIOH_9, 0), + + MESON_PIN(CARD_0, 0), + MESON_PIN(CARD_1, 0), + MESON_PIN(CARD_2, 0), + MESON_PIN(CARD_3, 0), + MESON_PIN(CARD_4, 0), + MESON_PIN(CARD_5, 0), + MESON_PIN(CARD_6, 0), + + MESON_PIN(BOOT_0, 0), + MESON_PIN(BOOT_1, 0), + MESON_PIN(BOOT_2, 0), + MESON_PIN(BOOT_3, 0), + MESON_PIN(BOOT_4, 0), + MESON_PIN(BOOT_5, 0), + MESON_PIN(BOOT_6, 0), + MESON_PIN(BOOT_7, 0), + MESON_PIN(BOOT_8, 0), + MESON_PIN(BOOT_9, 0), + MESON_PIN(BOOT_10, 0), + MESON_PIN(BOOT_11, 0), + MESON_PIN(BOOT_12, 0), + MESON_PIN(BOOT_13, 0), + MESON_PIN(BOOT_14, 0), + MESON_PIN(BOOT_15, 0), + MESON_PIN(BOOT_16, 0), + MESON_PIN(BOOT_17, 0), + MESON_PIN(BOOT_18, 0), + + MESON_PIN(DIF_0_P, 0), + MESON_PIN(DIF_0_N, 0), + MESON_PIN(DIF_1_P, 0), + MESON_PIN(DIF_1_N, 0), + MESON_PIN(DIF_2_P, 0), + MESON_PIN(DIF_2_N, 0), + MESON_PIN(DIF_3_P, 0), + MESON_PIN(DIF_3_N, 0), + MESON_PIN(DIF_4_P, 0), + MESON_PIN(DIF_4_N, 0), +}; + +static const struct pinctrl_pin_desc meson8b_aobus_pins[] = { + MESON_PIN(GPIOAO_0, AO_OFF), + MESON_PIN(GPIOAO_1, AO_OFF), + MESON_PIN(GPIOAO_2, AO_OFF), + MESON_PIN(GPIOAO_3, AO_OFF), + MESON_PIN(GPIOAO_4, AO_OFF), + MESON_PIN(GPIOAO_5, AO_OFF), + MESON_PIN(GPIOAO_6, AO_OFF), + MESON_PIN(GPIOAO_7, AO_OFF), + MESON_PIN(GPIOAO_8, AO_OFF), + MESON_PIN(GPIOAO_9, AO_OFF), + MESON_PIN(GPIOAO_10, AO_OFF), + MESON_PIN(GPIOAO_11, AO_OFF), + MESON_PIN(GPIOAO_12, AO_OFF), + MESON_PIN(GPIOAO_13, AO_OFF), + MESON_PIN(GPIO_BSD_EN, AO_OFF), + MESON_PIN(GPIO_TEST_N, AO_OFF), +}; + +/* bank X */ +static const unsigned int sd_d0_a_pins[] = { PIN(GPIOX_0, 0) }; +static const unsigned int sd_d1_a_pins[] = { PIN(GPIOX_1, 0) }; +static const unsigned int sd_d2_a_pins[] = { PIN(GPIOX_2, 0) }; +static const unsigned int sd_d3_a_pins[] = { PIN(GPIOX_3, 0) }; +static const unsigned int sdxc_d0_0_a_pins[] = { PIN(GPIOX_4, 0) }; +static const unsigned int sdxc_d47_a_pins[] = { PIN(GPIOX_4, 0), + PIN(GPIOX_5, 0), PIN(GPIOX_6, 0), PIN(GPIOX_7, 0) }; +static const unsigned int sdxc_d13_0_a_pins[] = { PIN(GPIOX_5, 0), + PIN(GPIOX_6, 0), PIN(GPIOX_7, 0) }; +static const unsigned int sd_clk_a_pins[] = { PIN(GPIOX_8, 0) }; +static const unsigned int sd_cmd_a_pins[] = { PIN(GPIOX_9, 0) }; +static const unsigned int xtal_32k_out_pins[] = { PIN(GPIOX_10, 0) }; +static const unsigned int xtal_24m_out_pins[] = { PIN(GPIOX_11, 0) }; +static const unsigned int uart_tx_b0_pins[] = { PIN(GPIOX_16, 0) }; +static const unsigned int uart_rx_b0_pins[] = { PIN(GPIOX_17, 0) }; +static const unsigned int uart_cts_b0_pins[] = { PIN(GPIOX_18, 0) }; +static const unsigned int uart_rts_b0_pins[] = { PIN(GPIOX_19, 0) }; + +static const unsigned int sdxc_d0_1_a_pins[] = { PIN(GPIOX_0, 0) }; +static const unsigned int sdxc_d13_1_a_pins[] = { PIN(GPIOX_1, 0), + PIN(GPIOX_2, 0), PIN(GPIOX_3, 0) }; +static const unsigned int pcm_out_a_pins[] = { PIN(GPIOX_4, 0) }; +static const unsigned int pcm_in_a_pins[] = { PIN(GPIOX_5, 0) }; +static const unsigned int pcm_fs_a_pins[] = { PIN(GPIOX_6, 0) }; +static const unsigned int pcm_clk_a_pins[] = { PIN(GPIOX_7, 0) }; +static const unsigned int sdxc_clk_a_pins[] = { PIN(GPIOX_8, 0) }; +static const unsigned int sdxc_cmd_a_pins[] = { PIN(GPIOX_9, 0) }; +static const unsigned int pwm_vs_0_pins[] = { PIN(GPIOX_10, 0) }; +static const unsigned int pwm_e_pins[] = { PIN(GPIOX_10, 0) }; +static const unsigned int pwm_vs_1_pins[] = { PIN(GPIOX_11, 0) }; + +static const unsigned int uart_tx_a_pins[] = { PIN(GPIOX_4, 0) }; +static const unsigned int uart_rx_a_pins[] = { PIN(GPIOX_5, 0) }; +static const unsigned int uart_cts_a_pins[] = { PIN(GPIOX_6, 0) }; +static const unsigned int uart_rts_a_pins[] = { PIN(GPIOX_7, 0) }; +static const unsigned int uart_tx_b1_pins[] = { PIN(GPIOX_8, 0) }; +static const unsigned int uart_rx_b1_pins[] = { PIN(GPIOX_9, 0) }; +static const unsigned int uart_cts_b1_pins[] = { PIN(GPIOX_10, 0) }; +static const unsigned int uart_rts_b1_pins[] = { PIN(GPIOX_20, 0) }; + +static const unsigned int iso7816_0_clk_pins[] = { PIN(GPIOX_6, 0) }; +static const unsigned int iso7816_0_data_pins[] = { PIN(GPIOX_7, 0) }; +static const unsigned int spi_sclk_0_pins[] = { PIN(GPIOX_8, 0) }; +static const unsigned int spi_miso_0_pins[] = { PIN(GPIOX_9, 0) }; +static const unsigned int spi_mosi_0_pins[] = { PIN(GPIOX_10, 0) }; +static const unsigned int iso7816_det_pins[] = { PIN(GPIOX_16, 0) }; +static const unsigned int iso7816_reset_pins[] = { PIN(GPIOX_17, 0) }; +static const unsigned int iso7816_1_clk_pins[] = { PIN(GPIOX_18, 0) }; +static const unsigned int iso7816_1_data_pins[] = { PIN(GPIOX_19, 0) }; +static const unsigned int spi_ss0_0_pins[] = { PIN(GPIOX_20, 0) }; + +static const unsigned int tsin_clk_b_pins[] = { PIN(GPIOX_8, 0) }; +static const unsigned int tsin_sop_b_pins[] = { PIN(GPIOX_9, 0) }; +static const unsigned int tsin_d0_b_pins[] = { PIN(GPIOX_10, 0) }; +static const unsigned int pwm_b_pins[] = { PIN(GPIOX_11, 0) }; +static const unsigned int i2c_sda_d0_pins[] = { PIN(GPIOX_16, 0) }; +static const unsigned int i2c_sck_d0_pins[] = { PIN(GPIOX_17, 0) }; +static const unsigned int tsin_d_valid_b_pins[] = { PIN(GPIOX_20, 0) }; + +/* bank Y */ +static const unsigned int tsin_d_valid_a_pins[] = { PIN(GPIOY_0, 0) }; +static const unsigned int tsin_sop_a_pins[] = { PIN(GPIOY_1, 0) }; +static const unsigned int tsin_d17_a_pins[] = { PIN(GPIOY_6, 0), + PIN(GPIOY_7, 0), PIN(GPIOY_10, 0), PIN(GPIOY_11, 0), + PIN(GPIOY_12, 0), PIN(GPIOY_13, 0), PIN(GPIOY_14, 0) }; +static const unsigned int tsin_clk_a_pins[] = { PIN(GPIOY_8, 0) }; +static const unsigned int tsin_d0_a_pins[] = { PIN(GPIOY_9, 0) }; + +static const unsigned int spdif_out_0_pins[] = { PIN(GPIOY_3, 0) }; + +static const unsigned int xtal_24m_pins[] = { PIN(GPIOY_3, 0) }; +static const unsigned int iso7816_2_clk_pins[] = { PIN(GPIOY_13, 0) }; +static const unsigned int iso7816_2_data_pins[] = { PIN(GPIOY_14, 0) }; + +/* bank DV */ +static const unsigned int pwm_d_pins[] = { PIN(GPIODV_28, 0) }; +static const unsigned int pwm_c0_pins[] = { PIN(GPIODV_29, 0) }; + +static const unsigned int pwm_vs_2_pins[] = { PIN(GPIODV_9, 0) }; +static const unsigned int pwm_vs_3_pins[] = { PIN(GPIODV_28, 0) }; +static const unsigned int pwm_vs_4_pins[] = { PIN(GPIODV_29, 0) }; + +static const unsigned int xtal24_out_pins[] = { PIN(GPIODV_29, 0) }; + +static const unsigned int uart_tx_c_pins[] = { PIN(GPIODV_24, 0) }; +static const unsigned int uart_rx_c_pins[] = { PIN(GPIODV_25, 0) }; +static const unsigned int uart_cts_c_pins[] = { PIN(GPIODV_26, 0) }; +static const unsigned int uart_rts_c_pins[] = { PIN(GPIODV_27, 0) }; + +static const unsigned int pwm_c1_pins[] = { PIN(GPIODV_9, 0) }; + +static const unsigned int i2c_sda_a_pins[] = { PIN(GPIODV_24, 0) }; +static const unsigned int i2c_sck_a_pins[] = { PIN(GPIODV_25, 0) }; +static const unsigned int i2c_sda_b0_pins[] = { PIN(GPIODV_26, 0) }; +static const unsigned int i2c_sck_b0_pins[] = { PIN(GPIODV_27, 0) }; +static const unsigned int i2c_sda_c0_pins[] = { PIN(GPIODV_28, 0) }; +static const unsigned int i2c_sck_c0_pins[] = { PIN(GPIODV_29, 0) }; + +/* bank H */ +static const unsigned int hdmi_hpd_pins[] = { PIN(GPIOH_0, 0) }; +static const unsigned int hdmi_sda_pins[] = { PIN(GPIOH_1, 0) }; +static const unsigned int hdmi_scl_pins[] = { PIN(GPIOH_2, 0) }; +static const unsigned int hdmi_cec_0_pins[] = { PIN(GPIOH_3, 0) }; +static const unsigned int eth_txd1_0_pins[] = { PIN(GPIOH_5, 0) }; +static const unsigned int eth_txd0_0_pins[] = { PIN(GPIOH_6, 0) }; +static const unsigned int clk_24m_out_pins[] = { PIN(GPIOH_9, 0) }; + +static const unsigned int spi_ss1_pins[] = { PIN(GPIOH_0, 0) }; +static const unsigned int spi_ss2_pins[] = { PIN(GPIOH_1, 0) }; +static const unsigned int spi_ss0_1_pins[] = { PIN(GPIOH_3, 0) }; +static const unsigned int spi_miso_1_pins[] = { PIN(GPIOH_4, 0) }; +static const unsigned int spi_mosi_1_pins[] = { PIN(GPIOH_5, 0) }; +static const unsigned int spi_sclk_1_pins[] = { PIN(GPIOH_6, 0) }; + +static const unsigned int eth_txd3_pins[] = { PIN(GPIOH_7, 0) }; +static const unsigned int eth_txd2_pins[] = { PIN(GPIOH_8, 0) }; +static const unsigned int eth_tx_clk_pins[] = { PIN(GPIOH_9, 0) }; + +static const unsigned int i2c_sda_b1_pins[] = { PIN(GPIOH_3, 0) }; +static const unsigned int i2c_sck_b1_pins[] = { PIN(GPIOH_4, 0) }; +static const unsigned int i2c_sda_c1_pins[] = { PIN(GPIOH_5, 0) }; +static const unsigned int i2c_sck_c1_pins[] = { PIN(GPIOH_6, 0) }; +static const unsigned int i2c_sda_d1_pins[] = { PIN(GPIOH_7, 0) }; +static const unsigned int i2c_sck_d1_pins[] = { PIN(GPIOH_8, 0) }; + +/* bank BOOT */ +static const unsigned int nand_io_pins[] = { PIN(BOOT_0, 0), + PIN(BOOT_1, 0), PIN(BOOT_2, 0), PIN(BOOT_3, 0), + PIN(BOOT_4, 0), PIN(BOOT_5, 0), PIN(BOOT_6, 0), + PIN(BOOT_7, 0) }; +static const unsigned int nand_io_ce0_pins[] = { PIN(BOOT_8, 0) }; +static const unsigned int nand_io_ce1_pins[] = { PIN(BOOT_9, 0) }; +static const unsigned int nand_io_rb0_pins[] = { PIN(BOOT_10, 0) }; +static const unsigned int nand_ale_pins[] = { PIN(BOOT_11, 0) }; +static const unsigned int nand_cle_pins[] = { PIN(BOOT_12, 0) }; +static const unsigned int nand_wen_clk_pins[] = { PIN(BOOT_13, 0) }; +static const unsigned int nand_ren_clk_pins[] = { PIN(BOOT_14, 0) }; +static const unsigned int nand_dqs_0_pins[] = { PIN(BOOT_15, 0) }; +static const unsigned int nand_dqs_1_pins[] = { PIN(BOOT_18, 0) }; + +static const unsigned int sdxc_d0_c_pins[] = { PIN(BOOT_0, 0)}; +static const unsigned int sdxc_d13_c_pins[] = { PIN(BOOT_1, 0), + PIN(BOOT_2, 0), PIN(BOOT_3, 0) }; +static const unsigned int sdxc_d47_c_pins[] = { PIN(BOOT_4, 0), + PIN(BOOT_5, 0), PIN(BOOT_6, 0), PIN(BOOT_7, 0) }; +static const unsigned int sdxc_clk_c_pins[] = { PIN(BOOT_8, 0) }; +static const unsigned int sdxc_cmd_c_pins[] = { PIN(BOOT_10, 0) }; +static const unsigned int nor_d_pins[] = { PIN(BOOT_11, 0) }; +static const unsigned int nor_q_pins[] = { PIN(BOOT_12, 0) }; +static const unsigned int nor_c_pins[] = { PIN(BOOT_13, 0) }; +static const unsigned int nor_cs_pins[] = { PIN(BOOT_18, 0) }; + +static const unsigned int sd_d0_c_pins[] = { PIN(BOOT_0, 0) }; +static const unsigned int sd_d1_c_pins[] = { PIN(BOOT_1, 0) }; +static const unsigned int sd_d2_c_pins[] = { PIN(BOOT_2, 0) }; +static const unsigned int sd_d3_c_pins[] = { PIN(BOOT_3, 0) }; +static const unsigned int sd_cmd_c_pins[] = { PIN(BOOT_8, 0) }; +static const unsigned int sd_clk_c_pins[] = { PIN(BOOT_10, 0) }; + +/* bank CARD */ +static const unsigned int sd_d1_b_pins[] = { PIN(CARD_0, 0) }; +static const unsigned int sd_d0_b_pins[] = { PIN(CARD_1, 0) }; +static const unsigned int sd_clk_b_pins[] = { PIN(CARD_2, 0) }; +static const unsigned int sd_cmd_b_pins[] = { PIN(CARD_3, 0) }; +static const unsigned int sd_d3_b_pins[] = { PIN(CARD_4, 0) }; +static const unsigned int sd_d2_b_pins[] = { PIN(CARD_5, 0) }; + +static const unsigned int sdxc_d13_b_pins[] = { PIN(CARD_0, 0), + PIN(CARD_4, 0), PIN(CARD_5, 0) }; +static const unsigned int sdxc_d0_b_pins[] = { PIN(CARD_1, 0) }; +static const unsigned int sdxc_clk_b_pins[] = { PIN(CARD_2, 0) }; +static const unsigned int sdxc_cmd_b_pins[] = { PIN(CARD_3, 0) }; + +/* bank AO */ +static const unsigned int uart_tx_ao_a_pins[] = { PIN(GPIOAO_0, AO_OFF) }; +static const unsigned int uart_rx_ao_a_pins[] = { PIN(GPIOAO_1, AO_OFF) }; +static const unsigned int uart_cts_ao_a_pins[] = { PIN(GPIOAO_2, AO_OFF) }; +static const unsigned int uart_rts_ao_a_pins[] = { PIN(GPIOAO_3, AO_OFF) }; +static const unsigned int i2c_mst_sck_ao_pins[] = { PIN(GPIOAO_4, AO_OFF) }; +static const unsigned int i2c_mst_sda_ao_pins[] = { PIN(GPIOAO_5, AO_OFF) }; +static const unsigned int clk_32k_in_out_pins[] = { PIN(GPIOAO_6, AO_OFF) }; +static const unsigned int remote_input_pins[] = { PIN(GPIOAO_7, AO_OFF) }; +static const unsigned int hdmi_cec_1_pins[] = { PIN(GPIOAO_12, AO_OFF) }; +static const unsigned int ir_blaster_pins[] = { PIN(GPIOAO_13, AO_OFF) }; + +static const unsigned int pwm_c2_pins[] = { PIN(GPIOAO_3, AO_OFF) }; +static const unsigned int i2c_sck_ao_pins[] = { PIN(GPIOAO_4, AO_OFF) }; +static const unsigned int i2c_sda_ao_pins[] = { PIN(GPIOAO_5, AO_OFF) }; +static const unsigned int ir_remote_out_pins[] = { PIN(GPIOAO_7, AO_OFF) }; +static const unsigned int i2s_am_clk_out_pins[] = { PIN(GPIOAO_8, AO_OFF) }; +static const unsigned int i2s_ao_clk_out_pins[] = { PIN(GPIOAO_9, AO_OFF) }; +static const unsigned int i2s_lr_clk_out_pins[] = { PIN(GPIOAO_10, AO_OFF) }; +static const unsigned int i2s_out_01_pins[] = { PIN(GPIOAO_11, AO_OFF) }; + +static const unsigned int uart_tx_ao_b0_pins[] = { PIN(GPIOAO_0, AO_OFF) }; +static const unsigned int uart_rx_ao_b0_pins[] = { PIN(GPIOAO_1, AO_OFF) }; +static const unsigned int uart_cts_ao_b_pins[] = { PIN(GPIOAO_2, AO_OFF) }; +static const unsigned int uart_rts_ao_b_pins[] = { PIN(GPIOAO_3, AO_OFF) }; +static const unsigned int uart_tx_ao_b1_pins[] = { PIN(GPIOAO_4, AO_OFF) }; +static const unsigned int uart_rx_ao_b1_pins[] = { PIN(GPIOAO_5, AO_OFF) }; +static const unsigned int spdif_out_1_pins[] = { PIN(GPIOAO_6, AO_OFF) }; + +static const unsigned int i2s_in_ch01_pins[] = { PIN(GPIOAO_6, AO_OFF) }; +static const unsigned int i2s_ao_clk_in_pins[] = { PIN(GPIOAO_9, AO_OFF) }; +static const unsigned int i2s_lr_clk_in_pins[] = { PIN(GPIOAO_10, AO_OFF) }; + +/* bank DIF */ +static const unsigned int eth_rxd1_pins[] = { PIN(DIF_0_P, 0) }; +static const unsigned int eth_rxd0_pins[] = { PIN(DIF_0_N, 0) }; +static const unsigned int eth_rx_dv_pins[] = { PIN(DIF_1_P, 0) }; +static const unsigned int eth_rx_clk_pins[] = { PIN(DIF_1_N, 0) }; +static const unsigned int eth_txd0_1_pins[] = { PIN(DIF_2_P, 0) }; +static const unsigned int eth_txd1_1_pins[] = { PIN(DIF_2_N, 0) }; +static const unsigned int eth_tx_en_pins[] = { PIN(DIF_3_P, 0) }; +static const unsigned int eth_ref_clk_pins[] = { PIN(DIF_3_N, 0) }; +static const unsigned int eth_mdc_pins[] = { PIN(DIF_4_P, 0) }; +static const unsigned int eth_mdio_en_pins[] = { PIN(DIF_4_N, 0) }; + +static struct meson_pmx_group meson8b_cbus_groups[] = { + GPIO_GROUP(GPIOX_0, 0), + GPIO_GROUP(GPIOX_1, 0), + GPIO_GROUP(GPIOX_2, 0), + GPIO_GROUP(GPIOX_3, 0), + GPIO_GROUP(GPIOX_4, 0), + GPIO_GROUP(GPIOX_5, 0), + GPIO_GROUP(GPIOX_6, 0), + GPIO_GROUP(GPIOX_7, 0), + GPIO_GROUP(GPIOX_8, 0), + GPIO_GROUP(GPIOX_9, 0), + GPIO_GROUP(GPIOX_10, 0), + GPIO_GROUP(GPIOX_11, 0), + GPIO_GROUP(GPIOX_16, 0), + GPIO_GROUP(GPIOX_17, 0), + GPIO_GROUP(GPIOX_18, 0), + GPIO_GROUP(GPIOX_19, 0), + GPIO_GROUP(GPIOX_20, 0), + GPIO_GROUP(GPIOX_21, 0), + + GPIO_GROUP(GPIOY_0, 0), + GPIO_GROUP(GPIOY_1, 0), + GPIO_GROUP(GPIOY_3, 0), + GPIO_GROUP(GPIOY_6, 0), + GPIO_GROUP(GPIOY_7, 0), + GPIO_GROUP(GPIOY_8, 0), + GPIO_GROUP(GPIOY_9, 0), + GPIO_GROUP(GPIOY_10, 0), + GPIO_GROUP(GPIOY_11, 0), + GPIO_GROUP(GPIOY_12, 0), + GPIO_GROUP(GPIOY_13, 0), + GPIO_GROUP(GPIOY_14, 0), + + GPIO_GROUP(GPIODV_9, 0), + GPIO_GROUP(GPIODV_24, 0), + GPIO_GROUP(GPIODV_25, 0), + GPIO_GROUP(GPIODV_26, 0), + GPIO_GROUP(GPIODV_27, 0), + GPIO_GROUP(GPIODV_28, 0), + GPIO_GROUP(GPIODV_29, 0), + + GPIO_GROUP(GPIOH_0, 0), + GPIO_GROUP(GPIOH_1, 0), + GPIO_GROUP(GPIOH_2, 0), + GPIO_GROUP(GPIOH_3, 0), + GPIO_GROUP(GPIOH_4, 0), + GPIO_GROUP(GPIOH_5, 0), + GPIO_GROUP(GPIOH_6, 0), + GPIO_GROUP(GPIOH_7, 0), + GPIO_GROUP(GPIOH_8, 0), + GPIO_GROUP(GPIOH_9, 0), + + GPIO_GROUP(DIF_0_P, 0), + GPIO_GROUP(DIF_0_N, 0), + GPIO_GROUP(DIF_1_P, 0), + GPIO_GROUP(DIF_1_N, 0), + GPIO_GROUP(DIF_2_P, 0), + GPIO_GROUP(DIF_2_N, 0), + GPIO_GROUP(DIF_3_P, 0), + GPIO_GROUP(DIF_3_N, 0), + GPIO_GROUP(DIF_4_P, 0), + GPIO_GROUP(DIF_4_N, 0), + + /* bank X */ + GROUP(sd_d0_a, 8, 5), + GROUP(sd_d1_a, 8, 4), + GROUP(sd_d2_a, 8, 3), + GROUP(sd_d3_a, 8, 2), + GROUP(sdxc_d0_0_a, 5, 29), + GROUP(sdxc_d47_a, 5, 12), + GROUP(sdxc_d13_0_a, 5, 28), + GROUP(sd_clk_a, 8, 1), + GROUP(sd_cmd_a, 8, 0), + GROUP(xtal_32k_out, 3, 22), + GROUP(xtal_24m_out, 3, 20), + GROUP(uart_tx_b0, 4, 9), + GROUP(uart_rx_b0, 4, 8), + GROUP(uart_cts_b0, 4, 7), + GROUP(uart_rts_b0, 4, 6), + GROUP(sdxc_d0_1_a, 5, 14), + GROUP(sdxc_d13_1_a, 5, 13), + GROUP(pcm_out_a, 3, 30), + GROUP(pcm_in_a, 3, 29), + GROUP(pcm_fs_a, 3, 28), + GROUP(pcm_clk_a, 3, 27), + GROUP(sdxc_clk_a, 5, 11), + GROUP(sdxc_cmd_a, 5, 10), + GROUP(pwm_vs_0, 7, 31), + GROUP(pwm_e, 9, 19), + GROUP(pwm_vs_1, 7, 30), + GROUP(uart_tx_a, 4, 17), + GROUP(uart_rx_a, 4, 16), + GROUP(uart_cts_a, 4, 15), + GROUP(uart_rts_a, 4, 14), + GROUP(uart_tx_b1, 6, 19), + GROUP(uart_rx_b1, 6, 18), + GROUP(uart_cts_b1, 6, 17), + GROUP(uart_rts_b1, 6, 16), + GROUP(iso7816_0_clk, 5, 9), + GROUP(iso7816_0_data, 5, 8), + GROUP(spi_sclk_0, 4, 22), + GROUP(spi_miso_0, 4, 24), + GROUP(spi_mosi_0, 4, 23), + GROUP(iso7816_det, 4, 21), + GROUP(iso7816_reset, 4, 20), + GROUP(iso7816_1_clk, 4, 19), + GROUP(iso7816_1_data, 4, 18), + GROUP(spi_ss0_0, 4, 25), + GROUP(tsin_clk_b, 3, 6), + GROUP(tsin_sop_b, 3, 7), + GROUP(tsin_d0_b, 3, 8), + GROUP(pwm_b, 2, 3), + GROUP(i2c_sda_d0, 4, 5), + GROUP(i2c_sck_d0, 4, 4), + GROUP(tsin_d_valid_b, 3, 9), + + /* bank Y */ + GROUP(tsin_d_valid_a, 3, 2), + GROUP(tsin_sop_a, 3, 1), + GROUP(tsin_d17_a, 3, 5), + GROUP(tsin_clk_a, 3, 0), + GROUP(tsin_d0_a, 3, 4), + GROUP(spdif_out_0, 1, 7), + GROUP(xtal_24m, 3, 18), + GROUP(iso7816_2_clk, 5, 7), + GROUP(iso7816_2_data, 5, 6), + + /* bank DV */ + GROUP(pwm_d, 3, 26), + GROUP(pwm_c0, 3, 25), + GROUP(pwm_vs_2, 7, 28), + GROUP(pwm_vs_3, 7, 27), + GROUP(pwm_vs_4, 7, 26), + GROUP(xtal24_out, 7, 25), + GROUP(uart_tx_c, 6, 23), + GROUP(uart_rx_c, 6, 22), + GROUP(uart_cts_c, 6, 21), + GROUP(uart_rts_c, 6, 20), + GROUP(pwm_c1, 3, 24), + GROUP(i2c_sda_a, 9, 31), + GROUP(i2c_sck_a, 9, 30), + GROUP(i2c_sda_b0, 9, 29), + GROUP(i2c_sck_b0, 9, 28), + GROUP(i2c_sda_c0, 9, 27), + GROUP(i2c_sck_c0, 9, 26), + + /* bank H */ + GROUP(hdmi_hpd, 1, 26), + GROUP(hdmi_sda, 1, 25), + GROUP(hdmi_scl, 1, 24), + GROUP(hdmi_cec_0, 1, 23), + GROUP(eth_txd1_0, 7, 21), + GROUP(eth_txd0_0, 7, 20), + GROUP(clk_24m_out, 4, 1), + GROUP(spi_ss1, 8, 11), + GROUP(spi_ss2, 8, 12), + GROUP(spi_ss0_1, 9, 13), + GROUP(spi_miso_1, 9, 12), + GROUP(spi_mosi_1, 9, 11), + GROUP(spi_sclk_1, 9, 10), + GROUP(eth_txd3, 6, 13), + GROUP(eth_txd2, 6, 12), + GROUP(eth_tx_clk, 6, 11), + GROUP(i2c_sda_b1, 5, 27), + GROUP(i2c_sck_b1, 5, 26), + GROUP(i2c_sda_c1, 5, 25), + GROUP(i2c_sck_c1, 5, 24), + GROUP(i2c_sda_d1, 4, 3), + GROUP(i2c_sck_d1, 4, 2), + + /* bank BOOT */ + GROUP(nand_io, 2, 26), + GROUP(nand_io_ce0, 2, 25), + GROUP(nand_io_ce1, 2, 24), + GROUP(nand_io_rb0, 2, 17), + GROUP(nand_ale, 2, 21), + GROUP(nand_cle, 2, 20), + GROUP(nand_wen_clk, 2, 19), + GROUP(nand_ren_clk, 2, 18), + GROUP(nand_dqs_0, 2, 27), + GROUP(nand_dqs_1, 2, 28), + GROUP(sdxc_d0_c, 4, 30), + GROUP(sdxc_d13_c, 4, 29), + GROUP(sdxc_d47_c, 4, 28), + GROUP(sdxc_clk_c, 7, 19), + GROUP(sdxc_cmd_c, 7, 18), + GROUP(nor_d, 5, 1), + GROUP(nor_q, 5, 3), + GROUP(nor_c, 5, 2), + GROUP(nor_cs, 5, 0), + GROUP(sd_d0_c, 6, 29), + GROUP(sd_d1_c, 6, 28), + GROUP(sd_d2_c, 6, 27), + GROUP(sd_d3_c, 6, 26), + GROUP(sd_cmd_c, 6, 30), + GROUP(sd_clk_c, 6, 31), + + /* bank CARD */ + GROUP(sd_d1_b, 2, 14), + GROUP(sd_d0_b, 2, 15), + GROUP(sd_clk_b, 2, 11), + GROUP(sd_cmd_b, 2, 10), + GROUP(sd_d3_b, 2, 12), + GROUP(sd_d2_b, 2, 13), + GROUP(sdxc_d13_b, 2, 6), + GROUP(sdxc_d0_b, 2, 7), + GROUP(sdxc_clk_b, 2, 5), + GROUP(sdxc_cmd_b, 2, 4), + + /* bank DIF */ + GROUP(eth_rxd1, 6, 0), + GROUP(eth_rxd0, 6, 1), + GROUP(eth_rx_dv, 6, 2), + GROUP(eth_rx_clk, 6, 3), + GROUP(eth_txd0_1, 6, 4), + GROUP(eth_txd1_1, 6, 5), + GROUP(eth_tx_en, 6, 6), + GROUP(eth_ref_clk, 6, 8), + GROUP(eth_mdc, 6, 9), + GROUP(eth_mdio_en, 6, 10), +}; + +static struct meson_pmx_group meson8b_aobus_groups[] = { + GPIO_GROUP(GPIOAO_0, AO_OFF), + GPIO_GROUP(GPIOAO_1, AO_OFF), + GPIO_GROUP(GPIOAO_2, AO_OFF), + GPIO_GROUP(GPIOAO_3, AO_OFF), + GPIO_GROUP(GPIOAO_4, AO_OFF), + GPIO_GROUP(GPIOAO_5, AO_OFF), + GPIO_GROUP(GPIOAO_6, AO_OFF), + GPIO_GROUP(GPIOAO_7, AO_OFF), + GPIO_GROUP(GPIOAO_8, AO_OFF), + GPIO_GROUP(GPIOAO_9, AO_OFF), + GPIO_GROUP(GPIOAO_10, AO_OFF), + GPIO_GROUP(GPIOAO_11, AO_OFF), + GPIO_GROUP(GPIOAO_12, AO_OFF), + GPIO_GROUP(GPIOAO_13, AO_OFF), + GPIO_GROUP(GPIO_BSD_EN, AO_OFF), + GPIO_GROUP(GPIO_TEST_N, AO_OFF), + + /* bank AO */ + GROUP(uart_tx_ao_a, 0, 12), + GROUP(uart_rx_ao_a, 0, 11), + GROUP(uart_cts_ao_a, 0, 10), + GROUP(uart_rts_ao_a, 0, 9), + GROUP(i2c_mst_sck_ao, 0, 6), + GROUP(i2c_mst_sda_ao, 0, 5), + GROUP(clk_32k_in_out, 0, 18), + GROUP(remote_input, 0, 0), + GROUP(hdmi_cec_1, 0, 17), + GROUP(ir_blaster, 0, 31), + GROUP(pwm_c2, 0, 22), + GROUP(i2c_sck_ao, 0, 2), + GROUP(i2c_sda_ao, 0, 1), + GROUP(ir_remote_out, 0, 21), + GROUP(i2s_am_clk_out, 0, 30), + GROUP(i2s_ao_clk_out, 0, 29), + GROUP(i2s_lr_clk_out, 0, 28), + GROUP(i2s_out_01, 0, 27), + GROUP(uart_tx_ao_b0, 0, 26), + GROUP(uart_rx_ao_b0, 0, 25), + GROUP(uart_cts_ao_b, 0, 8), + GROUP(uart_rts_ao_b, 0, 7), + GROUP(uart_tx_ao_b1, 0, 24), + GROUP(uart_rx_ao_b1, 0, 23), + GROUP(spdif_out_1, 0, 16), + GROUP(i2s_in_ch01, 0, 13), + GROUP(i2s_ao_clk_in, 0, 15), + GROUP(i2s_lr_clk_in, 0, 14), +}; + +static const char * const gpio_groups[] = { + "GPIOX_0", "GPIOX_1", "GPIOX_2", "GPIOX_3", "GPIOX_4", + "GPIOX_5", "GPIOX_6", "GPIOX_7", "GPIOX_8", "GPIOX_9", + "GPIOX_10", "GPIOX_11", "GPIOX_16", "GPIOX_17", "GPIOX_18", + "GPIOX_19", "GPIOX_20", "GPIOX_21", + + "GPIOY_0", "GPIOY_1", "GPIOY_3", "GPIOY_6", "GPIOY_7", + "GPIOY_8", "GPIOY_9", "GPIOY_10", "GPIOY_11", "GPIOY_12", + "GPIOY_13", "GPIOY_14", + + "GPIODV_9", "GPIODV_24", "GPIODV_25", "GPIODV_26", + "GPIODV_27", "GPIODV_28", "GPIODV_29", + + "GPIOH_0", "GPIOH_1", "GPIOH_2", "GPIOH_3", "GPIOH_4", + "GPIOH_5", "GPIOH_6", "GPIOH_7", "GPIOH_8", "GPIOH_9", + + "CARD_0", "CARD_1", "CARD_2", "CARD_3", "CARD_4", + "CARD_5", "CARD_6", + + "BOOT_0", "BOOT_1", "BOOT_2", "BOOT_3", "BOOT_4", + "BOOT_5", "BOOT_6", "BOOT_7", "BOOT_8", "BOOT_9", + "BOOT_10", "BOOT_11", "BOOT_12", "BOOT_13", "BOOT_14", + "BOOT_15", "BOOT_16", "BOOT_17", "BOOT_18", + + "GPIOAO_0", "GPIOAO_1", "GPIOAO_2", "GPIOAO_3", + "GPIOAO_4", "GPIOAO_5", "GPIOAO_6", "GPIOAO_7", + "GPIOAO_8", "GPIOAO_9", "GPIOAO_10", "GPIOAO_11", + "GPIOAO_12", "GPIOAO_13", "GPIO_BSD_EN", "GPIO_TEST_N", + + "DIF_0_P", "DIF_0_N", "DIF_1_P", "DIF_1_N", + "DIF_2_P", "DIF_2_N", "DIF_3_P", "DIF_3_N", + "DIF_4_P", "DIF_4_N" +}; + +static const char * const sd_a_groups[] = { + "sd_d0_a", "sd_d1_a", "sd_d2_a", "sd_d3_a", "sd_clk_a", + "sd_cmd_a" +}; + +static const char * const sdxc_a_groups[] = { + "sdxc_d0_0_a", "sdxc_d13_0_a", "sdxc_d47_a", "sdxc_clk_a", + "sdxc_cmd_a", "sdxc_d0_1_a", "sdxc_d13_1_a" +}; + +static const char * const pcm_a_groups[] = { + "pcm_out_a", "pcm_in_a", "pcm_fs_a", "pcm_clk_a" +}; + +static const char * const uart_a_groups[] = { + "uart_tx_a", "uart_rx_a", "uart_cts_a", "uart_rts_a" +}; + +static const char * const uart_b_groups[] = { + "uart_tx_b0", "uart_rx_b0", "uart_cts_b0", "uart_rts_b0", + "uart_tx_b1", "uart_rx_b1", "uart_cts_b1", "uart_rts_b1" +}; + +static const char * const iso7816_groups[] = { + "iso7816_det", "iso7816_reset", "iso7816_0_clk", "iso7816_0_data", + "iso7816_1_clk", "iso7816_1_data", "iso7816_2_clk", "iso7816_2_data" +}; + +static const char * const i2c_d_groups[] = { + "i2c_sda_d0", "i2c_sck_d0", "i2c_sda_d1", "i2c_sck_d1" +}; + +static const char * const xtal_groups[] = { + "xtal_32k_out", "xtal_24m_out", "xtal_24m", "xtal24_out" +}; + +static const char * const uart_c_groups[] = { + "uart_tx_c", "uart_rx_c", "uart_cts_c", "uart_rts_c" +}; + +static const char * const i2c_c_groups[] = { + "i2c_sda_c0", "i2c_sck_c0", "i2c_sda_c1", "i2c_sck_c1" +}; + +static const char * const hdmi_groups[] = { + "hdmi_hpd", "hdmi_sda", "hdmi_scl", "hdmi_cec_0" +}; + +static const char * const hdmi_cec_groups[] = { + "hdmi_cec_1" +}; + +static const char * const spi_groups[] = { + "spi_ss0_0", "spi_miso_0", "spi_mosi_0", "spi_sclk_0", + "spi_ss0_1", "spi_ss1", "spi_sclk_1", "spi_mosi_1", + "spi_miso_1", "spi_ss2" +}; + +static const char * const ethernet_groups[] = { + "eth_tx_clk", "eth_tx_en", "eth_txd1_0", "eth_txd1_1", + "eth_txd0_0", "eth_txd0_1", "eth_rx_clk", "eth_rx_dv", + "eth_rxd1", "eth_rxd0", "eth_mdio_en", "eth_mdc", "eth_ref_clk", + "eth_txd2", "eth_txd3" +}; + +static const char * const i2c_a_groups[] = { + "i2c_sda_a", "i2c_sck_a", +}; + +static const char * const i2c_b_groups[] = { + "i2c_sda_b0", "i2c_sck_b0", "i2c_sda_b1", "i2c_sck_b1" +}; + +static const char * const sd_c_groups[] = { + "sd_d0_c", "sd_d1_c", "sd_d2_c", "sd_d3_c", + "sd_cmd_c", "sd_clk_c" +}; + +static const char * const sdxc_c_groups[] = { + "sdxc_d0_c", "sdxc_d13_c", "sdxc_d47_c", "sdxc_cmd_c", + "sdxc_clk_c" +}; + +static const char * const nand_groups[] = { + "nand_io", "nand_io_ce0", "nand_io_ce1", + "nand_io_rb0", "nand_ale", "nand_cle", + "nand_wen_clk", "nand_ren_clk", "nand_dqs0", + "nand_dqs1" +}; + +static const char * const nor_groups[] = { + "nor_d", "nor_q", "nor_c", "nor_cs" +}; + +static const char * const sd_b_groups[] = { + "sd_d1_b", "sd_d0_b", "sd_clk_b", "sd_cmd_b", + "sd_d3_b", "sd_d2_b" +}; + +static const char * const sdxc_b_groups[] = { + "sdxc_d13_b", "sdxc_d0_b", "sdxc_clk_b", "sdxc_cmd_b" +}; + +static const char * const uart_ao_groups[] = { + "uart_tx_ao_a", "uart_rx_ao_a", "uart_cts_ao_a", "uart_rts_ao_a" +}; + +static const char * const remote_groups[] = { + "remote_input", "ir_blaster", "ir_remote_out" +}; + +static const char * const i2c_slave_ao_groups[] = { + "i2c_sck_ao", "i2c_sda_ao" +}; + +static const char * const uart_ao_b_groups[] = { + "uart_tx_ao_b0", "uart_rx_ao_b0", "uart_tx_ao_b1", "uart_rx_ao_b1", + "uart_cts_ao_b", "uart_rts_ao_b" +}; + +static const char * const i2c_mst_ao_groups[] = { + "i2c_mst_sck_ao", "i2c_mst_sda_ao" +}; + +static const char * const clk_24m_groups[] = { + "clk_24m_out" +}; + +static const char * const clk_32k_groups[] = { + "clk_32k_in_out" +}; + +static const char * const spdif_0_groups[] = { + "spdif_out_0" +}; + +static const char * const spdif_1_groups[] = { + "spdif_out_1" +}; + +static const char * const i2s_groups[] = { + "i2s_am_clk_out", "i2s_ao_clk_out", "i2s_lr_clk_out", + "i2s_out_01", "i2s_in_ch01", "i2s_ao_clk_in", + "i2s_lr_clk_in" +}; + +static const char * const pwm_b_groups[] = { + "pwm_b" +}; + +static const char * const pwm_c_groups[] = { + "pwm_c0", "pwm_c1" +}; + +static const char * const pwm_c_ao_groups[] = { + "pwm_c2" +}; + +static const char * const pwm_d_groups[] = { + "pwm_d" +}; + +static const char * const pwm_e_groups[] = { + "pwm_e" +}; + +static const char * const pwm_vs_groups[] = { + "pwm_vs_0", "pwm_vs_1", "pwm_vs_2", + "pwm_vs_3", "pwm_vs_4" +}; + +static const char * const tsin_a_groups[] = { + "tsin_d0_a", "tsin_d17_a", "tsin_clk_a", "tsin_sop_a", + "tsin_d_valid_a" +}; + +static const char * const tsin_b_groups[] = { + "tsin_d0_b", "tsin_clk_b", "tsin_sop_b", "tsin_d_valid_b" +}; + +static struct meson_pmx_func meson8b_cbus_functions[] = { + FUNCTION(gpio), + FUNCTION(sd_a), + FUNCTION(sdxc_a), + FUNCTION(pcm_a), + FUNCTION(uart_a), + FUNCTION(uart_b), + FUNCTION(iso7816), + FUNCTION(i2c_d), + FUNCTION(xtal), + FUNCTION(uart_c), + FUNCTION(i2c_c), + FUNCTION(hdmi), + FUNCTION(spi), + FUNCTION(ethernet), + FUNCTION(i2c_a), + FUNCTION(i2c_b), + FUNCTION(sd_c), + FUNCTION(sdxc_c), + FUNCTION(nand), + FUNCTION(nor), + FUNCTION(sd_b), + FUNCTION(sdxc_b), + FUNCTION(spdif_0), + FUNCTION(pwm_b), + FUNCTION(pwm_c), + FUNCTION(pwm_d), + FUNCTION(pwm_e), + FUNCTION(pwm_vs), + FUNCTION(tsin_a), + FUNCTION(tsin_b), + FUNCTION(clk_24m), +}; + +static const char * const gpio_aobus_groups[] = { + "GPIOAO_0", "GPIOAO_1", "GPIOAO_2", "GPIOAO_3", "GPIOAO_4", + "GPIOAO_5", "GPIOAO_6", "GPIOAO_7", "GPIOAO_8", "GPIOAO_9", + "GPIOAO_10", "GPIOAO_11", "GPIOAO_12", "GPIOAO_13", "GPIOAO_14", +}; + +static struct meson_pmx_func meson8b_aobus_functions[] = { + FUNCTION(gpio_aobus), + FUNCTION(uart_ao), + FUNCTION(uart_ao_b), + FUNCTION(i2c_slave_ao), + FUNCTION(i2c_mst_ao), + FUNCTION(i2s), + FUNCTION(remote), + FUNCTION(clk_32k), + FUNCTION(pwm_c_ao), + FUNCTION(spdif_1), + FUNCTION(hdmi_cec), +}; + +static struct meson_bank meson8b_cbus_banks[] = { + /* name first last pullen pull dir out in */ + BANK("X", PIN(GPIOX_0, 0), PIN(GPIOX_21, 0), + 4, 0, 4, 0, 0, 0, 1, 0, 2, 0), + BANK("Y", PIN(GPIOY_0, 0), PIN(GPIOY_16, 0), + 3, 0, 3, 0, 3, 0, 4, 0, 5, 0), + BANK("DV", PIN(GPIODV_0, 0), PIN(GPIODV_29, 0), + 0, 0, 0, 0, 6, 0, 7, 0, 8, 0), + BANK("H", PIN(GPIOH_0, 0), PIN(GPIOH_9, 0), + 1, 16, 1, 16, 9, 19, 10, 19, 11, 19), + BANK("CARD", PIN(CARD_0, 0), PIN(CARD_6, 0), + 2, 20, 2, 20, 0, 22, 1, 22, 2, 22), + BANK("BOOT", PIN(BOOT_0, 0), PIN(BOOT_18, 0), + 2, 0, 2, 0, 9, 0, 10, 0, 11, 0), + BANK("DIF", PIN(DIF_0_P, 0), PIN(DIF_4_N, 0), + 5, 8, 5, 8, 12, 12, 13, 12, 14, 12), +}; + +static struct meson_bank meson8b_aobus_banks[] = { + /* name first last pullen pull dir out in */ + BANK("AO", PIN(GPIOAO_0, AO_OFF), PIN(GPIO_TEST_N, AO_OFF), + 0, 0, 0, 16, 0, 0, 0, 16, 1, 0), +}; + +static struct meson_domain_data meson8b_periphs_domain_data = { + .name = "cbus-banks", + .banks = meson8b_cbus_banks, + .num_banks = ARRAY_SIZE(meson8b_cbus_banks), + .pin_base = 0, + .num_pins = 115, +}; + +static struct meson_domain_data meson8b_aobus_domain_data = { + .name = "aobus-banks", + .banks = meson8b_aobus_banks, + .num_banks = ARRAY_SIZE(meson8b_aobus_banks), + .pin_base = 115, + .num_pins = 16, +}; + +struct meson_pinctrl_data meson8b_cbus_pinctrl_data = { + .pins = meson8b_cbus_pins, + .groups = meson8b_cbus_groups, + .funcs = meson8b_cbus_functions, + .domain_data = &meson8b_periphs_domain_data, + .num_pins = ARRAY_SIZE(meson8b_cbus_pins), + .num_groups = ARRAY_SIZE(meson8b_cbus_groups), + .num_funcs = ARRAY_SIZE(meson8b_cbus_functions), +}; + +struct meson_pinctrl_data meson8b_aobus_pinctrl_data = { + .pins = meson8b_aobus_pins, + .groups = meson8b_aobus_groups, + .funcs = meson8b_aobus_functions, + .domain_data = &meson8b_aobus_domain_data, + .num_pins = ARRAY_SIZE(meson8b_aobus_pins), + .num_groups = ARRAY_SIZE(meson8b_aobus_groups), + .num_funcs = ARRAY_SIZE(meson8b_aobus_functions), +}; diff --git a/include/dt-bindings/gpio/meson8b-gpio.h b/include/dt-bindings/gpio/meson8b-gpio.h index c38cb20..72a3067 100644 --- a/include/dt-bindings/gpio/meson8b-gpio.h +++ b/include/dt-bindings/gpio/meson8b-gpio.h @@ -15,18 +15,142 @@ #ifndef _DT_BINDINGS_MESON8B_GPIO_H #define _DT_BINDINGS_MESON8B_GPIO_H -#include +/* First GPIO chip */ +#define GPIOH_0 0 +#define GPIOH_1 1 +#define GPIOH_2 2 +#define GPIOH_3 3 +#define GPIOH_4 4 +#define GPIOH_5 5 +#define GPIOH_6 6 +#define GPIOH_7 7 +#define GPIOH_8 8 +#define GPIOH_9 9 +#define BOOT_0 10 +#define BOOT_1 11 +#define BOOT_2 12 +#define BOOT_3 13 +#define BOOT_4 14 +#define BOOT_5 15 +#define BOOT_6 16 +#define BOOT_7 17 +#define BOOT_8 18 +#define BOOT_9 19 +#define BOOT_10 20 +#define BOOT_11 21 +#define BOOT_12 22 +#define BOOT_13 23 +#define BOOT_14 24 +#define BOOT_15 25 +#define BOOT_16 26 +#define BOOT_17 27 +#define BOOT_18 28 +#define CARD_0 29 +#define CARD_1 30 +#define CARD_2 31 +#define CARD_3 32 +#define CARD_4 33 +#define CARD_5 34 +#define CARD_6 35 +#define GPIODV_0 36 +#define GPIODV_1 37 +#define GPIODV_2 38 +#define GPIODV_3 39 +#define GPIODV_4 40 +#define GPIODV_5 41 +#define GPIODV_6 42 +#define GPIODV_7 43 +#define GPIODV_8 44 +#define GPIODV_9 45 +#define GPIODV_10 46 +#define GPIODV_11 47 +#define GPIODV_12 48 +#define GPIODV_13 49 +#define GPIODV_14 50 +#define GPIODV_15 51 +#define GPIODV_16 52 +#define GPIODV_17 53 +#define GPIODV_18 54 +#define GPIODV_19 55 +#define GPIODV_20 56 +#define GPIODV_21 57 +#define GPIODV_22 58 +#define GPIODV_23 59 +#define GPIODV_24 60 +#define GPIODV_25 61 +#define GPIODV_26 62 +#define GPIODV_27 63 +#define GPIODV_28 64 +#define GPIODV_29 65 +#define GPIOY_0 66 +#define GPIOY_1 67 +#define GPIOY_2 68 +#define GPIOY_3 69 +#define GPIOY_4 70 +#define GPIOY_5 71 +#define GPIOY_6 72 +#define GPIOY_7 73 +#define GPIOY_8 74 +#define GPIOY_9 75 +#define GPIOY_10 76 +#define GPIOY_11 77 +#define GPIOY_12 78 +#define GPIOY_13 79 +#define GPIOY_14 80 +#define GPIOY_15 81 +#define GPIOY_16 82 +#define GPIOX_0 83 +#define GPIOX_1 84 +#define GPIOX_2 85 +#define GPIOX_3 86 +#define GPIOX_4 87 +#define GPIOX_5 88 +#define GPIOX_6 89 +#define GPIOX_7 90 +#define GPIOX_8 91 +#define GPIOX_9 92 +#define GPIOX_10 93 +#define GPIOX_11 94 +#define GPIOX_12 95 +#define GPIOX_13 96 +#define GPIOX_14 97 +#define GPIOX_15 98 +#define GPIOX_16 99 +#define GPIOX_17 100 +#define GPIOX_18 101 +#define GPIOX_19 102 +#define GPIOX_20 103 +#define GPIOX_21 104 + +/* Second GPIO chip */ +#define GPIOAO_0 0 +#define GPIOAO_1 1 +#define GPIOAO_2 2 +#define GPIOAO_3 3 +#define GPIOAO_4 4 +#define GPIOAO_5 5 +#define GPIOAO_6 6 +#define GPIOAO_7 7 +#define GPIOAO_8 8 +#define GPIOAO_9 9 +#define GPIOAO_10 10 +#define GPIOAO_11 11 +#define GPIOAO_12 12 +#define GPIOAO_13 13 +#define GPIO_BSD_EN 14 +#define GPIO_TEST_N 15 + /* GPIO Bank DIF */ -#define DIF_0_P 120 -#define DIF_0_N 121 -#define DIF_1_P 122 -#define DIF_1_N 123 -#define DIF_2_P 124 -#define DIF_2_N 125 -#define DIF_3_P 126 -#define DIF_3_N 127 -#define DIF_4_P 128 -#define DIF_4_N 129 +#define DIF_0_P 105 +#define DIF_0_N 106 +#define DIF_1_P 107 +#define DIF_1_N 108 +#define DIF_2_P 109 +#define DIF_2_N 110 +#define DIF_3_P 111 +#define DIF_3_N 112 +#define DIF_4_P 113 +#define DIF_4_N 114 #endif /* _DT_BINDINGS_MESON8B_GPIO_H */ -- 2.7.4