From eabf8333d65b95bf0c3a2cb897570881723e38cd Mon Sep 17 00:00:00 2001
From: Christian Konig <christian.koenig@amd.com>
Date: Thu, 21 Feb 2013 15:16:49 +0000
Subject: [PATCH] R600/SI: add constant for inline zero operand
MIME-Version: 1.0
Content-Type: text/plain; charset=utf8
Content-Transfer-Encoding: 8bit

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
llvm-svn: 175747
---
 llvm/lib/Target/R600/SIInstrInfo.td | 7 +++----
 1 file changed, 3 insertions(+), 4 deletions(-)

diff --git a/llvm/lib/Target/R600/SIInstrInfo.td b/llvm/lib/Target/R600/SIInstrInfo.td
index cf0d5b9..8b90d45 100644
--- a/llvm/lib/Target/R600/SIInstrInfo.td
+++ b/llvm/lib/Target/R600/SIInstrInfo.td
@@ -49,9 +49,8 @@ class InlineImm <ValueType vt> : ImmLeaf <vt, [{
 // SI assembler operands
 //===----------------------------------------------------------------------===//
 
-class SIOperand <ValueType vt, dag opInfo>: Operand <vt> {
-  let EncoderMethod = "encodeOperand";
-  let MIOperandInfo = opInfo;
+def SIOperand {
+  int ZERO = 0x80;
 }
 
 class GPR4Align <RegisterClass rc> : Operand <vAny> {
@@ -201,7 +200,7 @@ multiclass VOPC_Helper <bits<8> op, RegisterClass vrc, RegisterClass arc,
          InstFlag:$omod, InstFlag:$neg),
     opName, pattern
   > {
-    let SRC2 = 0x80;
+    let SRC2 = SIOperand.ZERO;
   }
 }
 
-- 
2.7.4