From ea92bd8d447dcb92e06d20426d71a9e86cd5249e Mon Sep 17 00:00:00 2001
From: =?utf8?q?Marcin=20=C5=9Alusarz?= <marcin.slusarz@intel.com>
Date: Mon, 20 Mar 2023 11:32:07 +0100
Subject: [PATCH] intel/compiler: mask GS URB handles at thread payload
 construction

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25195>
---
 src/intel/compiler/brw_fs_thread_payload.cpp | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/src/intel/compiler/brw_fs_thread_payload.cpp b/src/intel/compiler/brw_fs_thread_payload.cpp
index 3bd7d11..5197639 100644
--- a/src/intel/compiler/brw_fs_thread_payload.cpp
+++ b/src/intel/compiler/brw_fs_thread_payload.cpp
@@ -108,7 +108,9 @@ gs_thread_payload::gs_thread_payload(const fs_visitor &v)
    unsigned r = reg_unit(v.devinfo);
 
    /* R1: output URB handles. */
-   urb_handles = brw_ud8_grf(r, 0);
+   urb_handles = v.bld.vgrf(BRW_REGISTER_TYPE_UD);
+   v.bld.AND(urb_handles, brw_ud8_grf(r, 0),
+         v.devinfo->ver >= 20 ? brw_imm_ud(0xFFFFFF) : brw_imm_ud(0xFFFF));
    r += reg_unit(v.devinfo);
 
    if (gs_prog_data->include_primitive_id) {
-- 
2.7.4