From ea48bf8649e12db8dc85078b001b9cc8d52a72b5 Mon Sep 17 00:00:00 2001 From: Nemanja Ivanovic Date: Fri, 19 Mar 2021 22:52:40 -0500 Subject: [PATCH] [PowerPC][NFC] Do not produce i64 constants in 32-bit mode There are some instances where we produce constants of type MVT::i64 unconditionally in the target DAG combines. This is not actually valid in 32-bit mode. --- llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 4 ++-- llvm/lib/Target/PowerPC/PPCInstrPrefix.td | 16 ++++++++-------- 2 files changed, 10 insertions(+), 10 deletions(-) diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp index 4fa1689..5e004c4 100644 --- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp @@ -10111,7 +10111,7 @@ SDValue PPCTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, PPCISD::EXTRACT_VSX_REG, dl, MVT::v16i8, WideVec, DAG.getConstant(Subtarget.isLittleEndian() ? NumVecs - 1 - VecNo : VecNo, - dl, MVT::i64)); + dl, getPointerTy(DAG.getDataLayout()))); RetOps.push_back(Extract); } return DAG.getMergeValues(RetOps, dl); @@ -10395,7 +10395,7 @@ SDValue PPCTargetLowering::LowerVectorStore(SDValue Op, for (unsigned Idx = 0; Idx < NumVecs; ++Idx) { unsigned VecNum = Subtarget.isLittleEndian() ? NumVecs - 1 - Idx : Idx; SDValue Elt = DAG.getNode(PPCISD::EXTRACT_VSX_REG, dl, MVT::v16i8, Value, - DAG.getConstant(VecNum, dl, MVT::i64)); + DAG.getConstant(VecNum, dl, getPointerTy(DAG.getDataLayout()))); SDValue Store = DAG.getStore(StoreChain, dl, Elt, BasePtr, SN->getPointerInfo().getWithOffset(Idx * 16), diff --git a/llvm/lib/Target/PowerPC/PPCInstrPrefix.td b/llvm/lib/Target/PowerPC/PPCInstrPrefix.td index 5981bca..7f12a40 100644 --- a/llvm/lib/Target/PowerPC/PPCInstrPrefix.td +++ b/llvm/lib/Target/PowerPC/PPCInstrPrefix.td @@ -18,10 +18,10 @@ def SDT_PPCPairBuild : SDTypeProfile<1, 2, [ SDTCisVT<0, v256i1>, SDTCisVT<1, v4i32>, SDTCisVT<2, v4i32> ]>; def SDT_PPCAccExtractVsx : SDTypeProfile<1, 2, [ - SDTCisVT<0, v4i32>, SDTCisVT<1, v512i1>, SDTCisInt<2> + SDTCisVT<0, v4i32>, SDTCisVT<1, v512i1>, SDTCisPtrTy<2> ]>; def SDT_PPCPairExtractVsx : SDTypeProfile<1, 2, [ - SDTCisVT<0, v4i32>, SDTCisVT<1, v256i1>, SDTCisInt<2> + SDTCisVT<0, v4i32>, SDTCisVT<1, v256i1>, SDTCisPtrTy<2> ]>; def SDT_PPCxxmfacc : SDTypeProfile<1, 1, [ SDTCisVT<0, v512i1>, SDTCisVT<1, v512i1> @@ -1608,13 +1608,13 @@ let Predicates = [MMA] in { v16i8:$vs3, v16i8:$vs2)), (XXMTACC Concats.VecsToVecQuad)>; def : Pat<(v512i1 (PPCxxmfacc v512i1:$AS)), (XXMFACC acc:$AS)>; - def : Pat<(v4i32 (PPCAccExtractVsx acc:$v, (i64 0))), + def : Pat<(v4i32 (PPCAccExtractVsx acc:$v, 0)), Extracts.Vec0>; - def : Pat<(v4i32 (PPCAccExtractVsx acc:$v, (i64 1))), + def : Pat<(v4i32 (PPCAccExtractVsx acc:$v, 1)), Extracts.Vec1>; - def : Pat<(v4i32 (PPCAccExtractVsx acc:$v, (i64 2))), + def : Pat<(v4i32 (PPCAccExtractVsx acc:$v, 2)), Extracts.Vec2>; - def : Pat<(v4i32 (PPCAccExtractVsx acc:$v, (i64 3))), + def : Pat<(v4i32 (PPCAccExtractVsx acc:$v, 3)), Extracts.Vec3>; } @@ -1623,9 +1623,9 @@ let Predicates = [PairedVectorMemops] in { Concats.VecsToVecPair0>; def : Pat<(v256i1 (int_ppc_vsx_assemble_pair v16i8:$vs1, v16i8:$vs0)), Concats.VecsToVecPair0>; - def : Pat<(v4i32 (PPCPairExtractVsx vsrpevenrc:$v, (i64 0))), + def : Pat<(v4i32 (PPCPairExtractVsx vsrpevenrc:$v, 0)), (v4i32 (EXTRACT_SUBREG $v, sub_vsx0))>; - def : Pat<(v4i32 (PPCPairExtractVsx vsrpevenrc:$v, (i64 1))), + def : Pat<(v4i32 (PPCPairExtractVsx vsrpevenrc:$v, 1)), (v4i32 (EXTRACT_SUBREG $v, sub_vsx1))>; } -- 2.7.4