From ea417f53354b5ea65c7c4863a4f336dda23bf019 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Tue, 25 Oct 2016 07:23:48 +0100 Subject: [PATCH] radv: move pipeline barrier image transitions after src flushing This seems like it would conform better with the spec. noticed while digging into fast clears. Reviewed-by: Bas Nieuwenhuizen Signed-off-by: Dave Airlie --- src/amd/vulkan/radv_cmd_buffer.c | 20 ++++++++++++-------- 1 file changed, 12 insertions(+), 8 deletions(-) diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index 9517e7a..824f9d8 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -2246,19 +2246,11 @@ void radv_CmdPipelineBarrier( } for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) { - RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image); src_flags |= pImageMemoryBarriers[i].srcAccessMask; dst_flags |= pImageMemoryBarriers[i].dstAccessMask; - - radv_handle_image_transition(cmd_buffer, image, - pImageMemoryBarriers[i].oldLayout, - pImageMemoryBarriers[i].newLayout, - pImageMemoryBarriers[i].subresourceRange, - 0); } enum radv_cmd_flush_bits flush_bits = 0; - for_each_bit(b, src_flags) { switch ((VkAccessFlagBits)(1 << b)) { case VK_ACCESS_SHADER_WRITE_BIT: @@ -2277,6 +2269,18 @@ void radv_CmdPipelineBarrier( break; } } + cmd_buffer->state.flush_bits |= flush_bits; + + for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) { + RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image); + radv_handle_image_transition(cmd_buffer, image, + pImageMemoryBarriers[i].oldLayout, + pImageMemoryBarriers[i].newLayout, + pImageMemoryBarriers[i].subresourceRange, + 0); + } + + flush_bits = 0; for_each_bit(b, dst_flags) { switch ((VkAccessFlagBits)(1 << b)) { -- 2.7.4