From e9f17e9fb06a4389588f47be8c766b07e8d8b89f Mon Sep 17 00:00:00 2001 From: Lionel Landwerlin Date: Fri, 25 Nov 2016 14:23:01 +0000 Subject: [PATCH] i965: enable INTEL_conservative_rasterization on Gen9+ Signed-off-by: Lionel Landwerlin Reviewed-by: Chris Forbes --- src/mesa/drivers/dri/i965/brw_compiler.h | 1 + src/mesa/drivers/dri/i965/brw_defines.h | 1 + src/mesa/drivers/dri/i965/brw_fs.cpp | 1 + src/mesa/drivers/dri/i965/gen8_ps_state.c | 13 ++++++++----- src/mesa/drivers/dri/i965/gen8_sf_state.c | 6 ++++++ src/mesa/drivers/dri/i965/intel_extensions.c | 1 + 6 files changed, 18 insertions(+), 5 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_compiler.h b/src/mesa/drivers/dri/i965/brw_compiler.h index 410641f..a97f874 100644 --- a/src/mesa/drivers/dri/i965/brw_compiler.h +++ b/src/mesa/drivers/dri/i965/brw_compiler.h @@ -398,6 +398,7 @@ struct brw_wm_prog_data { bool early_fragment_tests; bool post_depth_coverage; + bool inner_coverage; bool dispatch_8; bool dispatch_16; bool dual_src_blend; diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h index f22a52f..cae8e9a 100644 --- a/src/mesa/drivers/dri/i965/brw_defines.h +++ b/src/mesa/drivers/dri/i965/brw_defines.h @@ -2373,6 +2373,7 @@ enum brw_message_target { #define _3DSTATE_RASTER 0x7850 /* GEN8+ */ /* DW1 */ # define GEN9_RASTER_VIEWPORT_Z_FAR_CLIP_TEST_ENABLE (1 << 26) +# define GEN9_RASTER_CONSERVATIVE_RASTERIZATION_ENABLE (1 << 24) # define GEN8_RASTER_FRONT_WINDING_CCW (1 << 21) # define GEN8_RASTER_CULL_BOTH (0 << 16) # define GEN8_RASTER_CULL_NONE (1 << 16) diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp index ce0c07e..b5d1381 100644 --- a/src/mesa/drivers/dri/i965/brw_fs.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs.cpp @@ -6455,6 +6455,7 @@ brw_compile_fs(const struct brw_compiler *compiler, void *log_data, prog_data->early_fragment_tests = shader->info->fs.early_fragment_tests; prog_data->post_depth_coverage = shader->info->fs.post_depth_coverage; + prog_data->inner_coverage = shader->info->fs.inner_coverage; prog_data->barycentric_interp_modes = brw_compute_barycentric_interp_modes(compiler->devinfo, shader); diff --git a/src/mesa/drivers/dri/i965/gen8_ps_state.c b/src/mesa/drivers/dri/i965/gen8_ps_state.c index 33ef023..e43192d 100644 --- a/src/mesa/drivers/dri/i965/gen8_ps_state.c +++ b/src/mesa/drivers/dri/i965/gen8_ps_state.c @@ -32,6 +32,7 @@ void gen8_upload_ps_extra(struct brw_context *brw, const struct brw_wm_prog_data *prog_data) { + struct gl_context *ctx = &brw->ctx; uint32_t dw1 = 0; dw1 |= GEN8_PSX_PIXEL_SHADER_VALID; @@ -52,14 +53,15 @@ gen8_upload_ps_extra(struct brw_context *brw, if (prog_data->persample_dispatch) dw1 |= GEN8_PSX_SHADER_IS_PER_SAMPLE; + /* _NEW_POLYGON */ if (prog_data->uses_sample_mask) { if (brw->gen >= 9) { - if (prog_data->post_depth_coverage) { + if (prog_data->post_depth_coverage) dw1 |= BRW_PCICMS_DEPTH << GEN9_PSX_SHADER_NORMAL_COVERAGE_MASK_SHIFT; - } - else { + else if (prog_data->inner_coverage && ctx->IntelConservativeRasterization) dw1 |= BRW_PSICMS_INNER << GEN9_PSX_SHADER_NORMAL_COVERAGE_MASK_SHIFT; - } + else + dw1 |= BRW_PSICMS_NORMAL << GEN9_PSX_SHADER_NORMAL_COVERAGE_MASK_SHIFT; } else { dw1 |= GEN8_PSX_SHADER_USES_INPUT_COVERAGE_MASK; @@ -289,7 +291,8 @@ upload_ps_state(struct brw_context *brw) const struct brw_tracked_state gen8_ps_state = { .dirty = { - .mesa = _NEW_MULTISAMPLE, + .mesa = _NEW_MULTISAMPLE | + _NEW_POLYGON, .brw = BRW_NEW_BATCH | BRW_NEW_BLORP | BRW_NEW_FS_PROG_DATA, diff --git a/src/mesa/drivers/dri/i965/gen8_sf_state.c b/src/mesa/drivers/dri/i965/gen8_sf_state.c index 5d77b39..afe7b52 100644 --- a/src/mesa/drivers/dri/i965/gen8_sf_state.c +++ b/src/mesa/drivers/dri/i965/gen8_sf_state.c @@ -319,6 +319,12 @@ upload_raster(struct brw_context *brw) } } + /* _NEW_POLYGON */ + if (ctx->IntelConservativeRasterization) { + if (brw->gen >= 9) + dw1 |= GEN9_RASTER_CONSERVATIVE_RASTERIZATION_ENABLE; + } + BEGIN_BATCH(5); OUT_BATCH(_3DSTATE_RASTER << 16 | (5 - 2)); OUT_BATCH(dw1); diff --git a/src/mesa/drivers/dri/i965/intel_extensions.c b/src/mesa/drivers/dri/i965/intel_extensions.c index 19f4684..c1f42aa 100644 --- a/src/mesa/drivers/dri/i965/intel_extensions.c +++ b/src/mesa/drivers/dri/i965/intel_extensions.c @@ -414,6 +414,7 @@ intelInitExtensions(struct gl_context *ctx) ctx->Extensions.KHR_blend_equation_advanced_coherent = true; ctx->Extensions.KHR_texture_compression_astc_ldr = true; ctx->Extensions.KHR_texture_compression_astc_sliced_3d = true; + ctx->Extensions.INTEL_conservative_rasterization = true; ctx->Extensions.MESA_shader_framebuffer_fetch = true; ctx->Extensions.ARB_post_depth_coverage = true; } -- 2.7.4