From e90d0387d90c78d882fe18434010e071a1702210 Mon Sep 17 00:00:00 2001 From: Sanjay Patel Date: Wed, 18 Mar 2015 16:07:10 +0000 Subject: [PATCH] fixed to test features, not CPU model The 'vmovntdq' was only passing due to a fluke in SandyBridge codegen that splits 32-byte stores in half, but that meant that the test was not correctly checking for the 32-byte store that we thought we were generating. The lax checking in this file will be addressed in another commit. There are bigger problems here. llvm-svn: 232644 --- llvm/test/CodeGen/X86/avx-intrinsics-x86.ll | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/llvm/test/CodeGen/X86/avx-intrinsics-x86.ll b/llvm/test/CodeGen/X86/avx-intrinsics-x86.ll index ecf8a19..cbd80678 100644 --- a/llvm/test/CodeGen/X86/avx-intrinsics-x86.ll +++ b/llvm/test/CodeGen/X86/avx-intrinsics-x86.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple=x86_64-apple-darwin -march=x86 -mcpu=corei7-avx | FileCheck %s +; RUN: llc < %s -mtriple=x86_64-apple-darwin -march=x86 -mattr=avx,aes,pclmul | FileCheck %s define <2 x i64> @test_x86_aesni_aesdec(<2 x i64> %a0, <2 x i64> %a1) { ; CHECK: vaesdec @@ -2460,9 +2460,10 @@ define i32 @crc32_32_32(i32 %a, i32 %b) nounwind { declare i32 @llvm.x86.sse42.crc32.32.32(i32, i32) nounwind ; CHECK: movntdq -define void @movnt_dq(i8* %p, <4 x i64> %a1) nounwind { - %a2 = add <4 x i64> %a1, - tail call void @llvm.x86.avx.movnt.dq.256(i8* %p, <4 x i64> %a2) nounwind +define void @movnt_dq(i8* %p, <2 x i64> %a1) nounwind { + %a2 = add <2 x i64> %a1, + %a3 = shufflevector <2 x i64> %a2, <2 x i64> undef, <4 x i32> + tail call void @llvm.x86.avx.movnt.dq.256(i8* %p, <4 x i64> %a3) nounwind ret void } declare void @llvm.x86.avx.movnt.dq.256(i8*, <4 x i64>) nounwind -- 2.7.4