From e8e0f32958fafa43fb68573b09b710e6260fa9ad Mon Sep 17 00:00:00 2001 From: Luke Lau Date: Fri, 30 Jun 2023 17:44:47 +0100 Subject: [PATCH] [RISCV] Fix vfwcvt/vfncvt pseudos w/ rounding mode lowering Some signed opcodes were being lowered to their unsigned counterparts and vice-versa. Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D154234 --- llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 42 ++++++++++++------------ llvm/test/CodeGen/RISCV/rvv/double-round-conv.ll | 8 ++--- llvm/test/CodeGen/RISCV/rvv/float-round-conv.ll | 16 ++++----- llvm/test/CodeGen/RISCV/rvv/half-round-conv.ll | 12 +++---- 4 files changed, 39 insertions(+), 39 deletions(-) diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp index 78e00fc..e6c83d4 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -14096,15 +14096,15 @@ RISCVTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI, // ========================================================================= case RISCV::PseudoVFWCVT_RM_XU_F_V_M1_MASK: - return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFWCVT_X_F_V_M1_MASK); + return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFWCVT_XU_F_V_M1_MASK); case RISCV::PseudoVFWCVT_RM_XU_F_V_M2_MASK: - return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFWCVT_X_F_V_M2_MASK); + return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFWCVT_XU_F_V_M2_MASK); case RISCV::PseudoVFWCVT_RM_XU_F_V_M4_MASK: - return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFWCVT_X_F_V_M4_MASK); + return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFWCVT_XU_F_V_M4_MASK); case RISCV::PseudoVFWCVT_RM_XU_F_V_MF2_MASK: - return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFWCVT_X_F_V_MF2_MASK); + return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFWCVT_XU_F_V_MF2_MASK); case RISCV::PseudoVFWCVT_RM_XU_F_V_MF4_MASK: - return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFWCVT_X_F_V_MF4_MASK); + return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFWCVT_XU_F_V_MF4_MASK); case RISCV::PseudoVFWCVT_RM_X_F_V_M1_MASK: return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFWCVT_X_F_V_M1_MASK); @@ -14131,32 +14131,32 @@ RISCVTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI, return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFWCVT_F_XU_V_MF8_MASK); case RISCV::PseudoVFWCVT_RM_F_X_V_M1_MASK: - return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFWCVT_F_XU_V_M1_MASK); + return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFWCVT_F_X_V_M1_MASK); case RISCV::PseudoVFWCVT_RM_F_X_V_M2_MASK: - return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFWCVT_F_XU_V_M2_MASK); + return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFWCVT_F_X_V_M2_MASK); case RISCV::PseudoVFWCVT_RM_F_X_V_M4_MASK: - return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFWCVT_F_XU_V_M4_MASK); + return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFWCVT_F_X_V_M4_MASK); case RISCV::PseudoVFWCVT_RM_F_X_V_MF2_MASK: - return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFWCVT_F_XU_V_MF2_MASK); + return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFWCVT_F_X_V_MF2_MASK); case RISCV::PseudoVFWCVT_RM_F_X_V_MF4_MASK: - return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFWCVT_F_XU_V_MF4_MASK); + return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFWCVT_F_X_V_MF4_MASK); case RISCV::PseudoVFWCVT_RM_F_X_V_MF8_MASK: - return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFWCVT_F_XU_V_MF8_MASK); + return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFWCVT_F_X_V_MF8_MASK); // ========================================================================= // VFNCVT // ========================================================================= case RISCV::PseudoVFNCVT_RM_XU_F_W_M1_MASK: - return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFNCVT_X_F_W_M1_MASK); + return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFNCVT_XU_F_W_M1_MASK); case RISCV::PseudoVFNCVT_RM_XU_F_W_M2_MASK: - return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFNCVT_X_F_W_M2_MASK); + return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFNCVT_XU_F_W_M2_MASK); case RISCV::PseudoVFNCVT_RM_XU_F_W_M4_MASK: - return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFNCVT_X_F_W_M4_MASK); + return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFNCVT_XU_F_W_M4_MASK); case RISCV::PseudoVFNCVT_RM_XU_F_W_MF2_MASK: - return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFNCVT_X_F_W_MF2_MASK); + return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFNCVT_XU_F_W_MF2_MASK); case RISCV::PseudoVFNCVT_RM_XU_F_W_MF4_MASK: - return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFNCVT_X_F_W_MF4_MASK); + return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFNCVT_XU_F_W_MF4_MASK); case RISCV::PseudoVFNCVT_RM_XU_F_W_MF8_MASK: return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFNCVT_XU_F_W_MF8_MASK); @@ -14185,15 +14185,15 @@ RISCVTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI, return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFNCVT_F_XU_W_MF4_MASK); case RISCV::PseudoVFNCVT_RM_F_X_W_M1_MASK: - return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFNCVT_F_XU_W_M1_MASK); + return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFNCVT_F_X_W_M1_MASK); case RISCV::PseudoVFNCVT_RM_F_X_W_M2_MASK: - return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFNCVT_F_XU_W_M2_MASK); + return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFNCVT_F_X_W_M2_MASK); case RISCV::PseudoVFNCVT_RM_F_X_W_M4_MASK: - return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFNCVT_F_XU_W_M4_MASK); + return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFNCVT_F_X_W_M4_MASK); case RISCV::PseudoVFNCVT_RM_F_X_W_MF2_MASK: - return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFNCVT_F_XU_W_MF2_MASK); + return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFNCVT_F_X_W_MF2_MASK); case RISCV::PseudoVFNCVT_RM_F_X_W_MF4_MASK: - return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFNCVT_F_XU_W_MF4_MASK); + return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFNCVT_F_X_W_MF4_MASK); case RISCV::PseudoVFROUND_NOEXCEPT_V_M1_MASK: return emitVFROUND_NOEXCEPT_MASK(MI, BB, RISCV::PseudoVFCVT_X_F_V_M1_MASK, diff --git a/llvm/test/CodeGen/RISCV/rvv/double-round-conv.ll b/llvm/test/CodeGen/RISCV/rvv/double-round-conv.ll index 64e03e3..fd04a0f 100644 --- a/llvm/test/CodeGen/RISCV/rvv/double-round-conv.ll +++ b/llvm/test/CodeGen/RISCV/rvv/double-round-conv.ll @@ -705,7 +705,7 @@ define @ceil_nxv1f64_to_ui32( %x) { ; RV32-NEXT: vsetvli a0, zero, e32, mf2, ta, ma ; RV32-NEXT: vmset.m v0 ; RV32-NEXT: fsrmi a0, 3 -; RV32-NEXT: vfncvt.x.f.w v9, v8, v0.t +; RV32-NEXT: vfncvt.xu.f.w v9, v8, v0.t ; RV32-NEXT: fsrm a0 ; RV32-NEXT: vmv1r.v v8, v9 ; RV32-NEXT: ret @@ -715,7 +715,7 @@ define @ceil_nxv1f64_to_ui32( %x) { ; RV64-NEXT: vsetvli a0, zero, e32, mf2, ta, ma ; RV64-NEXT: vmset.m v0 ; RV64-NEXT: fsrmi a0, 3 -; RV64-NEXT: vfncvt.x.f.w v9, v8, v0.t +; RV64-NEXT: vfncvt.xu.f.w v9, v8, v0.t ; RV64-NEXT: fsrm a0 ; RV64-NEXT: vmv1r.v v8, v9 ; RV64-NEXT: ret @@ -987,7 +987,7 @@ define @ceil_nxv4f64_to_ui32( %x) { ; RV32-NEXT: vsetvli a0, zero, e32, m2, ta, ma ; RV32-NEXT: vmset.m v0 ; RV32-NEXT: fsrmi a0, 3 -; RV32-NEXT: vfncvt.x.f.w v12, v8, v0.t +; RV32-NEXT: vfncvt.xu.f.w v12, v8, v0.t ; RV32-NEXT: fsrm a0 ; RV32-NEXT: vmv.v.v v8, v12 ; RV32-NEXT: ret @@ -997,7 +997,7 @@ define @ceil_nxv4f64_to_ui32( %x) { ; RV64-NEXT: vsetvli a0, zero, e32, m2, ta, ma ; RV64-NEXT: vmset.m v0 ; RV64-NEXT: fsrmi a0, 3 -; RV64-NEXT: vfncvt.x.f.w v12, v8, v0.t +; RV64-NEXT: vfncvt.xu.f.w v12, v8, v0.t ; RV64-NEXT: fsrm a0 ; RV64-NEXT: vmv.v.v v8, v12 ; RV64-NEXT: ret diff --git a/llvm/test/CodeGen/RISCV/rvv/float-round-conv.ll b/llvm/test/CodeGen/RISCV/rvv/float-round-conv.ll index af1a20c..dad9a4f 100644 --- a/llvm/test/CodeGen/RISCV/rvv/float-round-conv.ll +++ b/llvm/test/CodeGen/RISCV/rvv/float-round-conv.ll @@ -515,7 +515,7 @@ define @ceil_nxv1f32_to_ui16( %x) { ; RV32-NEXT: vsetvli a0, zero, e16, mf4, ta, ma ; RV32-NEXT: vmset.m v0 ; RV32-NEXT: fsrmi a0, 3 -; RV32-NEXT: vfncvt.x.f.w v9, v8, v0.t +; RV32-NEXT: vfncvt.xu.f.w v9, v8, v0.t ; RV32-NEXT: fsrm a0 ; RV32-NEXT: vmv1r.v v8, v9 ; RV32-NEXT: ret @@ -525,7 +525,7 @@ define @ceil_nxv1f32_to_ui16( %x) { ; RV64-NEXT: vsetvli a0, zero, e16, mf4, ta, ma ; RV64-NEXT: vmset.m v0 ; RV64-NEXT: fsrmi a0, 3 -; RV64-NEXT: vfncvt.x.f.w v9, v8, v0.t +; RV64-NEXT: vfncvt.xu.f.w v9, v8, v0.t ; RV64-NEXT: fsrm a0 ; RV64-NEXT: vmv1r.v v8, v9 ; RV64-NEXT: ret @@ -611,7 +611,7 @@ define @ceil_nxv1f32_to_ui64( %x) { ; RV32-NEXT: vsetvli a0, zero, e32, mf2, ta, ma ; RV32-NEXT: vmset.m v0 ; RV32-NEXT: fsrmi a0, 3 -; RV32-NEXT: vfwcvt.x.f.v v9, v8, v0.t +; RV32-NEXT: vfwcvt.xu.f.v v9, v8, v0.t ; RV32-NEXT: fsrm a0 ; RV32-NEXT: vmv1r.v v8, v9 ; RV32-NEXT: ret @@ -621,7 +621,7 @@ define @ceil_nxv1f32_to_ui64( %x) { ; RV64-NEXT: vsetvli a0, zero, e32, mf2, ta, ma ; RV64-NEXT: vmset.m v0 ; RV64-NEXT: fsrmi a0, 3 -; RV64-NEXT: vfwcvt.x.f.v v9, v8, v0.t +; RV64-NEXT: vfwcvt.xu.f.v v9, v8, v0.t ; RV64-NEXT: fsrm a0 ; RV64-NEXT: vmv1r.v v8, v9 ; RV64-NEXT: ret @@ -753,7 +753,7 @@ define @ceil_nxv4f32_to_ui16( %x) { ; RV32-NEXT: vsetvli a0, zero, e16, m1, ta, ma ; RV32-NEXT: vmset.m v0 ; RV32-NEXT: fsrmi a0, 3 -; RV32-NEXT: vfncvt.x.f.w v10, v8, v0.t +; RV32-NEXT: vfncvt.xu.f.w v10, v8, v0.t ; RV32-NEXT: fsrm a0 ; RV32-NEXT: vmv.v.v v8, v10 ; RV32-NEXT: ret @@ -763,7 +763,7 @@ define @ceil_nxv4f32_to_ui16( %x) { ; RV64-NEXT: vsetvli a0, zero, e16, m1, ta, ma ; RV64-NEXT: vmset.m v0 ; RV64-NEXT: fsrmi a0, 3 -; RV64-NEXT: vfncvt.x.f.w v10, v8, v0.t +; RV64-NEXT: vfncvt.xu.f.w v10, v8, v0.t ; RV64-NEXT: fsrm a0 ; RV64-NEXT: vmv.v.v v8, v10 ; RV64-NEXT: ret @@ -849,7 +849,7 @@ define @ceil_nxv4f32_to_ui64( %x) { ; RV32-NEXT: vsetvli a0, zero, e32, m2, ta, ma ; RV32-NEXT: vmset.m v0 ; RV32-NEXT: fsrmi a0, 3 -; RV32-NEXT: vfwcvt.x.f.v v12, v8, v0.t +; RV32-NEXT: vfwcvt.xu.f.v v12, v8, v0.t ; RV32-NEXT: fsrm a0 ; RV32-NEXT: vmv4r.v v8, v12 ; RV32-NEXT: ret @@ -859,7 +859,7 @@ define @ceil_nxv4f32_to_ui64( %x) { ; RV64-NEXT: vsetvli a0, zero, e32, m2, ta, ma ; RV64-NEXT: vmset.m v0 ; RV64-NEXT: fsrmi a0, 3 -; RV64-NEXT: vfwcvt.x.f.v v12, v8, v0.t +; RV64-NEXT: vfwcvt.xu.f.v v12, v8, v0.t ; RV64-NEXT: fsrm a0 ; RV64-NEXT: vmv4r.v v8, v12 ; RV64-NEXT: ret diff --git a/llvm/test/CodeGen/RISCV/rvv/half-round-conv.ll b/llvm/test/CodeGen/RISCV/rvv/half-round-conv.ll index a37d3eb..4ba88a9 100644 --- a/llvm/test/CodeGen/RISCV/rvv/half-round-conv.ll +++ b/llvm/test/CodeGen/RISCV/rvv/half-round-conv.ll @@ -517,7 +517,7 @@ define @ceil_nxv1f16_to_ui32( %x) { ; RV32-NEXT: vsetvli a0, zero, e16, mf4, ta, ma ; RV32-NEXT: vmset.m v0 ; RV32-NEXT: fsrmi a0, 3 -; RV32-NEXT: vfwcvt.x.f.v v9, v8, v0.t +; RV32-NEXT: vfwcvt.xu.f.v v9, v8, v0.t ; RV32-NEXT: fsrm a0 ; RV32-NEXT: vmv1r.v v8, v9 ; RV32-NEXT: ret @@ -527,7 +527,7 @@ define @ceil_nxv1f16_to_ui32( %x) { ; RV64-NEXT: vsetvli a0, zero, e16, mf4, ta, ma ; RV64-NEXT: vmset.m v0 ; RV64-NEXT: fsrmi a0, 3 -; RV64-NEXT: vfwcvt.x.f.v v9, v8, v0.t +; RV64-NEXT: vfwcvt.xu.f.v v9, v8, v0.t ; RV64-NEXT: fsrm a0 ; RV64-NEXT: vmv1r.v v8, v9 ; RV64-NEXT: ret @@ -655,7 +655,7 @@ define @ceil_nxv4f16_to_ui8( %x) { ; RV32-NEXT: vsetvli a0, zero, e8, mf2, ta, ma ; RV32-NEXT: vmset.m v0 ; RV32-NEXT: fsrmi a0, 3 -; RV32-NEXT: vfncvt.x.f.w v9, v8, v0.t +; RV32-NEXT: vfncvt.xu.f.w v9, v8, v0.t ; RV32-NEXT: fsrm a0 ; RV32-NEXT: vmv1r.v v8, v9 ; RV32-NEXT: ret @@ -665,7 +665,7 @@ define @ceil_nxv4f16_to_ui8( %x) { ; RV64-NEXT: vsetvli a0, zero, e8, mf2, ta, ma ; RV64-NEXT: vmset.m v0 ; RV64-NEXT: fsrmi a0, 3 -; RV64-NEXT: vfncvt.x.f.w v9, v8, v0.t +; RV64-NEXT: vfncvt.xu.f.w v9, v8, v0.t ; RV64-NEXT: fsrm a0 ; RV64-NEXT: vmv1r.v v8, v9 ; RV64-NEXT: ret @@ -751,7 +751,7 @@ define @ceil_nxv4f16_to_ui32( %x) { ; RV32-NEXT: vsetvli a0, zero, e16, m1, ta, ma ; RV32-NEXT: vmset.m v0 ; RV32-NEXT: fsrmi a0, 3 -; RV32-NEXT: vfwcvt.x.f.v v10, v8, v0.t +; RV32-NEXT: vfwcvt.xu.f.v v10, v8, v0.t ; RV32-NEXT: fsrm a0 ; RV32-NEXT: vmv2r.v v8, v10 ; RV32-NEXT: ret @@ -761,7 +761,7 @@ define @ceil_nxv4f16_to_ui32( %x) { ; RV64-NEXT: vsetvli a0, zero, e16, m1, ta, ma ; RV64-NEXT: vmset.m v0 ; RV64-NEXT: fsrmi a0, 3 -; RV64-NEXT: vfwcvt.x.f.v v10, v8, v0.t +; RV64-NEXT: vfwcvt.xu.f.v v10, v8, v0.t ; RV64-NEXT: fsrm a0 ; RV64-NEXT: vmv2r.v v8, v10 ; RV64-NEXT: ret -- 2.7.4