From e7e5bbc55db2a17ac1c48498a717736ca520f710 Mon Sep 17 00:00:00 2001 From: ibolton Date: Wed, 16 Jan 2013 16:21:05 +0000 Subject: [PATCH] Make zero_extends explicit for some more SImode patterns (AArch64) git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@195243 138bc75d-0d04-0410-961f-82ee72b054a4 --- gcc/ChangeLog | 10 +++++ gcc/config/aarch64/aarch64.md | 94 +++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 104 insertions(+) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 0587ff9..2205dc4 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,13 @@ +2013-01-16 Ian Bolton + + * gcc/config/aarch64/aarch64.md + (*cstoresi_neg_uxtw): New pattern. + (*cmovsi_insn_uxtw): New pattern. + (*si3_uxtw): New pattern. + (*_si3_uxtw): New pattern. + (*si3_insn_uxtw): New pattern. + (*bswapsi2_uxtw): New pattern. + 2013-01-16 Richard Biener * tree-inline.c (tree_function_versioning): Remove set but diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index d3baa08..73d86a7 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -2198,6 +2198,18 @@ (set_attr "mode" "")] ) +;; zero_extend version of the above +(define_insn "*cstoresi_insn_uxtw" + [(set (match_operand:DI 0 "register_operand" "=r") + (zero_extend:DI + (match_operator:SI 1 "aarch64_comparison_operator" + [(match_operand 2 "cc_register" "") (const_int 0)])))] + "" + "cset\\t%w0, %m1" + [(set_attr "v8type" "csel") + (set_attr "mode" "SI")] +) + (define_insn "*cstore_neg" [(set (match_operand:ALLI 0 "register_operand" "=r") (neg:ALLI (match_operator:ALLI 1 "aarch64_comparison_operator" @@ -2208,6 +2220,18 @@ (set_attr "mode" "")] ) +;; zero_extend version of the above +(define_insn "*cstoresi_neg_uxtw" + [(set (match_operand:DI 0 "register_operand" "=r") + (zero_extend:DI + (neg:SI (match_operator:SI 1 "aarch64_comparison_operator" + [(match_operand 2 "cc_register" "") (const_int 0)]))))] + "" + "csetm\\t%w0, %m1" + [(set_attr "v8type" "csel") + (set_attr "mode" "SI")] +) + (define_expand "cmov6" [(set (match_operand:GPI 0 "register_operand" "") (if_then_else:GPI @@ -2262,6 +2286,30 @@ (set_attr "mode" "")] ) +;; zero_extend version of above +(define_insn "*cmovsi_insn_uxtw" + [(set (match_operand:DI 0 "register_operand" "=r,r,r,r,r,r,r") + (zero_extend:DI + (if_then_else:SI + (match_operator 1 "aarch64_comparison_operator" + [(match_operand 2 "cc_register" "") (const_int 0)]) + (match_operand:SI 3 "aarch64_reg_zero_or_m1_or_1" "rZ,rZ,UsM,rZ,Ui1,UsM,Ui1") + (match_operand:SI 4 "aarch64_reg_zero_or_m1_or_1" "rZ,UsM,rZ,Ui1,rZ,UsM,Ui1"))))] + "!((operands[3] == const1_rtx && operands[4] == constm1_rtx) + || (operands[3] == constm1_rtx && operands[4] == const1_rtx))" + ;; Final two alternatives should be unreachable, but included for completeness + "@ + csel\\t%w0, %w3, %w4, %m1 + csinv\\t%w0, %w3, wzr, %m1 + csinv\\t%w0, %w4, wzr, %M1 + csinc\\t%w0, %w3, wzr, %m1 + csinc\\t%w0, %w4, wzr, %M1 + mov\\t%w0, -1 + mov\\t%w0, 1" + [(set_attr "v8type" "csel") + (set_attr "mode" "SI")] +) + (define_insn "*cmov_insn" [(set (match_operand:GPF 0 "register_operand" "=w") (if_then_else:GPF @@ -2374,6 +2422,17 @@ [(set_attr "v8type" "logic,logic_imm") (set_attr "mode" "")]) +;; zero_extend version of above +(define_insn "*si3_uxtw" + [(set (match_operand:DI 0 "register_operand" "=r,rk") + (zero_extend:DI + (LOGICAL:SI (match_operand:SI 1 "register_operand" "%r,r") + (match_operand:SI 2 "aarch64_logical_operand" "r,K"))))] + "" + "\\t%w0, %w1, %w2" + [(set_attr "v8type" "logic,logic_imm") + (set_attr "mode" "SI")]) + (define_insn "*_3" [(set (match_operand:GPI 0 "register_operand" "=r") (LOGICAL:GPI (SHIFT:GPI @@ -2385,6 +2444,19 @@ [(set_attr "v8type" "logic_shift") (set_attr "mode" "")]) +;; zero_extend version of above +(define_insn "*_si3_uxtw" + [(set (match_operand:DI 0 "register_operand" "=r") + (zero_extend:DI + (LOGICAL:SI (SHIFT:SI + (match_operand:SI 1 "register_operand" "r") + (match_operand:QI 2 "aarch64_shift_imm_si" "n")) + (match_operand:SI 3 "register_operand" "r"))))] + "" + "\\t%w0, %w3, %w1, %2" + [(set_attr "v8type" "logic_shift") + (set_attr "mode" "SI")]) + (define_insn "one_cmpl2" [(set (match_operand:GPI 0 "register_operand" "=r") (not:GPI (match_operand:GPI 1 "register_operand" "r")))] @@ -2596,6 +2668,18 @@ (set_attr "mode" "")] ) +;; zero_extend version of above +(define_insn "*si3_insn_uxtw" + [(set (match_operand:DI 0 "register_operand" "=r") + (zero_extend:DI (SHIFT:SI + (match_operand:SI 1 "register_operand" "r") + (match_operand:QI 2 "aarch64_reg_or_shift_imm_si" "rUss"))))] + "" + "\\t%w0, %w1, %w2" + [(set_attr "v8type" "shift") + (set_attr "mode" "SI")] +) + (define_insn "*ashl3_insn" [(set (match_operand:SHORT 0 "register_operand" "=r") (ashift:SHORT (match_operand:SHORT 1 "register_operand" "r") @@ -2733,6 +2817,16 @@ (set_attr "mode" "HI")] ) +;; zero_extend version of above +(define_insn "*bswapsi2_uxtw" + [(set (match_operand:DI 0 "register_operand" "=r") + (zero_extend:DI (bswap:SI (match_operand:SI 1 "register_operand" "r"))))] + "" + "rev\\t%w0, %w1" + [(set_attr "v8type" "rev") + (set_attr "mode" "SI")] +) + ;; ------------------------------------------------------------------- ;; Floating-point intrinsics ;; ------------------------------------------------------------------- -- 2.7.4