From e7da31ba2030b85ff0d15a0c4aac3318cb66b64a Mon Sep 17 00:00:00 2001 From: Kito Cheng Date: Fri, 3 Dec 2021 23:50:54 +0800 Subject: [PATCH] RISC-V: Minimal support of vector extensions gcc/ChangeLog: * common/config/riscv/riscv-common.c (riscv_implied_info): Add vector extensions. (riscv_ext_version_table): Add version info for vector extensions. (riscv_ext_flag_table): Add option mask for vector extensions. * config/riscv/riscv-opts.h (MASK_VECTOR_EEW_32): New. (MASK_VECTOR_EEW_64): New. (MASK_VECTOR_EEW_FP_32): New. (MASK_VECTOR_EEW_FP_64): New. (MASK_ZVL32B): New. (MASK_ZVL64B): New. (MASK_ZVL128B): New. (MASK_ZVL256B): New. (MASK_ZVL512B): New. (MASK_ZVL1024B): New. (MASK_ZVL2048B): New. (MASK_ZVL4096B): New. (MASK_ZVL8192B): New. (MASK_ZVL16384B): New. (MASK_ZVL32768B): New. (MASK_ZVL65536B): New. (TARGET_ZVL32B): New. (TARGET_ZVL64B): New. (TARGET_ZVL128B): New. (TARGET_ZVL256B): New. (TARGET_ZVL512B): New. (TARGET_ZVL1024B): New. (TARGET_ZVL2048B): New. (TARGET_ZVL4096B): New. (TARGET_ZVL8192B): New. (TARGET_ZVL16384B): New. (TARGET_ZVL32768B): New. (TARGET_ZVL65536B): New. * config/riscv/riscv.opt (Mask(VECTOR)): New. (riscv_vector_eew_flags): New. (riscv_zvl_flags): New. gcc/testsuite/ChangeLog: * gcc.target/riscv/predef-14.c: New. * gcc.target/riscv/predef-15.c: Ditto. * gcc.target/riscv/predef-16.c: Ditto. --- gcc/common/config/riscv/riscv-common.c | 86 ++++++++++++++++++++++++++++ gcc/config/riscv/riscv-opts.h | 31 ++++++++++ gcc/config/riscv/riscv.opt | 8 +++ gcc/testsuite/gcc.target/riscv/predef-14.c | 83 +++++++++++++++++++++++++++ gcc/testsuite/gcc.target/riscv/predef-15.c | 91 ++++++++++++++++++++++++++++++ gcc/testsuite/gcc.target/riscv/predef-16.c | 91 ++++++++++++++++++++++++++++++ 6 files changed, 390 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/predef-14.c create mode 100644 gcc/testsuite/gcc.target/riscv/predef-15.c create mode 100644 gcc/testsuite/gcc.target/riscv/predef-16.c diff --git a/gcc/common/config/riscv/riscv-common.c b/gcc/common/config/riscv/riscv-common.c index ecbca6c..c1d8431 100644 --- a/gcc/common/config/riscv/riscv-common.c +++ b/gcc/common/config/riscv/riscv-common.c @@ -64,6 +64,38 @@ static const riscv_implied_info_t riscv_implied_info[] = {"zks", "zbkx"}, {"zks", "zksed"}, {"zks", "zksh"}, + + {"v", "zvl128b"}, + {"v", "zve64d"}, + + {"zve32f", "f"}, + {"zve64f", "f"}, + {"zve64d", "d"}, + + {"zve32x", "zvl32b"}, + {"zve32f", "zve32x"}, + {"zve32f", "zvl32b"}, + + {"zve64x", "zve32x"}, + {"zve64x", "zvl64b"}, + {"zve64f", "zve32f"}, + {"zve64f", "zve64x"}, + {"zve64f", "zvl64b"}, + {"zve64d", "zve64f"}, + {"zve64d", "zvl64b"}, + + {"zvl64b", "zvl32b"}, + {"zvl128b", "zvl64b"}, + {"zvl256b", "zvl128b"}, + {"zvl512b", "zvl256b"}, + {"zvl1024b", "zvl512b"}, + {"zvl2048b", "zvl1024b"}, + {"zvl4096b", "zvl2048b"}, + {"zvl8192b", "zvl4096b"}, + {"zvl16384b", "zvl8192b"}, + {"zvl32768b", "zvl16384b"}, + {"zvl65536b", "zvl32768b"}, + {NULL, NULL} }; @@ -109,6 +141,8 @@ static const struct riscv_ext_version riscv_ext_version_table[] = {"c", ISA_SPEC_CLASS_20190608, 2, 0}, {"c", ISA_SPEC_CLASS_2P2, 2, 0}, + {"v", ISA_SPEC_CLASS_NONE, 1, 0}, + {"zicsr", ISA_SPEC_CLASS_20191213, 2, 0}, {"zicsr", ISA_SPEC_CLASS_20190608, 2, 0}, @@ -131,6 +165,26 @@ static const struct riscv_ext_version riscv_ext_version_table[] = {"zksh", ISA_SPEC_CLASS_NONE, 1, 0}, {"zkt", ISA_SPEC_CLASS_NONE, 1, 0}, + {"zve32x", ISA_SPEC_CLASS_NONE, 1, 0}, + {"zve32f", ISA_SPEC_CLASS_NONE, 1, 0}, + {"zve32d", ISA_SPEC_CLASS_NONE, 1, 0}, + {"zve64x", ISA_SPEC_CLASS_NONE, 1, 0}, + {"zve64f", ISA_SPEC_CLASS_NONE, 1, 0}, + {"zve64d", ISA_SPEC_CLASS_NONE, 1, 0}, + + {"zvl32b", ISA_SPEC_CLASS_NONE, 1, 0}, + {"zvl64b", ISA_SPEC_CLASS_NONE, 1, 0}, + {"zvl128b", ISA_SPEC_CLASS_NONE, 1, 0}, + {"zvl256b", ISA_SPEC_CLASS_NONE, 1, 0}, + {"zvl512b", ISA_SPEC_CLASS_NONE, 1, 0}, + {"zvl1024b", ISA_SPEC_CLASS_NONE, 1, 0}, + {"zvl2048b", ISA_SPEC_CLASS_NONE, 1, 0}, + {"zvl4096b", ISA_SPEC_CLASS_NONE, 1, 0}, + {"zvl8192b", ISA_SPEC_CLASS_NONE, 1, 0}, + {"zvl16384b", ISA_SPEC_CLASS_NONE, 1, 0}, + {"zvl32768b", ISA_SPEC_CLASS_NONE, 1, 0}, + {"zvl65536b", ISA_SPEC_CLASS_NONE, 1, 0}, + /* Terminate the list. */ {NULL, ISA_SPEC_CLASS_NONE, 0, 0} }; @@ -965,6 +1019,7 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] = {"f", &gcc_options::x_target_flags, MASK_HARD_FLOAT}, {"d", &gcc_options::x_target_flags, MASK_DOUBLE_FLOAT}, {"c", &gcc_options::x_target_flags, MASK_RVC}, + {"v", &gcc_options::x_target_flags, MASK_VECTOR}, {"zicsr", &gcc_options::x_riscv_zi_subext, MASK_ZICSR}, {"zifencei", &gcc_options::x_riscv_zi_subext, MASK_ZIFENCEI}, @@ -985,6 +1040,37 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] = {"zksh", &gcc_options::x_riscv_zk_subext, MASK_ZKSH}, {"zkt", &gcc_options::x_riscv_zk_subext, MASK_ZKT}, + {"zve32x", &gcc_options::x_target_flags, MASK_VECTOR}, + {"zve32f", &gcc_options::x_target_flags, MASK_VECTOR}, + {"zve64x", &gcc_options::x_target_flags, MASK_VECTOR}, + {"zve64f", &gcc_options::x_target_flags, MASK_VECTOR}, + {"zve64d", &gcc_options::x_target_flags, MASK_VECTOR}, + + /* We don't need to put complete EEW/EEW_FP info here, due to the + implication relation of vector extension. + e.g. v -> zve64d ... zve32x, so v has set MASK_VECTOR_EEW_FP_64, + MASK_VECTOR_EEW_FP_32, MASK_VECTOR_EEW_64 and MASK_VECTOR_EEW_32 + due to the extension implication. */ + {"zve32x", &gcc_options::x_riscv_vector_eew_flags, MASK_VECTOR_EEW_32}, + {"zve32f", &gcc_options::x_riscv_vector_eew_flags, MASK_VECTOR_EEW_FP_32}, + {"zve64x", &gcc_options::x_riscv_vector_eew_flags, MASK_VECTOR_EEW_64}, + {"zve64f", &gcc_options::x_riscv_vector_eew_flags, MASK_VECTOR_EEW_FP_32}, + {"zve64d", &gcc_options::x_riscv_vector_eew_flags, MASK_VECTOR_EEW_FP_64}, + + {"zvl32b", &gcc_options::x_riscv_zvl_flags, MASK_ZVL32B}, + {"zvl64b", &gcc_options::x_riscv_zvl_flags, MASK_ZVL64B}, + {"zvl128b", &gcc_options::x_riscv_zvl_flags, MASK_ZVL128B}, + {"zvl256b", &gcc_options::x_riscv_zvl_flags, MASK_ZVL256B}, + {"zvl512b", &gcc_options::x_riscv_zvl_flags, MASK_ZVL512B}, + {"zvl1024b", &gcc_options::x_riscv_zvl_flags, MASK_ZVL1024B}, + {"zvl2048b", &gcc_options::x_riscv_zvl_flags, MASK_ZVL2048B}, + {"zvl4096b", &gcc_options::x_riscv_zvl_flags, MASK_ZVL4096B}, + {"zvl8192b", &gcc_options::x_riscv_zvl_flags, MASK_ZVL8192B}, + {"zvl16384b", &gcc_options::x_riscv_zvl_flags, MASK_ZVL16384B}, + {"zvl32768b", &gcc_options::x_riscv_zvl_flags, MASK_ZVL32768B}, + {"zvl65536b", &gcc_options::x_riscv_zvl_flags, MASK_ZVL65536B}, + + {NULL, NULL, 0} }; diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h index 6a0354d..929e4e3 100644 --- a/gcc/config/riscv/riscv-opts.h +++ b/gcc/config/riscv/riscv-opts.h @@ -105,4 +105,35 @@ enum stack_protector_guard { #define TARGET_ZKSH ((riscv_zk_subext & MASK_ZKSH) != 0) #define TARGET_ZKT ((riscv_zk_subext & MASK_ZKT) != 0) +#define MASK_VECTOR_EEW_32 (1 << 0) +#define MASK_VECTOR_EEW_64 (1 << 1) +#define MASK_VECTOR_EEW_FP_32 (1 << 2) +#define MASK_VECTOR_EEW_FP_64 (1 << 3) + +#define MASK_ZVL32B (1 << 0) +#define MASK_ZVL64B (1 << 1) +#define MASK_ZVL128B (1 << 2) +#define MASK_ZVL256B (1 << 3) +#define MASK_ZVL512B (1 << 4) +#define MASK_ZVL1024B (1 << 5) +#define MASK_ZVL2048B (1 << 6) +#define MASK_ZVL4096B (1 << 7) +#define MASK_ZVL8192B (1 << 8) +#define MASK_ZVL16384B (1 << 9) +#define MASK_ZVL32768B (1 << 10) +#define MASK_ZVL65536B (1 << 11) + +#define TARGET_ZVL32B ((riscv_zvl_flags & MASK_ZVL32B) != 0) +#define TARGET_ZVL64B ((riscv_zvl_flags & MASK_ZVL64B) != 0) +#define TARGET_ZVL128B ((riscv_zvl_flags & MASK_ZVL128B) != 0) +#define TARGET_ZVL256B ((riscv_zvl_flags & MASK_ZVL256B) != 0) +#define TARGET_ZVL512B ((riscv_zvl_flags & MASK_ZVL512B) != 0) +#define TARGET_ZVL1024B ((riscv_zvl_flags & MASK_ZVL1024B) != 0) +#define TARGET_ZVL2048B ((riscv_zvl_flags & MASK_ZVL2048B) != 0) +#define TARGET_ZVL4096B ((riscv_zvl_flags & MASK_ZVL4096B) != 0) +#define TARGET_ZVL8192B ((riscv_zvl_flags & MASK_ZVL8192B) != 0) +#define TARGET_ZVL16384B ((riscv_zvl_flags & MASK_ZVL16384B) != 0) +#define TARGET_ZVL32768B ((riscv_zvl_flags & MASK_ZVL32768B) != 0) +#define TARGET_ZVL65536B ((riscv_zvl_flags & MASK_ZVL65536B) != 0) + #endif /* ! GCC_RISCV_OPTS_H */ diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt index 486121b..9fffc08 100644 --- a/gcc/config/riscv/riscv.opt +++ b/gcc/config/riscv/riscv.opt @@ -146,6 +146,8 @@ Mask(RVC) Mask(RVE) +Mask(VECTOR) + mriscv-attribute Target Var(riscv_emit_attribute_p) Init(-1) Emit RISC-V ELF attribute. @@ -201,6 +203,12 @@ int riscv_zb_subext TargetVariable int riscv_zk_subext +TargetVariable +int riscv_vector_eew_flags + +TargetVariable +int riscv_zvl_flags + Enum Name(isa_spec_class) Type(enum riscv_isa_spec_class) Supported ISA specs (for use with the -misa-spec= option): diff --git a/gcc/testsuite/gcc.target/riscv/predef-14.c b/gcc/testsuite/gcc.target/riscv/predef-14.c new file mode 100644 index 0000000..108fc0c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/predef-14.c @@ -0,0 +1,83 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=rv32iv -mabi=ilp32 -mcmodel=medlow -misa-spec=2.2" } */ + +int main () { + +#ifndef __riscv_arch_test +#error "__riscv_arch_test" +#endif + +#if __riscv_xlen != 32 +#error "__riscv_xlen" +#endif + +#if !defined(__riscv_i) +#error "__riscv_i" +#endif + +#if defined(__riscv_c) +#error "__riscv_c" +#endif + +#if defined(__riscv_e) +#error "__riscv_e" +#endif + +#if defined(__riscv_a) +#error "__riscv_a" +#endif + +#if defined(__riscv_m) +#error "__riscv_m" +#endif + +#if !defined(__riscv_f) +#error "__riscv_f" +#endif + +#if !defined(__riscv_d) +#error "__riscv_d" +#endif + +#if !defined(__riscv_v) +#error "__riscv_v" +#endif + +#if !defined(__riscv_zvl32b) +#error "__riscv_zvl32b" +#endif + +#if !defined(__riscv_zvl64b) +#error "__riscv_zvl64b" +#endif + +#if !defined(__riscv_zvl128b) +#error "__riscv_zvl128b" +#endif + +#if defined(__riscv_zvl256b) +#error "__riscv_zvl256b" +#endif + +#if !defined(__riscv_zve32x) +#error "__riscv_zve32x" +#endif + +#if !defined(__riscv_zve32f) +#error "__riscv_zve32f" +#endif + +#if !defined(__riscv_zve64x) +#error "__riscv_zve64x" +#endif + +#if !defined(__riscv_zve64f) +#error "__riscv_zve64f" +#endif + +#if !defined(__riscv_zve64d) +#error "__riscv_zve64d" +#endif + + return 0; +} diff --git a/gcc/testsuite/gcc.target/riscv/predef-15.c b/gcc/testsuite/gcc.target/riscv/predef-15.c new file mode 100644 index 0000000..a37c457 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/predef-15.c @@ -0,0 +1,91 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=rv64iv_zvl512b -mabi=lp64 -mcmodel=medlow -misa-spec=2.2" } */ + +int main () { + +#ifndef __riscv_arch_test +#error "__riscv_arch_test" +#endif + +#if __riscv_xlen != 64 +#error "__riscv_xlen" +#endif + +#if !defined(__riscv_i) +#error "__riscv_i" +#endif + +#if defined(__riscv_c) +#error "__riscv_c" +#endif + +#if defined(__riscv_e) +#error "__riscv_e" +#endif + +#if defined(__riscv_a) +#error "__riscv_a" +#endif + +#if defined(__riscv_m) +#error "__riscv_m" +#endif + +#if !defined(__riscv_f) +#error "__riscv_f" +#endif + +#if !defined(__riscv_d) +#error "__riscv_d" +#endif + +#if !defined(__riscv_v) +#error "__riscv_v" +#endif + +#if !defined(__riscv_zvl32b) +#error "__riscv_zvl32b" +#endif + +#if !defined(__riscv_zvl64b) +#error "__riscv_zvl64b" +#endif + +#if !defined(__riscv_zvl128b) +#error "__riscv_zvl128b" +#endif + +#if !defined(__riscv_zvl256b) +#error "__riscv_zvl256b" +#endif + +#if !defined(__riscv_zvl512b) +#error "__riscv_zvl512b" +#endif + +#if defined(__riscv_zvl1024b) +#error "__riscv_zvl1024b" +#endif + +#if !defined(__riscv_zve32x) +#error "__riscv_zve32x" +#endif + +#if !defined(__riscv_zve32f) +#error "__riscv_zve32f" +#endif + +#if !defined(__riscv_zve64x) +#error "__riscv_zve64x" +#endif + +#if !defined(__riscv_zve64f) +#error "__riscv_zve64f" +#endif + +#if !defined(__riscv_zve64d) +#error "__riscv_zve64d" +#endif + + return 0; +} diff --git a/gcc/testsuite/gcc.target/riscv/predef-16.c b/gcc/testsuite/gcc.target/riscv/predef-16.c new file mode 100644 index 0000000..6c5c874 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/predef-16.c @@ -0,0 +1,91 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=rv64i_zve64f -mabi=lp64 -mcmodel=medlow -misa-spec=2.2" } */ + +int main () { + +#ifndef __riscv_arch_test +#error "__riscv_arch_test" +#endif + +#if __riscv_xlen != 64 +#error "__riscv_xlen" +#endif + +#if !defined(__riscv_i) +#error "__riscv_i" +#endif + +#if defined(__riscv_c) +#error "__riscv_c" +#endif + +#if defined(__riscv_e) +#error "__riscv_e" +#endif + +#if defined(__riscv_a) +#error "__riscv_a" +#endif + +#if defined(__riscv_m) +#error "__riscv_m" +#endif + +#if !defined(__riscv_f) +#error "__riscv_f" +#endif + +#if defined(__riscv_d) +#error "__riscv_d" +#endif + +#if defined(__riscv_v) +#error "__riscv_v" +#endif + +#if !defined(__riscv_zvl32b) +#error "__riscv_zvl32b" +#endif + +#if !defined(__riscv_zvl64b) +#error "__riscv_zvl64b" +#endif + +#if defined(__riscv_zvl128b) +#error "__riscv_zvl128b" +#endif + +#if defined(__riscv_zvl256b) +#error "__riscv_zvl256b" +#endif + +#if defined(__riscv_zvl512b) +#error "__riscv_zvl512b" +#endif + +#if defined(__riscv_zvl1024b) +#error "__riscv_zvl1024b" +#endif + +#if !defined(__riscv_zve32x) +#error "__riscv_zve32x" +#endif + +#if !defined(__riscv_zve32f) +#error "__riscv_zve32f" +#endif + +#if !defined(__riscv_zve64x) +#error "__riscv_zve64x" +#endif + +#if !defined(__riscv_zve64f) +#error "__riscv_zve64f" +#endif + +#if defined(__riscv_zve64d) +#error "__riscv_zve64d" +#endif + + return 0; +} -- 2.7.4