From e7d898a26891a29518992fc137763d9fe77d1b0a Mon Sep 17 00:00:00 2001 From: Samuel Pitoiset Date: Tue, 15 Dec 2020 18:37:48 +0100 Subject: [PATCH] radv: check if HTILE is enabled per-level instead of the entire image With HTILE mipmaps support, we should check if the base level currently in use supports compression. Signed-off-by: Samuel Pitoiset Reviewed-by: Bas Nieuwenhuizen Part-of: --- src/amd/vulkan/radv_cmd_buffer.c | 4 ++-- src/amd/vulkan/radv_meta_clear.c | 3 ++- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index 6e7cef3..2b3880c 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -2058,7 +2058,7 @@ radv_update_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer, }; struct radv_image *image = iview->image; - assert(radv_image_has_htile(image)); + assert(radv_htile_enabled(image, range.baseMipLevel)); radv_set_ds_clear_metadata(cmd_buffer, iview->image, &range, ds_clear_value, aspects); @@ -6156,7 +6156,7 @@ static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffe { struct radv_device *device = cmd_buffer->device; - if (!radv_image_has_htile(image)) + if (!radv_htile_enabled(image, range->baseMipLevel)) return; if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) { diff --git a/src/amd/vulkan/radv_meta_clear.c b/src/amd/vulkan/radv_meta_clear.c index 65f4590..4f84347 100644 --- a/src/amd/vulkan/radv_meta_clear.c +++ b/src/amd/vulkan/radv_meta_clear.c @@ -699,7 +699,8 @@ static bool depth_view_can_fast_clear(struct radv_cmd_buffer *cmd_buffer, clear_value.depth != 1.0) || ((aspects & VK_IMAGE_ASPECT_STENCIL_BIT) && clear_value.stencil != 0))) return false; - if (iview->base_mip == 0 && + if (radv_htile_enabled(iview->image, iview->base_mip) && + iview->base_mip == 0 && iview->base_layer == 0 && iview->layer_count == iview->image->info.array_size && radv_layout_is_htile_compressed(cmd_buffer->device, iview->image, layout, in_render_loop, queue_mask) && -- 2.7.4