From e7a68fd93e822ebb8069cb8f675b369ccb879721 Mon Sep 17 00:00:00 2001 From: Simon Pilgrim Date: Tue, 23 Apr 2019 11:11:34 +0000 Subject: [PATCH] Fix MSVC "32-bit shift implicitly converted to 64 bits" warning. NFCI. llvm-svn: 358969 --- llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp index 23d8adc..3b27b9f 100644 --- a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp +++ b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp @@ -710,7 +710,7 @@ bool AArch64DAGToDAGISel::SelectAddrModeIndexedBitWidth(SDValue N, bool IsSigned if (IsSignedImm) { int64_t RHSC = RHS->getSExtValue(); unsigned Scale = Log2_32(Size); - int64_t Range = 0x1 << (BW-1); + int64_t Range = 0x1LL << (BW - 1); if ((RHSC & (Size - 1)) == 0 && RHSC >= -(Range << Scale) && RHSC < (Range << Scale)) { @@ -726,7 +726,7 @@ bool AArch64DAGToDAGISel::SelectAddrModeIndexedBitWidth(SDValue N, bool IsSigned // unsigned Immediate uint64_t RHSC = RHS->getZExtValue(); unsigned Scale = Log2_32(Size); - uint64_t Range = 0x1 << BW; + uint64_t Range = 0x1ULL << BW; if ((RHSC & (Size - 1)) == 0 && RHSC < (Range << Scale)) { Base = N.getOperand(0); -- 2.7.4