From e7a306310b0bfbd97cdce8f77686b6453fc76bca Mon Sep 17 00:00:00 2001 From: Dmitry Preobrazhensky Date: Fri, 30 Dec 2022 16:29:47 +0300 Subject: [PATCH] [AMDGPU][GFX11] Correct tied src2 of v_fmac_f16_e64 src2 was incorrectly defined as VSrc_f16 but it is tied to dst which is VGPR_32. As a result, disassembler failed to decode src2. Differential Revision: https://reviews.llvm.org/D140299 --- llvm/lib/Target/AMDGPU/VOP2Instructions.td | 2 ++ llvm/test/CodeGen/AMDGPU/fmul-2-combine-multi-use.ll | 2 +- llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_from_vop2.txt | 6 ++++++ 3 files changed, 9 insertions(+), 1 deletion(-) diff --git a/llvm/lib/Target/AMDGPU/VOP2Instructions.td b/llvm/lib/Target/AMDGPU/VOP2Instructions.td index 8d4676e..4dd4564 100644 --- a/llvm/lib/Target/AMDGPU/VOP2Instructions.td +++ b/llvm/lib/Target/AMDGPU/VOP2Instructions.td @@ -495,6 +495,8 @@ def VOP_MAC_F16_t16 : VOP_MAC { Src1ModDPP:$src1_modifiers, Src1DPP:$src1, getVregSrcForVT_t16.ret:$src2, // stub argument dpp8:$dpp8, FI:$fi); + let Src2Mod = FP32InputMods; // dummy unused modifiers + let Src2RC64 = VGPRSrc_32; // stub argument } def VOP_MAC_F32 : VOP_MAC ; let HasExtDPP = 0, HasExt32BitDPP = 0 in diff --git a/llvm/test/CodeGen/AMDGPU/fmul-2-combine-multi-use.ll b/llvm/test/CodeGen/AMDGPU/fmul-2-combine-multi-use.ll index b498d87..0aaa51f 100644 --- a/llvm/test/CodeGen/AMDGPU/fmul-2-combine-multi-use.ll +++ b/llvm/test/CodeGen/AMDGPU/fmul-2-combine-multi-use.ll @@ -156,7 +156,7 @@ define amdgpu_kernel void @multiple_fadd_use_test_f16(ptr addrspace(1) %out, i16 ; VI-DENORM-DAG: v_fma_f16 [[MAD:v[0-9]+]], [[X]], 2.0, v{{[0-9]+}} ; GFX10-FLUSH-DAG: v_add_f16_e32 [[MAD:v[0-9]+]], s{{[0-9]+}}, [[MUL2]] ; GFX10-DENORM-DAG: v_fma_f16 [[MAD:v[0-9]+]], [[X]], 2.0, s{{[0-9]+}} -; GFX11-DENORM-DAG: v_fmac_f16_e64 [[MAD:v[0-9]+]], [[X]], 2.0 +; GFX11-DENORM-DAG: v_fma_f16 [[MAD:v[0-9]+]], [[X]], 2.0, s{{[0-9]+}} ; GCN-DAG: buffer_store_{{short|b16}} [[MUL2]] ; GCN-DAG: buffer_store_{{short|b16}} [[MAD]] diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_from_vop2.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_from_vop2.txt index ae57754..3141e8f 100644 --- a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_from_vop2.txt +++ b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_from_vop2.txt @@ -471,6 +471,12 @@ # GFX11: v_fmac_f16_e64 v255, -|0xfe0b|, -|vcc_hi| clamp div:2 ; encoding: [0xff,0x83,0x36,0xd5,0xff,0xd6,0x00,0x78,0x0b,0xfe,0x00,0x00] 0xff,0x83,0x36,0xd5,0xff,0xd6,0x00,0x78,0x0b,0xfe,0x00,0x00 +# GFX11: v_fmac_f16_e64 v250, -|0xfe0b|, -|vcc_hi| clamp div:2 ; encoding: [0xfa,0x83,0x36,0xd5,0xff,0xd6,0x00,0x78,0x0b,0xfe,0x00,0x00] +0xfa,0x83,0x36,0xd5,0xff,0xd6,0x00,0x78,0x0b,0xfe,0x00,0x00 + +# GFX11: v_fmac_f16_e64 v255, v1, v2 ; encoding: [0xff,0x00,0x36,0xd5,0x01,0x05,0x02,0x00] +0xff,0x00,0x36,0xd5,0x01,0x05,0x02,0x00 + # GFX11: v_fmac_f32_e64 v5, v1, v2 ; encoding: [0x05,0x00,0x2b,0xd5,0x01,0x05,0x02,0x00] 0x05,0x00,0x2b,0xd5,0x01,0x05,0x02,0x00 -- 2.7.4