From e790b2b7443adb601ce54a63e64fdfc670c8df45 Mon Sep 17 00:00:00 2001 From: Jay Foad Date: Thu, 5 Aug 2021 09:35:49 +0100 Subject: [PATCH] [AMDGPU] Make more use of getHiHalf64 and split64BitValue. NFCI. --- llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp | 24 ++++++------------------ 1 file changed, 6 insertions(+), 18 deletions(-) diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp index 4fefc41..9b65ed1 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp @@ -2211,13 +2211,10 @@ SDValue AMDGPUTargetLowering::LowerFTRUNC(SDValue Op, SelectionDAG &DAG) const { assert(Op.getValueType() == MVT::f64); const SDValue Zero = DAG.getConstant(0, SL, MVT::i32); - const SDValue One = DAG.getConstant(1, SL, MVT::i32); - - SDValue VecSrc = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Src); // Extract the upper half, since this is where we will find the sign and // exponent. - SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, VecSrc, One); + SDValue Hi = getHiHalf64(Src, DAG); SDValue Exp = extractF64Exponent(Hi, SL, DAG); @@ -2397,13 +2394,10 @@ SDValue AMDGPUTargetLowering::LowerCTLZ_CTTZ(SDValue Op, SelectionDAG &DAG) cons if (ZeroUndef && Src.getValueType() == MVT::i32) return DAG.getNode(NewOpc, SL, MVT::i32, Src); - SDValue Vec = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Src); - const SDValue Zero = DAG.getConstant(0, SL, MVT::i32); - const SDValue One = DAG.getConstant(1, SL, MVT::i32); - SDValue Lo = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Vec, Zero); - SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Vec, One); + SDValue Lo, Hi; + std::tie(Lo, Hi) = split64BitValue(Src, DAG); EVT SetCCVT = getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), MVT::i32); @@ -2573,12 +2567,8 @@ SDValue AMDGPUTargetLowering::LowerINT_TO_FP64(SDValue Op, SelectionDAG &DAG, SDLoc SL(Op); SDValue Src = Op.getOperand(0); - SDValue BC = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Src); - - SDValue Lo = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, BC, - DAG.getConstant(0, SL, MVT::i32)); - SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, BC, - DAG.getConstant(1, SL, MVT::i32)); + SDValue Lo, Hi; + std::tie(Lo, Hi) = split64BitValue(Src, DAG); SDValue CvtHi = DAG.getNode(Signed ? ISD::SINT_TO_FP : ISD::UINT_TO_FP, SL, MVT::f64, Hi); @@ -3313,11 +3303,9 @@ SDValue AMDGPUTargetLowering::performSrlCombine(SDNode *N, // srl i64:x, C for C >= 32 // => // build_pair (srl hi_32(x), C - 32), 0 - SDValue One = DAG.getConstant(1, SL, MVT::i32); SDValue Zero = DAG.getConstant(0, SL, MVT::i32); - SDValue VecOp = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, LHS); - SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, VecOp, One); + SDValue Hi = getHiHalf64(LHS, DAG); SDValue NewConst = DAG.getConstant(ShiftAmt - 32, SL, MVT::i32); SDValue NewShift = DAG.getNode(ISD::SRL, SL, MVT::i32, Hi, NewConst); -- 2.7.4