From e76fedac70a3a688b5621639003700dad9c0c144 Mon Sep 17 00:00:00 2001 From: Jaehoon Chung Date: Fri, 28 Apr 2023 13:00:11 +0900 Subject: [PATCH] RISC-V: fix riscv64 extension isa problem During building with tizen gcc, the below message is displayed. [ 33s] arch/riscv/lib/cache.c:12: Error: unrecognized opcode `fence.i', extension `zifencei' required [ 33s] make[1]: *** [scripts/Makefile.build:257: arch/riscv/lib/cache.o] Error 1 [ 33s] make[1]: *** Waiting for unfinished jobs.... [ 33s] CC common/miiphyutil.o [ 34s] CC boot/image.o [ 34s] CC boot/image-board.o Older gcc doesn't support some isa extensions for riscv. (Since GCC 11.1, it's supported.) This patch is refered to below commit of linux-starfive repo. commit e6303a1c7cf531457aca1ff35f3d3ee38977eca2 Author: Marek Szulc Date: Fri Aug 19 12:29:48 2022 +0200 riscv: fix riscv64 unrecognized opcode build error Change-Id: Ib4f52134bad8d9f1971d4d8fb9f757d2fa9cfb1e Signed-off-by: Jaehoon Chung --- arch/riscv/Makefile | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile index 4963b5109b..1322ba5af4 100644 --- a/arch/riscv/Makefile +++ b/arch/riscv/Makefile @@ -42,6 +42,8 @@ ifeq ($(toolchain-need-zicsr-zifencei),y) RISCV_MARCH := $(RISCV_MARCH)_zicsr_zifencei endif +RISCV_MARCH := ${subst imafd,g,${RISCV_MARCH}} + ARCH_FLAGS = -march=$(RISCV_MARCH) -mabi=$(ABI) \ -mcmodel=$(CMODEL) -- 2.34.1