From e741eb2c7d85b0884d68e856f4391341a6c6f7e3 Mon Sep 17 00:00:00 2001 From: Vasileios Kalintiris Date: Mon, 2 Mar 2015 12:47:32 +0000 Subject: [PATCH] [mips] Optimize conditional moves where RHS is zero. Summary: When the RHS of a conditional move node is zero, we can utilize the $zero register by inverting the conditional move instruction and by swapping the order of its True/False operands. Reviewers: dsanders Differential Revision: http://reviews.llvm.org/D7945 llvm-svn: 230956 --- llvm/lib/Target/Mips/MipsISelLowering.cpp | 32 ++++ llvm/test/CodeGen/Mips/fcmp.ll | 302 +++++++++++++----------------- 2 files changed, 159 insertions(+), 175 deletions(-) diff --git a/llvm/lib/Target/Mips/MipsISelLowering.cpp b/llvm/lib/Target/Mips/MipsISelLowering.cpp index 9253b2e..0b54d59 100644 --- a/llvm/lib/Target/Mips/MipsISelLowering.cpp +++ b/llvm/lib/Target/Mips/MipsISelLowering.cpp @@ -617,6 +617,35 @@ static SDValue performSELECTCombine(SDNode *N, SelectionDAG &DAG, return SDValue(); } +static SDValue performCMovFPCombine(SDNode *N, SelectionDAG &DAG, + TargetLowering::DAGCombinerInfo &DCI, + const MipsSubtarget &Subtarget) { + if (DCI.isBeforeLegalizeOps()) + return SDValue(); + + SDValue ValueIfTrue = N->getOperand(0), ValueIfFalse = N->getOperand(2); + + ConstantSDNode *FalseC = dyn_cast(ValueIfFalse); + if (!FalseC || FalseC->getZExtValue()) + return SDValue(); + + // Since RHS (False) is 0, we swap the order of the True/False operands + // (obviously also inverting the condition) so that we can + // take advantage of conditional moves using the $0 register. + // Example: + // return (a != 0) ? x : 0; + // load $reg, x + // movz $reg, $0, a + unsigned Opc = (N->getOpcode() == MipsISD::CMovFP_T) ? MipsISD::CMovFP_F : + MipsISD::CMovFP_T; + + SDValue FCC = N->getOperand(1), Glue = N->getOperand(3); + SDVTList VTs = DAG.getVTList(FCC.getValueType(), ValueIfTrue.getValueType(), + ValueIfFalse.getValueType(), + Glue.getValueType()); + return DAG.getNode(Opc, SDLoc(N), VTs, ValueIfFalse, FCC, ValueIfTrue, Glue); +} + static SDValue performANDCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget) { @@ -750,6 +779,9 @@ SDValue MipsTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) return performDivRemCombine(N, DAG, DCI, Subtarget); case ISD::SELECT: return performSELECTCombine(N, DAG, DCI, Subtarget); + case MipsISD::CMovFP_F: + case MipsISD::CMovFP_T: + return performCMovFPCombine(N, DAG, DCI, Subtarget); case ISD::AND: return performANDCombine(N, DAG, DCI, Subtarget); case ISD::OR: diff --git a/llvm/test/CodeGen/Mips/fcmp.ll b/llvm/test/CodeGen/Mips/fcmp.ll index 8e83b00..aa1f09bf 100644 --- a/llvm/test/CodeGen/Mips/fcmp.ll +++ b/llvm/test/CodeGen/Mips/fcmp.ll @@ -1,10 +1,17 @@ -; RUN: llc < %s -march=mipsel -mcpu=mips32 | FileCheck %s -check-prefix=ALL -check-prefix=32-C -; RUN: llc < %s -march=mipsel -mcpu=mips32r2 | FileCheck %s -check-prefix=ALL -check-prefix=32-C -; RUN: llc < %s -march=mipsel -mcpu=mips32r6 | FileCheck %s -check-prefix=ALL -check-prefix=32-CMP -; RUN: llc < %s -march=mips64el -mcpu=mips4 | FileCheck %s -check-prefix=ALL -check-prefix=64-C -; RUN: llc < %s -march=mips64el -mcpu=mips64 | FileCheck %s -check-prefix=ALL -check-prefix=64-C -; RUN: llc < %s -march=mips64el -mcpu=mips64r2 | FileCheck %s -check-prefix=ALL -check-prefix=64-C -; RUN: llc < %s -march=mips64el -mcpu=mips64r6 | FileCheck %s -check-prefix=ALL -check-prefix=64-CMP +; RUN: llc < %s -march=mips -mcpu=mips32 | \ +; RUN: FileCheck %s -check-prefix=ALL -check-prefix=32-C +; RUN: llc < %s -march=mips -mcpu=mips32r2 | \ +; RUN: FileCheck %s -check-prefix=ALL -check-prefix=32-C +; RUN: llc < %s -march=mips -mcpu=mips32r6 | \ +; RUN: FileCheck %s -check-prefix=ALL -check-prefix=32-CMP +; RUN: llc < %s -march=mips64 -mcpu=mips4 | \ +; RUN: FileCheck %s -check-prefix=ALL -check-prefix=64-C +; RUN: llc < %s -march=mips64 -mcpu=mips64 | \ +; RUN: FileCheck %s -check-prefix=ALL -check-prefix=64-C +; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | \ +; RUN: FileCheck %s -check-prefix=ALL -check-prefix=64-C +; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | \ +; RUN: FileCheck %s -check-prefix=ALL -check-prefix=64-CMP define i32 @false_f32(float %a, float %b) nounwind { ; ALL-LABEL: false_f32: @@ -18,15 +25,13 @@ define i32 @false_f32(float %a, float %b) nounwind { define i32 @oeq_f32(float %a, float %b) nounwind { ; ALL-LABEL: oeq_f32: -; 32-C-DAG: addiu $[[T0:2]], $zero, 0 -; 32-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1 +; 32-C-DAG: addiu $2, $zero, 1 ; 32-C-DAG: c.eq.s $f12, $f14 -; 32-C-DAG: movt $[[T0]], $1, $fcc0 +; 32-C: movf $2, $zero, $fcc0 -; 64-C-DAG: addiu $[[T0:2]], $zero, 0 -; 64-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1 +; 64-C-DAG: addiu $2, $zero, 1 ; 64-C-DAG: c.eq.s $f12, $f13 -; 64-C-DAG: movt $[[T0]], $1, $fcc0 +; 64-C: movf $2, $zero, $fcc0 ; 32-CMP-DAG: cmp.eq.s $[[T0:f[0-9]+]], $f12, $f14 ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] @@ -44,15 +49,13 @@ define i32 @oeq_f32(float %a, float %b) nounwind { define i32 @ogt_f32(float %a, float %b) nounwind { ; ALL-LABEL: ogt_f32: -; 32-C-DAG: addiu $[[T0:2]], $zero, 0 -; 32-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1 +; 32-C-DAG: addiu $2, $zero, 1 ; 32-C-DAG: c.ule.s $f12, $f14 -; 32-C-DAG: movf $[[T0]], $1, $fcc0 +; 32-C: movt $2, $zero, $fcc0 -; 64-C-DAG: addiu $[[T0:2]], $zero, 0 -; 64-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1 +; 64-C-DAG: addiu $2, $zero, 1 ; 64-C-DAG: c.ule.s $f12, $f13 -; 64-C-DAG: movf $[[T0]], $1, $fcc0 +; 64-C: movt $2, $zero, $fcc0 ; 32-CMP-DAG: cmp.lt.s $[[T0:f[0-9]+]], $f14, $f12 ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] @@ -70,15 +73,13 @@ define i32 @ogt_f32(float %a, float %b) nounwind { define i32 @oge_f32(float %a, float %b) nounwind { ; ALL-LABEL: oge_f32: -; 32-C-DAG: addiu $[[T0:2]], $zero, 0 -; 32-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1 +; 32-C-DAG: addiu $2, $zero, 1 ; 32-C-DAG: c.ult.s $f12, $f14 -; 32-C-DAG: movf $[[T0]], $1, $fcc0 +; 32-C: movt $2, $zero, $fcc0 -; 64-C-DAG: addiu $[[T0:2]], $zero, 0 -; 64-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1 +; 64-C-DAG: addiu $2, $zero, 1 ; 64-C-DAG: c.ult.s $f12, $f13 -; 64-C-DAG: movf $[[T0]], $1, $fcc0 +; 64-C: movt $2, $zero, $fcc0 ; 32-CMP-DAG: cmp.le.s $[[T0:f[0-9]+]], $f14, $f12 ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] @@ -96,15 +97,13 @@ define i32 @oge_f32(float %a, float %b) nounwind { define i32 @olt_f32(float %a, float %b) nounwind { ; ALL-LABEL: olt_f32: -; 32-C-DAG: addiu $[[T0:2]], $zero, 0 -; 32-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1 +; 32-C-DAG: addiu $2, $zero, 1 ; 32-C-DAG: c.olt.s $f12, $f14 -; 32-C-DAG: movt $[[T0]], $1, $fcc0 +; 32-C: movf $2, $zero, $fcc0 -; 64-C-DAG: addiu $[[T0:2]], $zero, 0 -; 64-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1 +; 64-C-DAG: addiu $2, $zero, 1 ; 64-C-DAG: c.olt.s $f12, $f13 -; 64-C-DAG: movt $[[T0]], $1, $fcc0 +; 64-C: movf $2, $zero, $fcc0 ; 32-CMP-DAG: cmp.lt.s $[[T0:f[0-9]+]], $f12, $f14 ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] @@ -122,15 +121,13 @@ define i32 @olt_f32(float %a, float %b) nounwind { define i32 @ole_f32(float %a, float %b) nounwind { ; ALL-LABEL: ole_f32: -; 32-C-DAG: addiu $[[T0:2]], $zero, 0 -; 32-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1 +; 32-C-DAG: addiu $2, $zero, 1 ; 32-C-DAG: c.ole.s $f12, $f14 -; 32-C-DAG: movt $[[T0]], $1, $fcc0 +; 32-C: movf $2, $zero, $fcc0 -; 64-C-DAG: addiu $[[T0:2]], $zero, 0 -; 64-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1 +; 64-C-DAG: addiu $2, $zero, 1 ; 64-C-DAG: c.ole.s $f12, $f13 -; 64-C-DAG: movt $[[T0]], $1, $fcc0 +; 64-C: movf $2, $zero, $fcc0 ; 32-CMP-DAG: cmp.le.s $[[T0:f[0-9]+]], $f12, $f14 ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] @@ -148,15 +145,13 @@ define i32 @ole_f32(float %a, float %b) nounwind { define i32 @one_f32(float %a, float %b) nounwind { ; ALL-LABEL: one_f32: -; 32-C-DAG: addiu $[[T0:2]], $zero, 0 -; 32-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1 +; 32-C-DAG: addiu $2, $zero, 1 ; 32-C-DAG: c.ueq.s $f12, $f14 -; 32-C-DAG: movf $[[T0]], $1, $fcc0 +; 32-C: movt $2, $zero, $fcc0 -; 64-C-DAG: addiu $[[T0:2]], $zero, 0 -; 64-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1 +; 64-C-DAG: addiu $2, $zero, 1 ; 64-C-DAG: c.ueq.s $f12, $f13 -; 64-C-DAG: movf $[[T0]], $1, $fcc0 +; 64-C: movt $2, $zero, $fcc0 ; 32-CMP-DAG: cmp.ueq.s $[[T0:f[0-9]+]], $f12, $f14 ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] @@ -176,15 +171,13 @@ define i32 @one_f32(float %a, float %b) nounwind { define i32 @ord_f32(float %a, float %b) nounwind { ; ALL-LABEL: ord_f32: -; 32-C-DAG: addiu $[[T0:2]], $zero, 0 -; 32-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1 +; 32-C-DAG: addiu $2, $zero, 1 ; 32-C-DAG: c.un.s $f12, $f14 -; 32-C-DAG: movf $[[T0]], $1, $fcc0 +; 32-C: movt $2, $zero, $fcc0 -; 64-C-DAG: addiu $[[T0:2]], $zero, 0 -; 64-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1 +; 64-C-DAG: addiu $2, $zero, 1 ; 64-C-DAG: c.un.s $f12, $f13 -; 64-C-DAG: movf $[[T0]], $1, $fcc0 +; 64-C: movt $2, $zero, $fcc0 ; 32-CMP-DAG: cmp.un.s $[[T0:f[0-9]+]], $f12, $f14 ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] @@ -204,15 +197,13 @@ define i32 @ord_f32(float %a, float %b) nounwind { define i32 @ueq_f32(float %a, float %b) nounwind { ; ALL-LABEL: ueq_f32: -; 32-C-DAG: addiu $[[T0:2]], $zero, 0 -; 32-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1 +; 32-C-DAG: addiu $2, $zero, 1 ; 32-C-DAG: c.ueq.s $f12, $f14 -; 32-C-DAG: movt $[[T0]], $1, $fcc0 +; 32-C: movf $2, $zero, $fcc0 -; 64-C-DAG: addiu $[[T0:2]], $zero, 0 -; 64-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1 +; 64-C-DAG: addiu $2, $zero, 1 ; 64-C-DAG: c.ueq.s $f12, $f13 -; 64-C-DAG: movt $[[T0]], $1, $fcc0 +; 64-C: movf $2, $zero, $fcc0 ; 32-CMP-DAG: cmp.ueq.s $[[T0:f[0-9]+]], $f12, $f14 ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] @@ -230,15 +221,13 @@ define i32 @ueq_f32(float %a, float %b) nounwind { define i32 @ugt_f32(float %a, float %b) nounwind { ; ALL-LABEL: ugt_f32: -; 32-C-DAG: addiu $[[T0:2]], $zero, 0 -; 32-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1 +; 32-C-DAG: addiu $2, $zero, 1 ; 32-C-DAG: c.ole.s $f12, $f14 -; 32-C-DAG: movf $[[T0]], $1, $fcc0 +; 32-C: movt $2, $zero, $fcc0 -; 64-C-DAG: addiu $[[T0:2]], $zero, 0 -; 64-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1 +; 64-C-DAG: addiu $2, $zero, 1 ; 64-C-DAG: c.ole.s $f12, $f13 -; 64-C-DAG: movf $[[T0]], $1, $fcc0 +; 64-C: movt $2, $zero, $fcc0 ; 32-CMP-DAG: cmp.ult.s $[[T0:f[0-9]+]], $f14, $f12 ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] @@ -256,15 +245,13 @@ define i32 @ugt_f32(float %a, float %b) nounwind { define i32 @uge_f32(float %a, float %b) nounwind { ; ALL-LABEL: uge_f32: -; 32-C-DAG: addiu $[[T0:2]], $zero, 0 -; 32-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1 +; 32-C-DAG: addiu $2, $zero, 1 ; 32-C-DAG: c.olt.s $f12, $f14 -; 32-C-DAG: movf $[[T0]], $1, $fcc0 +; 32-C: movt $2, $zero, $fcc0 -; 64-C-DAG: addiu $[[T0:2]], $zero, 0 -; 64-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1 +; 64-C-DAG: addiu $2, $zero, 1 ; 64-C-DAG: c.olt.s $f12, $f13 -; 64-C-DAG: movf $[[T0]], $1, $fcc0 +; 64-C: movt $2, $zero, $fcc0 ; 32-CMP-DAG: cmp.ule.s $[[T0:f[0-9]+]], $f14, $f12 ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] @@ -282,15 +269,13 @@ define i32 @uge_f32(float %a, float %b) nounwind { define i32 @ult_f32(float %a, float %b) nounwind { ; ALL-LABEL: ult_f32: -; 32-C-DAG: addiu $[[T0:2]], $zero, 0 -; 32-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1 +; 32-C-DAG: addiu $2, $zero, 1 ; 32-C-DAG: c.ult.s $f12, $f14 -; 32-C-DAG: movt $[[T0]], $1, $fcc0 +; 32-C: movf $2, $zero, $fcc0 -; 64-C-DAG: addiu $[[T0:2]], $zero, 0 -; 64-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1 +; 64-C-DAG: addiu $2, $zero, 1 ; 64-C-DAG: c.ult.s $f12, $f13 -; 64-C-DAG: movt $[[T0]], $1, $fcc0 +; 64-C: movf $2, $zero, $fcc0 ; 32-CMP-DAG: cmp.ult.s $[[T0:f[0-9]+]], $f12, $f14 ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] @@ -300,6 +285,7 @@ define i32 @ult_f32(float %a, float %b) nounwind { ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 64-CMP-DAG: andi $2, $[[T1]], 1 + %1 = fcmp ult float %a, %b %2 = zext i1 %1 to i32 ret i32 %2 @@ -308,15 +294,13 @@ define i32 @ult_f32(float %a, float %b) nounwind { define i32 @ule_f32(float %a, float %b) nounwind { ; ALL-LABEL: ule_f32: -; 32-C-DAG: addiu $[[T0:2]], $zero, 0 -; 32-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1 +; 32-C-DAG: addiu $2, $zero, 1 ; 32-C-DAG: c.ule.s $f12, $f14 -; 32-C-DAG: movt $[[T0]], $1, $fcc0 +; 32-C: movf $2, $zero, $fcc0 -; 64-C-DAG: addiu $[[T0:2]], $zero, 0 -; 64-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1 +; 64-C-DAG: addiu $2, $zero, 1 ; 64-C-DAG: c.ule.s $f12, $f13 -; 64-C-DAG: movt $[[T0]], $1, $fcc0 +; 64-C: movf $2, $zero, $fcc0 ; 32-CMP-DAG: cmp.ule.s $[[T0:f[0-9]+]], $f12, $f14 ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] @@ -334,15 +318,13 @@ define i32 @ule_f32(float %a, float %b) nounwind { define i32 @une_f32(float %a, float %b) nounwind { ; ALL-LABEL: une_f32: -; 32-C-DAG: addiu $[[T0:2]], $zero, 0 -; 32-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1 +; 32-C-DAG: addiu $2, $zero, 1 ; 32-C-DAG: c.eq.s $f12, $f14 -; 32-C-DAG: movf $[[T0]], $1, $fcc0 +; 32-C: movt $2, $zero, $fcc0 -; 64-C-DAG: addiu $[[T0:2]], $zero, 0 -; 64-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1 +; 64-C-DAG: addiu $2, $zero, 1 ; 64-C-DAG: c.eq.s $f12, $f13 -; 64-C-DAG: movf $[[T0]], $1, $fcc0 +; 64-C: movt $2, $zero, $fcc0 ; 32-CMP-DAG: cmp.eq.s $[[T0:f[0-9]+]], $f12, $f14 ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] @@ -362,15 +344,13 @@ define i32 @une_f32(float %a, float %b) nounwind { define i32 @uno_f32(float %a, float %b) nounwind { ; ALL-LABEL: uno_f32: -; 32-C-DAG: addiu $[[T0:2]], $zero, 0 -; 32-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1 +; 32-C-DAG: addiu $2, $zero, 1 ; 32-C-DAG: c.un.s $f12, $f14 -; 32-C-DAG: movt $[[T0]], $1, $fcc0 +; 32-C: movf $2, $zero, $fcc0 -; 64-C-DAG: addiu $[[T0:2]], $zero, 0 -; 64-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1 +; 64-C-DAG: addiu $2, $zero, 1 ; 64-C-DAG: c.un.s $f12, $f13 -; 64-C-DAG: movt $[[T0]], $1, $fcc0 +; 64-C: movf $2, $zero, $fcc0 ; 32-CMP-DAG: cmp.un.s $[[T0:f[0-9]+]], $f12, $f14 ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] @@ -406,15 +386,13 @@ define i32 @false_f64(double %a, double %b) nounwind { define i32 @oeq_f64(double %a, double %b) nounwind { ; ALL-LABEL: oeq_f64: -; 32-C-DAG: addiu $[[T0:2]], $zero, 0 -; 32-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1 +; 32-C-DAG: addiu $2, $zero, 1 ; 32-C-DAG: c.eq.d $f12, $f14 -; 32-C-DAG: movt $[[T0]], $1, $fcc0 +; 32-C: movf $2, $zero, $fcc0 -; 64-C-DAG: addiu $[[T0:2]], $zero, 0 -; 64-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1 +; 64-C-DAG: addiu $2, $zero, 1 ; 64-C-DAG: c.eq.d $f12, $f13 -; 64-C-DAG: movt $[[T0]], $1, $fcc0 +; 64-C: movf $2, $zero, $fcc0 ; 32-CMP-DAG: cmp.eq.d $[[T0:f[0-9]+]], $f12, $f14 ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] @@ -432,15 +410,13 @@ define i32 @oeq_f64(double %a, double %b) nounwind { define i32 @ogt_f64(double %a, double %b) nounwind { ; ALL-LABEL: ogt_f64: -; 32-C-DAG: addiu $[[T0:2]], $zero, 0 -; 32-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1 +; 32-C-DAG: addiu $2, $zero, 1 ; 32-C-DAG: c.ule.d $f12, $f14 -; 32-C-DAG: movf $[[T0]], $1, $fcc0 +; 32-C: movt $2, $zero, $fcc0 -; 64-C-DAG: addiu $[[T0:2]], $zero, 0 -; 64-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1 +; 64-C-DAG: addiu $2, $zero, 1 ; 64-C-DAG: c.ule.d $f12, $f13 -; 64-C-DAG: movf $[[T0]], $1, $fcc0 +; 64-C: movt $2, $zero, $fcc0 ; 32-CMP-DAG: cmp.lt.d $[[T0:f[0-9]+]], $f14, $f12 ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] @@ -458,15 +434,13 @@ define i32 @ogt_f64(double %a, double %b) nounwind { define i32 @oge_f64(double %a, double %b) nounwind { ; ALL-LABEL: oge_f64: -; 32-C-DAG: addiu $[[T0:2]], $zero, 0 -; 32-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1 +; 32-C-DAG: addiu $2, $zero, 1 ; 32-C-DAG: c.ult.d $f12, $f14 -; 32-C-DAG: movf $[[T0]], $1, $fcc0 +; 32-C: movt $2, $zero, $fcc0 -; 64-C-DAG: addiu $[[T0:2]], $zero, 0 -; 64-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1 +; 64-C-DAG: addiu $2, $zero, 1 ; 64-C-DAG: c.ult.d $f12, $f13 -; 64-C-DAG: movf $[[T0]], $1, $fcc0 +; 64-C: movt $2, $zero, $fcc0 ; 32-CMP-DAG: cmp.le.d $[[T0:f[0-9]+]], $f14, $f12 ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] @@ -484,15 +458,13 @@ define i32 @oge_f64(double %a, double %b) nounwind { define i32 @olt_f64(double %a, double %b) nounwind { ; ALL-LABEL: olt_f64: -; 32-C-DAG: addiu $[[T0:2]], $zero, 0 -; 32-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1 +; 32-C-DAG: addiu $2, $zero, 1 ; 32-C-DAG: c.olt.d $f12, $f14 -; 32-C-DAG: movt $[[T0]], $1, $fcc0 +; 32-C: movf $2, $zero, $fcc0 -; 64-C-DAG: addiu $[[T0:2]], $zero, 0 -; 64-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1 +; 64-C-DAG: addiu $2, $zero, 1 ; 64-C-DAG: c.olt.d $f12, $f13 -; 64-C-DAG: movt $[[T0]], $1, $fcc0 +; 64-C: movf $2, $zero, $fcc0 ; 32-CMP-DAG: cmp.lt.d $[[T0:f[0-9]+]], $f12, $f14 ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] @@ -510,15 +482,13 @@ define i32 @olt_f64(double %a, double %b) nounwind { define i32 @ole_f64(double %a, double %b) nounwind { ; ALL-LABEL: ole_f64: -; 32-C-DAG: addiu $[[T0:2]], $zero, 0 -; 32-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1 +; 32-C-DAG: addiu $2, $zero, 1 ; 32-C-DAG: c.ole.d $f12, $f14 -; 32-C-DAG: movt $[[T0]], $1, $fcc0 +; 32-C: movf $2, $zero, $fcc0 -; 64-C-DAG: addiu $[[T0:2]], $zero, 0 -; 64-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1 +; 64-C-DAG: addiu $2, $zero, 1 ; 64-C-DAG: c.ole.d $f12, $f13 -; 64-C-DAG: movt $[[T0]], $1, $fcc0 +; 64-C: movf $2, $zero, $fcc0 ; 32-CMP-DAG: cmp.le.d $[[T0:f[0-9]+]], $f12, $f14 ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] @@ -536,15 +506,13 @@ define i32 @ole_f64(double %a, double %b) nounwind { define i32 @one_f64(double %a, double %b) nounwind { ; ALL-LABEL: one_f64: -; 32-C-DAG: addiu $[[T0:2]], $zero, 0 -; 32-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1 +; 32-C-DAG: addiu $2, $zero, 1 ; 32-C-DAG: c.ueq.d $f12, $f14 -; 32-C-DAG: movf $[[T0]], $1, $fcc0 +; 32-C: movt $2, $zero, $fcc0 -; 64-C-DAG: addiu $[[T0:2]], $zero, 0 -; 64-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1 +; 64-C-DAG: addiu $2, $zero, 1 ; 64-C-DAG: c.ueq.d $f12, $f13 -; 64-C-DAG: movf $[[T0]], $1, $fcc0 +; 64-C: movt $2, $zero, $fcc0 ; 32-CMP-DAG: cmp.ueq.d $[[T0:f[0-9]+]], $f12, $f14 ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] @@ -564,15 +532,13 @@ define i32 @one_f64(double %a, double %b) nounwind { define i32 @ord_f64(double %a, double %b) nounwind { ; ALL-LABEL: ord_f64: -; 32-C-DAG: addiu $[[T0:2]], $zero, 0 -; 32-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1 +; 32-C-DAG: addiu $2, $zero, 1 ; 32-C-DAG: c.un.d $f12, $f14 -; 32-C-DAG: movf $[[T0]], $1, $fcc0 +; 32-C: movt $2, $zero, $fcc0 -; 64-C-DAG: addiu $[[T0:2]], $zero, 0 -; 64-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1 +; 64-C-DAG: addiu $2, $zero, 1 ; 64-C-DAG: c.un.d $f12, $f13 -; 64-C-DAG: movf $[[T0]], $1, $fcc0 +; 64-C: movt $2, $zero, $fcc0 ; 32-CMP-DAG: cmp.un.d $[[T0:f[0-9]+]], $f12, $f14 ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] @@ -592,15 +558,13 @@ define i32 @ord_f64(double %a, double %b) nounwind { define i32 @ueq_f64(double %a, double %b) nounwind { ; ALL-LABEL: ueq_f64: -; 32-C-DAG: addiu $[[T0:2]], $zero, 0 -; 32-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1 +; 32-C-DAG: addiu $2, $zero, 1 ; 32-C-DAG: c.ueq.d $f12, $f14 -; 32-C-DAG: movt $[[T0]], $1, $fcc0 +; 32-C: movf $2, $zero, $fcc0 -; 64-C-DAG: addiu $[[T0:2]], $zero, 0 -; 64-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1 +; 64-C-DAG: addiu $2, $zero, 1 ; 64-C-DAG: c.ueq.d $f12, $f13 -; 64-C-DAG: movt $[[T0]], $1, $fcc0 +; 64-C: movf $2, $zero, $fcc0 ; 32-CMP-DAG: cmp.ueq.d $[[T0:f[0-9]+]], $f12, $f14 ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] @@ -618,15 +582,13 @@ define i32 @ueq_f64(double %a, double %b) nounwind { define i32 @ugt_f64(double %a, double %b) nounwind { ; ALL-LABEL: ugt_f64: -; 32-C-DAG: addiu $[[T0:2]], $zero, 0 -; 32-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1 +; 32-C-DAG: addiu $2, $zero, 1 ; 32-C-DAG: c.ole.d $f12, $f14 -; 32-C-DAG: movf $[[T0]], $1, $fcc0 +; 32-C: movt $2, $zero, $fcc0 -; 64-C-DAG: addiu $[[T0:2]], $zero, 0 -; 64-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1 +; 64-C-DAG: addiu $2, $zero, 1 ; 64-C-DAG: c.ole.d $f12, $f13 -; 64-C-DAG: movf $[[T0]], $1, $fcc0 +; 64-C: movt $2, $zero, $fcc0 ; 32-CMP-DAG: cmp.ult.d $[[T0:f[0-9]+]], $f14, $f12 ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] @@ -644,15 +606,13 @@ define i32 @ugt_f64(double %a, double %b) nounwind { define i32 @uge_f64(double %a, double %b) nounwind { ; ALL-LABEL: uge_f64: -; 32-C-DAG: addiu $[[T0:2]], $zero, 0 -; 32-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1 +; 32-C-DAG: addiu $2, $zero, 1 ; 32-C-DAG: c.olt.d $f12, $f14 -; 32-C-DAG: movf $[[T0]], $1, $fcc0 +; 32-C: movt $2, $zero, $fcc0 -; 64-C-DAG: addiu $[[T0:2]], $zero, 0 -; 64-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1 +; 64-C-DAG: addiu $2, $zero, 1 ; 64-C-DAG: c.olt.d $f12, $f13 -; 64-C-DAG: movf $[[T0]], $1, $fcc0 +; 64-C: movt $2, $zero, $fcc0 ; 32-CMP-DAG: cmp.ule.d $[[T0:f[0-9]+]], $f14, $f12 ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] @@ -670,15 +630,13 @@ define i32 @uge_f64(double %a, double %b) nounwind { define i32 @ult_f64(double %a, double %b) nounwind { ; ALL-LABEL: ult_f64: -; 32-C-DAG: addiu $[[T0:2]], $zero, 0 -; 32-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1 +; 32-C-DAG: addiu $2, $zero, 1 ; 32-C-DAG: c.ult.d $f12, $f14 -; 32-C-DAG: movt $[[T0]], $1, $fcc0 +; 32-C: movf $2, $zero, $fcc0 -; 64-C-DAG: addiu $[[T0:2]], $zero, 0 -; 64-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1 +; 64-C-DAG: addiu $2, $zero, 1 ; 64-C-DAG: c.ult.d $f12, $f13 -; 64-C-DAG: movt $[[T0]], $1, $fcc0 +; 64-C: movf $2, $zero, $fcc0 ; 32-CMP-DAG: cmp.ult.d $[[T0:f[0-9]+]], $f12, $f14 ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] @@ -696,15 +654,13 @@ define i32 @ult_f64(double %a, double %b) nounwind { define i32 @ule_f64(double %a, double %b) nounwind { ; ALL-LABEL: ule_f64: -; 32-C-DAG: addiu $[[T0:2]], $zero, 0 -; 32-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1 +; 32-C-DAG: addiu $2, $zero, 1 ; 32-C-DAG: c.ule.d $f12, $f14 -; 32-C-DAG: movt $[[T0]], $1, $fcc0 +; 32-C: movf $2, $zero, $fcc0 -; 64-C-DAG: addiu $[[T0:2]], $zero, 0 -; 64-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1 +; 64-C-DAG: addiu $2, $zero, 1 ; 64-C-DAG: c.ule.d $f12, $f13 -; 64-C-DAG: movt $[[T0]], $1, $fcc0 +; 64-C: movf $2, $zero, $fcc0 ; 32-CMP-DAG: cmp.ule.d $[[T0:f[0-9]+]], $f12, $f14 ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] @@ -722,15 +678,13 @@ define i32 @ule_f64(double %a, double %b) nounwind { define i32 @une_f64(double %a, double %b) nounwind { ; ALL-LABEL: une_f64: -; 32-C-DAG: addiu $[[T0:2]], $zero, 0 -; 32-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1 +; 32-C-DAG: addiu $2, $zero, 1 ; 32-C-DAG: c.eq.d $f12, $f14 -; 32-C-DAG: movf $[[T0]], $1, $fcc0 +; 32-C: movt $2, $zero, $fcc0 -; 64-C-DAG: addiu $[[T0:2]], $zero, 0 -; 64-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1 +; 64-C-DAG: addiu $2, $zero, 1 ; 64-C-DAG: c.eq.d $f12, $f13 -; 64-C-DAG: movf $[[T0]], $1, $fcc0 +; 64-C: movt $2, $zero, $fcc0 ; 32-CMP-DAG: cmp.eq.d $[[T0:f[0-9]+]], $f12, $f14 ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] @@ -750,15 +704,13 @@ define i32 @une_f64(double %a, double %b) nounwind { define i32 @uno_f64(double %a, double %b) nounwind { ; ALL-LABEL: uno_f64: -; 32-C-DAG: addiu $[[T0:2]], $zero, 0 -; 32-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1 +; 32-C-DAG: addiu $2, $zero, 1 ; 32-C-DAG: c.un.d $f12, $f14 -; 32-C-DAG: movt $[[T0]], $1, $fcc0 +; 32-C: movf $2, $zero, $fcc0 -; 64-C-DAG: addiu $[[T0:2]], $zero, 0 -; 64-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1 +; 64-C-DAG: addiu $2, $zero, 1 ; 64-C-DAG: c.un.d $f12, $f13 -; 64-C-DAG: movt $[[T0]], $1, $fcc0 +; 64-C: movf $2, $zero, $fcc0 ; 32-CMP-DAG: cmp.un.d $[[T0:f[0-9]+]], $f12, $f14 ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] -- 2.7.4