From e723b511e6e951444d2a646a23fc2e9cf4faecd4 Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Wed, 5 May 2021 13:55:24 -0400 Subject: [PATCH] GlobalISel: Update documentation --- llvm/docs/GlobalISel/IRTranslator.rst | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/llvm/docs/GlobalISel/IRTranslator.rst b/llvm/docs/GlobalISel/IRTranslator.rst index 9e12fdc..6268ebb 100644 --- a/llvm/docs/GlobalISel/IRTranslator.rst +++ b/llvm/docs/GlobalISel/IRTranslator.rst @@ -66,8 +66,8 @@ Aggregates worked much in this part of the codebase and it should have attention from someone more knowledgeable about it. -Aggregates are lowered to a single scalar vreg. -This differs from SelectionDAG's multiple vregs via ``GetValueVTs``. +Aggregates are lowered into multiple virtual registers, similar to +SelectionDAG's multiple vregs via ``GetValueVTs``. ``TODO``: As some of the bits are undef (padding), we should consider augmenting the -- 2.7.4